CN111009491B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN111009491B CN111009491B CN201910892512.6A CN201910892512A CN111009491B CN 111009491 B CN111009491 B CN 111009491B CN 201910892512 A CN201910892512 A CN 201910892512A CN 111009491 B CN111009491 B CN 111009491B
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Abstract
本公开提供了半导体装置及其制造方法。一种制造半导体装置的方法可包括:在衬底上形成包括模制层、缓冲层和支承层的模制结构;对模制结构执行各向异性蚀刻处理,以在模制结构中形成多个通孔;以及在通孔中形成多个底电极。缓冲层的氮含量在从模制层接近支承层的方向上增大。缓冲层的氧含量在从支承层接近模制层的方向上增大。
Description
相关申请的交叉引用
本申请要求于2018年10月4日在韩国知识产权局提交的韩国专利申请No.10-2018-0118213的优先权,该韩国专利申请的全部内容以引用方式全文并入本文中。
技术领域
本发明构思涉及一种半导体装置和/或其制造方法。例如,至少一些示例实施例涉及具有改善的可靠性的半导体装置和/或其制造方法。
背景技术
近年来对于电子工业中的轻、小、快、多功能、性能优异、可靠性高的产品(如手机和笔记本电脑)的需求不断增加。为了满足这些要求,需要增加集成度和提高半导体存储器装置的性能。
增加电容器的容量是提高高度集成的半导体存储器装置的可靠性的一种方法。电容器的底电极的高宽比越高,电容器的容量就越大。因此,已经对用于形成高高宽比电容器的处理技术进行了各种研究。
发明内容
本发明构思的一些示例实施例提供了一种具有改善的可靠性的半导体装置。
本发明构思的一些示例实施例提供了一种制造具有改善的可靠性的半导体装置的方法。
本发明构思的示例实施例不限于上述的这些,并且本领域技术人员将从下面的描述中清楚地理解上面未提及的其他示例实施例。
根据本发明构思的一些示例实施例,一种制造半导体装置的方法可包括:在衬底上形成包括模制层、缓冲层和支承层的模制结构,使得缓冲层的氮含量在从模制层接近支承层的方向上增大并且使得缓冲层的氧含量在从支承层接近模制层的方向上增大;对模制结构执行各向异性蚀刻处理,以在模制结构中形成多个通孔;以及在所述多个通孔中的对应通孔中形成多个底电极。
根据本发明构思的一些示例实施例,一种制造半导体装置的方法可包括:在衬底上形成模制层;使用第一气体和第二气体、通过逐渐减小第一气体的量和逐渐增大第二气体的量在模制层上形成缓冲层,第一气体包括氧并且第二气体包括氮;在缓冲层上形成支承层;通过执行各向异性蚀刻处理以顺序地各向异性地蚀刻支承层、缓冲层和模制层来形成通孔;以及在通孔中形成底电极。
根据本发明构思的一些示例实施例,一种半导体装置可包括:衬底上的底电极;底电极的侧壁上的第一支承层;第一支承层上方和底电极的侧壁上的第二支承层;以及覆盖底电极的侧壁和顶表面的电介质层。底电极可包括第一支承层与第二支承层之间的下区段以及下区段与第二支承层之间的上区段,上区段具有从下区段的侧壁突出的侧壁,以使得上区段的侧壁的中心具有尖点。
附图说明
图1A示出了显示根据本发明构思的一些示例实施例的半导体装置的平面图。
图1B示出了沿着图1A的线I-I'截取的显示根据本发明构思的一些示例实施例的半导体装置剖视图。
图1C示出了显示图1B的底电极的放大图。
图2A示出了显示根据本发明构思的一些示例实施例的半导体装置的平面图。
图2B示出了沿着图2A的线I-I'截取的显示根据本发明构思的一些示例实施例的半导体装置的剖视图。
图2C示出了显示图2B的底电极的放大图。
图3、图4、以及图6至图10示出了沿着图1A的线I-I’截取的显示根据本发明构思的一些示例实施例的制造半导体装置的方法的剖视图。
图5A示出了显示已经被蚀刻的缓冲层的放大图。
图5B示出了显示图4的部分A的放大图。
具体实施方式
图1A示出了显示根据本发明构思的一些示例实施例的半导体装置的平面图。图1B示出了沿着图1A的线I-I'截取的显示根据本发明构思的一些示例实施例的半导体装置的剖视图。图1C示出了显示图1B的底电极的放大图。
参照图1A和图1B,半导体装置可包括接触插塞110、底电极LE、第一支承层SL1、第二支承层SL2、电介质层130和顶电极UE。
接触插塞110可设置在衬底100上。衬底100可为半导体衬底,诸如硅(Si)衬底、锗(Ge)衬底、或硅锗(SiGe)衬底。接触插塞110可沿着第一方向X按照z字形布置。接触插塞110可包括半导体材料(例如,多晶硅)、金属半导体化合物(例如,硅化钨)、导电金属氮化物层(例如,氮化钛、氮化钽或氮化钨)和金属材料(例如,钛、钨或钽)中的一个或多个。
层间电介质层112可设置在衬底100上。层间电介质层112可填充彼此相邻的接触插塞110之间的间隙。层间电介质层112可包括氧化硅层、氮化硅层和氧氮化硅层中的一个或多个。虽然未示出,但是多条字线和与字线交叉的多条位线可形成在衬底100上和/或衬底100中。层间电介质层112可形成为覆盖字线和位线。杂质区可在字线中的每一个的相对侧上形成在衬底100中,并且接触插塞110中的每一个可连接至杂质区之一。
底电极LE可设置在接触插塞110上。底电极LE中的每一个可具有例如从衬底100的顶表面沿竖直方向延伸的柱形或圆柱形。底电极LE可包括以下中的一个或多个:金属材料(例如,钴、钛、镍、钨或钼)、金属氮化物层(例如,氮化钛(TiN)层、钛硅氮化物(TiSiN)层、钛铝氮化物(TiAlN)层、氮化钽(TaN)层、钽铝氮化物(TaAlN)层或氮化钨(WN)层)、贵金属层(例如,铂(Pt)、钌(Ru)或铱(Ir))、导电氧化物层(例如,PtO、RuO2、IrO2、SRO(SrRuO3)、BSRO((Ba,Sr)RuO3)、CRO(CaRuO3)、LSCo)、和金属硅化物层。下面将进一步详细讨论底电极LE。
第一支承层SL1可设置在底电极LE的侧壁上。第一支承层SL1可围绕底电极LE的侧壁。在第一支承层SL1上方,可在底电极LE的侧壁上设置第二支承层SL2。第二支承层SL2可围绕底电极LE的部分侧壁。第二支承层SL2可在竖直方向上与第一支承层SL1间隔开。第二支承层SL2可具有与底电极LE的顶表面的水平高度处于相同水平高度的顶表面。第一支承层SL1可比第二支承层SL2更靠近衬底100。第一支承层SL1和第二支承层SL2中的每一个可为例如碳氮化硅(SiCN)层。
一起参照图1A、图1B和图1C,底电极LE中的每一个可包括第一部分P1、第二部分P2、第三部分P3和第四部分P4。
第一部分P1可位于第一支承层SL1下方,第二部分P2可位于第一支承层SL1上方。可在第二部分P2上设有被设置为与第二支承层SL2水平重叠的第三部分P3,并且可在第一部分P1和第二部分P2之间设有被设置为与第一支承层SL1水平重叠的第四部分P4。
第二部分P2可包括下区段LP和上区段UP。下区段LP可设置在第一支承层SL1与第二支承层SL2之间,并且上区段UP可设置在下区段LP与第二支承层SL2之间。例如,下区段LP可设置在第四部分P4与第三部分P3之间,并且上区段UP可设置在下区段LP与第三部分P3之间。
上区段UP的宽度W1可大于下区段LP的宽度W2。上区段UP的宽度W1可为上区段UP的最小宽度,并且下区段LP的宽度W2可为下区段LP的最小宽度。下区段LP的宽度W2可以是均匀的。上区段UP的宽度W1可以是不均匀的。例如,上区段UP的宽度W1可随着从第一支承层SL1接近第二支承层SL2而增大和减小。底电极LE可具有侧壁50,并且下区段LP的侧壁50可以是平坦的并垂直于衬底100的顶表面。上区段UP的侧壁50可从下区段LP的侧壁50凸出。上区段UP的侧壁50可以是倾斜的。上区段UP的侧壁50可为平坦或弯曲的。当上区段UP的侧壁50是平坦的时,上区段UP的侧壁50可在其中心具有尖点PO。第一部分P1的宽度W3、第三部分P3的宽度W4和第四部分P4的宽度W5可与第二部分P2的下区段LP的宽度W2基本相同。第一部分P1的宽度W3、第三部分P3的宽度W4和第四部分P4的宽度W5可为均匀的。
通孔TH可设置在彼此相邻的底电极LE之间。通孔TH中的每一个可设置在第一方向X上彼此相邻的一对底电极LE之间,并且还可以设置在与第一方向X交叉的第二方向Y上彼此相邻的一对底电极LE之间,并且可以设置在这两对底电极LE之间的交叉点(intersection)处。例如,通孔TH可从底电极LE的通过第二支承层SL2暴露的凹区段RP之间的间隙朝着底电极LE的第二部分P2之间的间隙延伸。通孔TH还可从底电极LE的第二部分P2之间的间隙朝着底电极LE的第一部分P1之间的间隙延伸,同时穿过第一支承层SL1。当在平面图中看时,多个通孔TH可沿着第一方向X按照z字形布置。
顶电极UE可设置在底电极LE上。顶电极UE可设置在底电极LE的顶表面、通过第一支承层SL1和第二支承层SL2暴露的底电极LE的侧壁50、第一支承层SL1和第二支承层SL2的顶表面和底表面、以及第一支承层SL1的侧表面上。顶电极UE可填充第一空间S1、第二空间S2以及通孔TH。在底电极LE之间,可通过第一支承层SL1和第二支承层SL2限定第一空间S1。在底电极LE之间,可通过层间电介质层112和第一支承层SL1限定第二空间S2。顶电极UE可由掺杂的半导体材料、金属材料、金属氮化物材料和金属硅化物材料中的一个或多个形成。顶电极UE可由诸如钴、钛、镍、钨或钼的难熔金属材料形成。顶电极UE可由诸如氮化钛(TiN)、钛铝氮化物(TiAlN)或氮化钨(WN)的金属氮化物形成。顶电极UE可由诸如铂(Pt)、钌(Ru)或铱(Ir)的金属形成。
电介质层130可介于顶电极UE与底电极LE之间。例如,电介质层130可共形地覆盖底电极LE的顶表面、通过第一支承层SL1和第二支承层SL2暴露的底电极LE的侧壁50、第一支承层SL1和第二支承层SL2的顶表面和底表面、和第一支承层SL1的侧表面。电介质层130可由包括从由以下各项构成的组中选择的至少一个的单层或其组合形成:金属氧化物(诸如HfO2、ZrO2、Al2O3、La2O3、Ta2O3或TiO2)和钙钛矿电介质材料(诸如SrTiO3(STO)、(Ba,Sr)TiO3(BST)、BaTiO3、PZT或PLZT)。
图2A示出了显示根据本发明构思的一些示例实施例的半导体装置的平面图。图2B示出了沿着图2A的线I-I'截取的显示根据本发明构思的一些示例实施例的半导体装置的剖视图。图2C示出了显示图2B的底电极的放大图。
参照图2A至图2C,底电极LE可包括第一竖直部分V1、平行于第一竖直部分V1并在第一方向X上与第一竖直部分V1间隔开的第二竖直部分V2、和在第二方向Y上延伸并将第一竖直部分V1连接至第二竖直部分V2的水平部分P。水平部分P可将第一竖直部分V1的下部连接至第二竖直部分V2的下部。水平部分P可接触接触插塞110。底电极LE可具有在竖直方向上延长的U形。底电极LE的宽度W1、W2、W3、W4和W5中的每一个可与第一竖直部分V1的外壁50a与第二竖直部分V2的外壁50b之间的距离相对应。
电介质层130可共形地覆盖底电极LE的内壁和底表面,该底表面被设置在底电极LE的内空间60中。顶电极UE可位于电介质层130上并且可填充底电极LE的内空间60。
图3、图4、以及图6至图10示出了沿着图1A的线I-I’截取的显示根据本发明构思的一些示例实施例的制造半导体装置的方法的剖视图。图5A示出了显示已经被蚀刻的缓冲层的放大图。图5B示出了显示图4的部分A的放大图。
参照图3,层间电介质层112可形成在衬底100上。衬底100可为半导体衬底,诸如硅(Si)衬底、锗(Ge)衬底或硅锗(SiGe)衬底。层间电介质层112可包括氧化硅层、氮化硅层和氧氮化硅层中的一个或多个。
接触插塞110可形成在层间电介质层112中。接触插塞110可包括半导体材料(例如,多晶硅)、金属半导体化合物(例如,硅化钨)、导电金属氮化物层(例如,氮化钛、氮化钽或氮化钨)和金属材料(例如,钛、钨或钽)中的一个或多个。虽然未示出,但是多条字线和与字线交叉的多条位线可形成在衬底100上和/或衬底100中。层间电介质层112可形成为覆盖字线和位线。杂质区(未示出)可在字线中的每一条的相对侧上形成在衬底100中,并且接触插塞110中的每一个可连接至杂质区之一。
模制结构MS可形成在层间电介质层112上。模制结构MS可包括第一模制层220、第一支承层SL1、第二模制层226、缓冲层230和第二支承层SL2。第一模制层220可为例如氧化硅层。第一支承层SL1可包括具有相对于第一模制层220的蚀刻选择性的材料。第一支承层SL1可为例如碳氮化硅(SiCN)层。第二模制层226可包括具有相对于第一支承层SL1的蚀刻选择性的材料。第二模制层226可为例如氧化硅层。缓冲层230可形成在第二模制层226上。
缓冲层230可包括硅、氧和氮。缓冲层230中可具有均匀的硅含量。缓冲层230中的氧含量可随着从第二模制层226接近第二支承层SL2而逐渐减小,并且缓冲层230中的氮含量可随着从第二模制层226接近第二支承层SL2而逐渐增大。例如,缓冲层230可在其邻近于第二模制层226的顶表面的下部10处不含氮,并且可在其邻近于第二支承层SL2的底表面的上部20处不含氧。缓冲层230可在其位于下部10与上部20之间的中部30处含氮和氧。缓冲层230的中部30中的氮含量可随着从缓冲层230的下部10接近上部20而逐渐增大,并且缓冲层230的中部30中的氧含量可随着从缓冲层230的下部10接近上部20而逐渐减小。缓冲层230的下部10可包括氧化硅,缓冲层230的上部20可包括氮化硅,并且缓冲层230的中部30可包括氧氮化硅。
可利用包括硅的第一气体、包括氧的第二气体和包括氮的第三气体形成缓冲层230。缓冲层230的形成可包括引入第一气体和第二气体,以及逐渐减小第二气体的引入量同时逐渐增大第三气体的引入量。第二气体的引入量的逐渐减小可与第三气体的引入量的逐渐增大同时执行。从用于形成缓冲层230的沉积处理的开始至结束,第一气体的引入量可不变。第一气体可为或包括例如SiH4。第二气体可为或包括例如N2O。第三气体可为或包括例如NH3。
第二支承层SL2可形成在缓冲层230上。第二支承层SL2可包括例如碳氮化硅(SiCN)层。第一掩模层234和第二掩模层236可顺序地形成在模制结构MS上。例如,第一掩模层234可为氮化硅层,并且第二掩模层236可为多晶硅层。第二掩模层236可具有暴露第一掩模层234的一些部分的第一开口235。
参照图4,第二掩模层236可用作蚀刻掩模,以各向异性地蚀刻第一掩模层234和模制结构MS。因此,电极孔EH可被形成在模制结构MS中。例如,可通过各向异性蚀刻处理形成电极孔EH,以各向异性地蚀刻第一掩模层234、第二支承层SL2、缓冲层230、第二模制层226、第一支承层SL1和第一模制层220。各向异性蚀刻处理可为例如干蚀刻处理。干蚀刻处理可使用蚀刻气体,诸如CF4、CF4/O2或C2F6/O2。在蚀刻处理期间,第一掩模层234和第二掩模层236可被蚀刻和去除。对于另一示例,在蚀刻处理之后,可单独地执行其它蚀刻处理以蚀刻和去除第一掩模层234和第二掩模层236。
一起参照图5A和图5B,在将上述蚀刻气体用于形成电极孔EH的蚀刻处理期间,蚀刻副产物237可形成在电极孔EH的侧壁上。形成在含氧层上的蚀刻副产物237的厚度可小于形成在含氮层上的蚀刻副产物237的厚度。例如,形成在第二模制层226的侧壁上的蚀刻副产物237的厚度可小于形成在第二支承层SL2的侧壁上的蚀刻副产物237的厚度。这可能是因为被蚀刻而离开第二模制层226的氧与蚀刻气体中的碳反应以形成一氧化碳(CO)或二氧化碳(CO2),这种反应可导致氧的蒸发。
蚀刻副产物237可形成在暴露于电极孔EH的缓冲层230的侧壁上。因为缓冲层230中的氧含量随着从第二支承层SL2接近第二模制层226而增大,所以形成在缓冲层230的侧壁上的蚀刻副产物237的厚度可随着从第二支承层SL2接近第二模制层226而减小。因此,缓冲层230可在其上形成有蚀刻副产物237的侧壁处被部分地过度蚀刻。例如,缓冲层230的侧壁上的过度蚀刻的量可随着从第二支承层SL2接近第二模制层226而增大,然后可从缓冲层230的临界点CP开始逐渐减小。临界点CP可与撞击缓冲层230的侧壁的蚀刻离子的能量减小的位置相对应。缓冲层230可形成为具有凹侧壁。缓冲层230的厚度可随着从第二模制层226接近第二支承层SL2再次逐渐减小和增大。缓冲层230在其临界点CP处可具有最小厚度。
在各向异性蚀刻处理之后,可通过灰化处理和/或剥离处理去除蚀刻副产物237。
参照图6,底电极LE可形成在电极孔EH中。底电极LE的形成可包括形成导电层以填充电极孔EH并覆盖模制结构MS的顶表面,然后对导电层执行平坦化处理。因为电极孔EH中的每一个具有高高宽比,所以用于形成底电极LE的沉积处理可使用具有优秀的阶梯覆盖特性的层形成技术。例如,可使用化学气相沉积(CVD)或原子层沉积(ALD)形成底电极LE。底电极LE可形成为完全填充电极孔EH。在这种情况下,底电极LE中的每一个可具有柱形。对于另一示例,底电极LE可形成为共形地覆盖电极孔EH的侧壁和底表面。在这种情况下,底电极LE中的每一个可具有U形。
底电极LE可包括金属材料、金属氮化物层和金属硅化物层中的一个或多个。例如,底电极LE可由诸如钴、钛、镍、钨或钼的难熔金属材料形成。对于另一示例,底电极LE可由诸如氮化钛(TiN)层、氮化钛硅(TiSiN)层、氮化钛铝(TiAlN)层、氮化钽(TaN)层、氮化钽铝(TaAlN)层或氮化钨(WN)层的金属氮化物层形成。对于另一示例,底电极EL可由贵金属层形成,贵金属层包括从由铂(Pt)、钌(Ru)和铱(Ir)构成的组中选择的至少一个。对于另一示例,底电极LE可由诸如PtO2、RuO2或IrO2的导电贵金属氧化物层形成,或可由诸如SRO(SrRuO3)、BSRO((Ba,Sr)RuO3)、CRO(CaRuO 3)或LSCo的导电氧化物层形成。
根据本发明构思的一些示例实施例,缓冲层230可含氮,该氮的量随着从第二模制层226接近第二支承层SL2而逐渐增大,因此当执行各向异性蚀刻处理以形成电极孔EH时可防止缓冲层230在邻近第二模制层226的上部20的侧壁处被过度蚀刻。因此,可在形成在电极孔EH中的底电极LE之间设置足够的距离,结果,可在底电极LE之间避免电干扰。
第三掩模层242可形成在其中具有底电极LE的模制结构MS上。第三掩模层242可由具有相对于第二支承层SL2的蚀刻选择性的材料形成。第三掩模层242可为例如非晶碳层(ACL)。光刻胶层244可形成在第三掩模层242上。光刻胶层244可具有第二开口246。第二开口246中的每一个可与第二支承层SL2的在沿第一方向(图1的X)彼此相邻的一对底电极LE之间的部分竖直地重叠,并且还可与第二支承层SL2的在沿与第一方向X交叉的第二方向(图1的Y)彼此相邻的一对底电极LE之间的部分竖直地重叠。
参照图7,可执行光刻胶层244用作蚀刻掩模以顺序地蚀刻第三掩模层242、第二支承层SL2和缓冲层230的蚀刻处理。因此,通孔TH可形成为穿透第三掩模层242、第二支承层SL2和缓冲层230。通孔TH可部分地暴露第二模制层226的顶表面、缓冲层230的侧壁和底电极LE的侧壁。蚀刻处理可部分地蚀刻底电极LE的上部。因此,凹区段RP可形成在底电极LE的上拐角的一些部分上。凹区段RP可从底电极LE的顶表面凹进。当执行蚀刻处理时,也可去除光刻胶层244以暴露第三掩模层242的顶表面。蚀刻处理可为例如干蚀刻处理。干蚀刻处理可使用例如CxFy气体或者CHxFy气体。
参照图8,可去除第三掩模层242。第三掩模层242的去除可暴露第二支承层SL2的顶表面。可通过例如灰化处理和/或剥离处理去除第三掩模层242。可对暴露于通孔TH的缓冲层230和第二模制层226执行去除处理。可去除缓冲层230和第二模制层226以形成第一空间S1。在底电极LE之间,可通过第一支承层SL1和第二支承层SL2限定第一空间S1。通孔TH和第一空间S1可暴露第一支承层SL1和第二支承层SL2之间的底电极LE的侧壁、第一支承层SL1的顶表面和第二支承层SL2的底表面。可通过湿蚀刻处理去除缓冲层230和第二模制层226,该湿蚀刻处理使用具有相对于第一支承层SL1和第二支承层SL2的蚀刻选择性的蚀刻剂。例如,蚀刻剂可包括氢氟酸(HF)或鲎变形细胞溶解物(LAL)。
参照图9,可执行蚀刻处理以蚀刻暴露于通孔TH的第一支承层SL1的一些部分。可去除第一支承层SL1的一些部分以允许通孔TH部分地暴露第一模制层220的顶表面。当执行蚀刻处理以蚀刻第一支承层SL1的一些部分时,可发生过度蚀刻以部分地去除第一模制层220的上部。
参照图10,可对通过第一支承层SL1暴露的第一模制层220执行去除处理。第一模制层220可因此被去除以形成第二空间S2。在底电极LE之间,可通过层间电介质层112和第一支承层SL1限定第二空间S2。通孔TH和第二空间S2可暴露设置在第一支承层SL1下面的底电极LE的侧壁、层间电介质层112的顶表面和第一支承层SL1的底表面。可通过湿蚀刻处理去除第一模制层220,该湿蚀刻处理使用具有相对于第一支承层SL1和第二支承层SL2的蚀刻选择性的蚀刻剂。例如,可使用氢氟酸(HF)或鲎变形细胞溶解物(LAL)去除第一模制层220。
返回参照图1B,可在衬底100上形成电介质层130。电介质层130可共形地覆盖层间电介质层112的顶表面,底电极LE的侧壁,第一支承层SL1的顶表面、底表面和侧表面,以及第二支承层SL2的顶表面和底表面。电介质层130可由通过通孔TH提供的电介质材料形成。可使用具有优秀的阶梯覆盖特性的诸如原子层沉积(ALD)的层沉积技术形成电介质层130。电介质层130可由包括从由以下各项构成的组中选择的至少一个的单层或其组合形成:金属氧化物(诸如HfO2、ZrO2、Al2O3、La2O3、Ta2O3或TiO2)和钙钛矿电介质材料(诸如SrTiO3(STO)、(Ba,Sr)TiO3(BST)、BaTiO3、PZT或PLZT)。
可在电介质层130上形成顶电极UE。顶电极UE可形成在通孔TH、第一空间S1和第二空间S2中,同时覆盖电介质层130的顶表面。顶电极UE可共形地覆盖电介质层130的顶表面。因此,顶电极UE可以既不完全填充通孔TH、也不完全填充第一空间S1和第二空间S2。对于另一示例,顶电极UE可完全填充通孔TH、第一空间S1和第二空间S2。顶电极UE可由掺杂的半导体材料、金属材料、金属氮化物材料和金属硅化物材料中的一个或多个形成。顶电极UE可由诸如钴、钛、镍、钨或钼的难熔金属材料形成。顶电极UE可由诸如氮化钛(TiN)、氮化钛铝(TiAlN)或氮化钨(WN)的金属氮化物形成。顶电极UE可由诸如铂(Pt)、钌(Ru)或铱(Ir)的金属形成。
根据本发明构思的一些示例实施例,其氮含量随着从第二模制层226接近第二支承层SL2而逐渐增大的缓冲层230可设置在第二模制层226与第二支承层SL2之间,因此,当执行各向异性蚀刻处理以形成电极孔EH时,可抑制(或者,可替换地,防止)缓冲层230在其邻近第二模制层226的上侧壁50处被过度蚀刻。因此,可在形成在电极孔EH中的底电极LE之间设置足够的距离,结果,可在底电极LE之间避免电干扰。
虽然已结合附图所示的本发明构思的一些示例实施例描述了示例实施例,但是本领域技术人员应该理解,在不脱离本发明构思的示例实施例的情况下可作出各种改变和修改。本领域技术人员应该清楚,在不脱离本发明构思的范围和精神的情况下,可对其作出各种替代、修改和改变。
Claims (19)
1.一种制造半导体装置的方法,所述方法包括:
在衬底上形成包括模制层、缓冲层和支承层的模制结构,使得所述缓冲层的氮含量在从所述模制层接近所述支承层的方向上增大并且使得所述缓冲层的氧含量在从所述支承层接近所述模制层的方向上增大;
对所述模制结构执行各向异性蚀刻处理,以在所述模制结构中形成多个通孔;以及
在所述多个通孔中的对应通孔中形成多个底电极。
2.根据权利要求1所述的方法,其中,形成所述模制结构包括:
使用包括硅的第一气体、包括氧的第二气体和包括氮的第三气体在所述模制层上形成所述缓冲层,
供应恒定量的所述第一气体直到形成所述缓冲层,
逐渐减小所述第二气体的量直到形成所述缓冲层,以及
逐渐增大所述第三气体的量直到形成所述缓冲层。
3.根据权利要求2所述的方法,其中,
所述第一气体包括SiH4,
所述第二气体包括N2O,并且
所述第三气体包括NH3。
4.根据权利要求1所述的方法,其中,所述缓冲层包括:
邻近所述模制层的下部,所述下部包括氧化硅;
邻近所述支承层的上部,所述上部包括氮化硅;以及
所述下部与所述上部之间的中部,所述中部包括氧氮化硅。
5.根据权利要求1所述的方法,其中,执行所述各向异性蚀刻处理包括:
形成蚀刻副产物,以覆盖所述多个通孔中的所述缓冲层的侧壁,使得所述蚀刻副产物的厚度在从所述支承层接近所述模制层的方向上减小。
6.根据权利要求5所述的方法,其中,执行所述各向异性蚀刻处理还包括:
在形成所述多个通孔之后,使用灰化或剥离处理去除所述蚀刻副产物。
7.根据权利要求1所述的方法,其中,执行所述各向异性蚀刻处理形成所述多个通孔,使得所述缓冲层的厚度随着从所述模制层接近所述支承层而逐渐减小和增大。
8.根据权利要求1所述的方法,其中,所述多个底电极具有倾斜的侧壁。
9.一种制造半导体装置的方法,所述方法包括:
在衬底上形成模制层;
使用第一气体和第二气体、通过逐渐减小所述第一气体的量和逐渐增大所述第二气体的量在所述模制层上形成缓冲层,所述第一气体包括氧并且所述第二气体包括氮;
在所述缓冲层上形成支承层;
通过执行各向异性蚀刻处理以顺序地各向异性地蚀刻所述支承层、所述缓冲层和所述模制层来形成通孔;以及
在所述通孔中形成底电极。
10.根据权利要求9所述的方法,其中
所述第一气体包括N2O,并且
所述第二气体包括NH3。
11.根据权利要求9所述的方法,其中,形成所述缓冲层还包括:
在形成所述缓冲层期间供应恒定量的第三气体,所述第三气体包括硅。
12.根据权利要求11所述的方法,其中,所述第三气体包括SiH4。
13.根据权利要求9所述的方法,其中,
所述缓冲层的氮含量随着从所述模制层接近所述支承层而增大,并且
所述缓冲层的氧含量随着从所述支承层接近所述模制层而增大。
14.根据权利要求9所述的方法,其中,所述缓冲层包括:
邻近所述模制层的下部,所述下部包括氧化硅;
邻近所述支承层的上部,所述上部包括氮化硅;以及
所述下部与所述上部之间的中部,所述中部包括氧氮化硅。
15.根据权利要求9所述的方法,其中,执行各向异性蚀刻处理包括:
形成覆盖所述通孔中的所述缓冲层的侧壁的蚀刻副产物,使得所述蚀刻副产物的厚度随着从所述支承层接近所述模制层而减小。
16.根据权利要求9所述的方法,其中,执行各向异性蚀刻处理形成所述多个通孔,使得所述缓冲层的厚度随着从所述模制层接近所述支承层而逐渐减小和增大。
17.一种半导体装置,包括:
底电极,其位于衬底上;
第一支承层,其位于所述底电极的侧壁上;
第二支承层,其位于所述第一支承层的上方并且位于所述底电极的所述侧壁上;以及
电介质层,其覆盖所述底电极的所述侧壁和顶表面,其中所述底电极包括:
下区段,其位于所述第一支承层与所述第二支承层之间,并且不与所述第一支承层水平重叠;以及
上区段,其位于所述下区段与所述第二支承层之间,所述上区段具有从所述下区段的侧壁突出的侧壁,使得所述上区段的所述侧壁的中心具有尖点,
其中,所述上区段的宽度是不均匀的,并且所述下区段的宽度是均匀的,
其中,所述上区段的最顶部的宽度等于所述底电极的在所述第二支承层的侧壁上的部分的宽度。
18.根据权利要求17所述的半导体装置,其中,所述上区段的宽度随着接近所述第二支承层而增大和减小。
19.根据权利要求17所述的半导体装置,其中,所述上区段的宽度大于所述下区段的宽度。
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