CN110912718A

CN110912718A - Method for reducing power consumption of heterogeneous three-dimensional on-chip network layout

Info

Publication number: CN110912718A
Application number: CN201811071157.8A
Authority: CN
Inventors: 刘正轩; 宋国治; 张智慧; 周一杰; 成方圆
Original assignee: Tianjin Polytechnic University
Current assignee: Tianjin Polytechnic University
Priority date: 2018-09-14
Filing date: 2018-09-14
Publication date: 2020-03-24

Abstract

The invention provides a method for reducing power consumption of a heterogeneous three-dimensional network-on-chip Layout, which adopts the basic idea that the SLP (System Layout planning) idea of industrial engineering is applied to the field of network-on-chip Layout, and then optimizes the power consumption by combining an intelligent optimization algorithm, and ensures that the relation degree between all IP cores is highest. The power consumption of communication in different test cases is compared with the prior art, so that the superiority of the algorithm is verified, and the purpose of reducing the power consumption of the network on chip is achieved. Experimental results show that the power consumption can be reduced by adopting a system layout optimization algorithm to solve the NoC layout planning problem, and a plurality of beneficial conclusions can be obtained through analysis and explanation of experimental data. From the general trend, the reduction of power consumption is gradually reduced with the increase of average traffic between IP cores, and when the average core traffic between IP cores is within 1000Mbps, the total power consumption is reduced by 40.51% on average.

Description

Method for reducing power consumption of heterogeneous three-dimensional on-chip network layout

Technical Field

The invention belongs to the interdisciplinary field of integrated circuits, intelligent optimization algorithms and industrial engineering SLP (slow level signaling), and particularly designs a method for reducing the power consumption of a network layout on a heterogeneous three-dimensional chip.

Background

With the development of processors towards multi-core, more and more IPs are integrated on a chip, the connection between IP cores is more and more complex, and the traditional bus interconnection structure is not enough to meet the higher and higher requirements. Therefore, the conventional bus interconnect structure tends to be gradually replaced by a network on chip having low power consumption, high bandwidth, and the like.

The network on chip is divided into a conventional network on chip and an application-oriented network on chip according to a topological structure. Conventional networks on chip design topologies based on regular meshes and therefore require cores of similar size, but this approach is not suitable for heterogeneous networks on chip. When the network on chip for application is designed, the network on chip can be designed in a targeted manner according to the size characteristics, traffic volume and other information of different IP cores, so that the purposes of reducing the power consumption of the chip, improving the performance and the like are achieved.

Because the layout planning is an NP (Non-deterministic polymeric) problem, but because of the particularity of the NP-complete problem, that is, as the scale of the problem is continuously enlarged, the solution space of the problem will show exponential growth, so that the conventional solution method fails, the intelligent optimization algorithm (such as simulated annealing, particle swarm) is often adopted in large quantities for the complex layout problem. However, after a large amount of literature is studied, the traditional intelligent optimization algorithm can find the optimal solution, optimize the layout but not directly obtain a specific layout scheme.

We have found that in macroscopic systems such as warehouse functional area systems, the layout of facilities is much like the layout of IP cores on a chip. SLP is often used in industrial engineering to lay out macroscopic system facilities, so we use the SLP method for the first time to layout the IP cores of the chip.

SLP is a classic system topology method of longeval dominance proposed by muir in 1961. The method combines the logistics analysis and the operation unit correlation together to establish a correlation diagram which represents the closeness degree of each department. The correlation diagram is similar to the objective flow diagram between plants. The correlation map is adjusted using a trial and error algorithm until a satisfactory solution is obtained. Then, the departments are reasonably arranged according to the volume of the building. In order to evaluate the layout scheme, the system layout design also quantifies the scheme. Weights are given according to the different degrees of closeness, then different arrangement schemes are tested, and finally the arrangement scheme with the highest score is selected. In the traditional SLP method for system layout design, the basis and the entry point for researching engineering layout problems are summarized into 5 basic elements of P-products, Q-yield, R-process, S-auxiliary department and T-time. The SLP method is adopted to carry out the primary work of enterprise general plane arrangement, namely, the analysis of the mutual relation among all the operation units is carried out. Including the interrelationship of streams and non-streams. The mutual relation table of the operation units is obtained through synthesis, and then the degree of closeness of the mutual relation among the operation units in the mutual relation table is determined. Determining the distance between each operation unit, arranging the position of each operation unit, drawing the position correlation diagram of the operation unit, combining the actual floor area of each operation unit with the position correlation circle of the operation unit, and forming the area correlation circle of the operation unit; obtaining a plurality of feasible arrangement schemes, then adopting weighting factors to evaluate and prioritize each scheme, and quantifying each factor to take the arrangement scheme with the largest score as the optimal arrangement scheme.

Since the SLP method has been proposed, it has been extensively applied to layout design of various facilities. In general, when the SLP method is applied to draw the job unit location map and the area correlation map, the initial arrangement scheme needs to be manually and continuously modified and adjusted to meet the corresponding conditions. Designers mainly rely on experience to adjust the scheme according to the constraint conditions, so that the final results obtained by different designers with different experiences may be greatly different, human factors have large interference, the adjustment process is very complicated, the arrangement scheme is less, and a more optimal scheme is difficult to select. With the continuous development of computer technology, the SLP idea is improved, and a genetic algorithm is used for solving the facility arrangement problem, so that the problems can be effectively avoided.

Disclosure of Invention

The invention aims to solve the defects of the traditional intelligent optimization algorithm in a three-dimensional network on chip, and transplants SLP into the field of the network on chip to ensure that the power consumption of the whole network on chip is minimum and the closeness is maximum, thereby achieving the aim of optimizing the layout.

Drawings

FIG. 1 modified SLP flow chart

FIG. 2 example diagram of IP core location

FIG. 3 is a single-dot cross example diagram

FIG. 4 shows a variation

FIG. 5 is a graph of nuclear traffic vs. power consumption (G1-G4)

FIG. 6 is a graph of nuclear traffic vs. power consumption (G1-G6)

FIG. 7 core communication diagram of VOPD

FIG. 8 is a graph of the degree of closeness of IP cores

FIG. 9 layout scheme

Detailed Description

stepl SLP in combination with genetic algorithms

The SLP method has the characteristics of strong logic, clear order and the like. In order to solve the defects of the conventional SLP, a genetic algorithm is used for solving after an objective function is obtained, so that the interference of human factors is avoided. The specific steps of the method for improving SLP are shown in FIG. 1:

step2 layout planning modeling

A. Model assumptions

The main goal of the chip network layout design in the text is to realize the minimum communication power consumption and the maximum comprehensive relationship between the IP cores, and the text integrates the two goals, and establishes a layout optimization model of the three-dimensional chip network by combining the research objects of the text based on the method provided by the related documents of the chip network layout planning. The assumptions required by the model are now listed.

(1) Knowing the total layout planning area range of the three-dimensional sheet network, simplifying the shape into a rectangle, positioning the origin of a rectangular coordinate system at the lower left corner of the layout area, setting the X-axis direction in the direction of the long side of the layout area, and setting the Y-axis direction in the direction of the wide side of the layout area; where L represents the length of the web and W represents the width of the web.

(2) Each IP core is rectangular, and the sides of the rectangle of each IP core are parallel to the X axis and the Y axis as shown in the figure; where the IP core is l in length and w in width, as shown in FIG. 2, we finally determineThe layout scheme is the IP core center coordinate (x)_zi，y_zi)。

(3) The planes of each IP core layout are assumed to be coplanar, as in fig. 2.

B. Construction of models

(1) Power consumption model

The method aims at minimizing the overall interconnection power consumption among a kernel, a network interface and a router and the internal power consumption consumed by the router per se, and establishes a power consumption model, namely

minP＝P_m2n+P_s2n+P_s2s+P_s

Wherein P is_m2nRepresenting the interconnect power consumption between the core and the network interface, P_s2nRepresenting the interconnect power consumption, P, between the router and the network interface_s2sRepresenting interconnect power consumption, P, between routers_sRepresenting the internal power consumed by the router itself.

The power consumption on the interconnection line is calculated by the following model

P_wire＝P_unit1·f·d

Wherein P is_unit1Represents the power consumption per unit length of interconnect through the unit bit traffic, d represents the length of the interconnect, and f represents the traffic on the interconnect.

The calculation model of the power consumption consumed by the router is

P_s＝P_unit2·f·k

Wherein P is_unit2The power consumption of each port on the router when per bit traffic passes is represented, f represents the traffic on the router, and k represents the number of routers.

In summary, with the goal of minimizing the total interconnection power consumption of the network on chip and the power consumption consumed by the router itself, we establish a total power consumption model as follows:

when x is assumed to be any scheme of the on-chip network layout plan, x ∈ R, under the x layout scheme, f (X) represents a traffic matrix under the scheme x, and d (X) represents a distance matrix under the scheme x. The power consumption consumed under scheme x can be derived therefrom, as shown in the formula.

Wherein: i, j represents a certain IP core in the chip network;

m represents three interconnect power consumptions on the chip network;

n represents the number of IP cores placed on the slice network;

(2) traffic affinity model

In order to make the IP cores with large communication volume in the network-on-chip layout as close as possible, a model with the maximum communication volume closeness degree as a target is constructed by an arrival table and a mutual relation graph, namely the model

The larger the value of r (x), the more reasonable the layout under scheme x. Wherein: i, j represents a certain IP core in the chip network; r (x) represents the total value of the closeness degree of each IP core in the network chip; b_ijRepresenting a conversion factor between closeness and distance between the IP cores; g_ij(x) Representing the traffic matrix between IP cores under deployment scenario X.

Since the distance between the IP core i and the IP core j is required to be as close as possible as the closeness between them is higher, and the distance between them is required to be as far as possible as the closeness is lower. It can be seen that there is some relationship between the closeness of the IP cores and the distance, assuming a conversion factor b between them_ijDefinition of b_ijThe values of (A) are shown in Table 1.

TABLE 1 transformation factor b_ij

d_ij	b _ij
		0＜d_ij≤d_max/6	1
d_max/6＜d_ij≤d_max/3	0.8
		d_max/3＜d_ij≤d_max/2	0.6
d_max/2＜d_ij≤2d_max/3	0.4
		2d_max/3＜d_ij≤5d_max/6	0.2
5d_max/6＜d_ij≤d _max	0

(3) Layout model

The overall layout optimization model is established by taking the minimum power consumption and the maximum comprehensive relation among the IP cores as targets, and is as follows:

wherein:

d_ij＝|x_zi-x_zj|+|y_zi-y_zj| (2)

x_i+l_i≤L y_i+w_i≤W (4)

the formula (1) ensures that the total area of all IP cores is smaller than the total area of the patch network;

equation (2) represents the manhattan distance between IP cores;

formula (3) represents the position of the IP core with the center coordinates of each rectangle;

equation (4) represents that the IP core layout range cannot exceed the range of the slice network.

step 3 model solution

The upper section model establishes a network-on-chip power consumption model and an affinity model based on communication traffic, the relationship between two IP cores with large communication traffic is strong, and the relationship between cores with small communication traffic is weak. Genetic algorithm is adopted to specifically solve the model established in the previous section based on SLP method.

The method comprises the following specific steps:

(1) encoding

The binary coding is used here, i.e. a fixed length of 0, 1, the character string represents the chromosome, the length is chosen to be 10, e.g. chromosome i is represented as {0111000111 }.

(2) Initializing a population

An initial population is generated randomly and the population size is set to 200.

(3) Fitness function

The selection process is carried out according to the fitness, and the advantages are eliminated. The method is a dual-objective function optimization problem, and requires low power consumption and strong relationship. That is, two functions are converted into a single objective function, and the two objective functions are weighted, and the two functions have equal importance, and the weight values of the two functions are set to be u-0.5 and v-0.5. The final objective function is:

M＝u*P+v*R

the fitness function is expressed as the inverse of the final objective function, as follows:

(4) selection operator

The selection operator can ensure that the filial generation inherits the excellent gene of the parent generation, namely the filial generation has high or low quality. The better the individual fitness, the higher the probability of inheritance to the next generation, and flexible segmented replication is adopted in the method, namely, the population is sorted from high to low according to the fitness value and then divided into three segments, wherein one segment with high fitness value is reserved to filial generations twice, one segment with low fitness value is not reserved, and the middle segment is reserved once. The method can well retain excellent individuals.

(5) Crossover operator

Two individuals create new individuals through gene recombination, and crossover is a method for creating new individuals. Firstly, randomly pairing individuals in the population, and then carrying out cross operation to generate new individuals, thereby generating a new population.

The method adopts a single-point crossing mode to generate a new individual, wherein the single-point crossing is to randomly select a breakpoint (cross point) for a pair of chromosomes to be paired, and parts of the two chromosomes are interchanged to obtain a new set of chromosomes. The crossover probability is set to 0.9 here, and the crossover is as shown in fig. 3.

(6) Mutation operator

The crossover operator is a main method for generating new individuals in the genetic algorithm, the mutation operator is an auxiliary method for generating new individuals in the genetic algorithm, the defect of the local search capability of the genetic operator is made up, and the combination of the crossover operator and the mutation operator is the reason for the excellent optimizing capability of the genetic algorithm in solving the NP problem.

The genetic mutation is adopted, namely, one or more genes in an individual are replaced by other alleles at a certain mutation rate, the mutation probability is set to be 0.02, and the mutation mode is shown in figure 4.

(7) Termination of algorithm

An appropriate population size is set and when this size is reached, the genetic algorithm is terminated. Generally, the population size is usually between 100 and 1000, and the population size is selected to be 100 herein.

step 4 procedure

The CPU of the experimental operation environment is an Intel (R) core (TM) i5-6200U CPU, the main frequency is 2.30GHz2.40GHz, and the memory is a 4GB microcomputer.

The experimental program is written in C language and runs in Dev C + +5.11 under win10 system.

The test cases adopted by the invention are divided into two groups, the first group is MPEG4, MWD and VOPD^[2]The second group is 263dec 3dec, 263encmp3dec and mp3encmp3dec^[3]The detailed description is shown in table 2:

TABLE 2 test case examples

Test case	Reference numerals	Number of kernels	Number of nets
				MPEG4	G1
	12	13
			MWD	G2		12	12
VOPD	G3							12	14
			263decmp3dec	G4	14	15
263encmp3dec	G5						12	12
			mp3encmp3dec	G6	13	13

The power consumption model adopted in the method is that under the 0.18 mu m technology, the power consumption of each port on the router when passing through the traffic of each bit is 0.11pW/bit, and the power consumption of each unit line on the interconnection line when passing through the traffic of each unit is 0.6pW/bit/mm^[4]。

The parameter settings herein are shown in table 3 below.

TABLE 3 relevant parameter settings

Initial population	200	Number of iterations	100
				Probability of crossing	0.9	Probability of variation	0.02

We performed 20 experiments for each test case, and averaged the final average power consumption, with the experimental data shown in table 4.

Table 4 data of experimental results

Test case	PDF average Power consumption/mW	Average Power consumption/mW	Optimization/%
				G1	1.587	1.4508	8.58
G2	0.4598	0.1355	70.53
				G3	1.5659	0.6018	61.57
G4	6.0478	4.7566	21.35
				G5	12.1402	59.6317	-79.64
G6	1.345	9.5809	-85.96

From table 4, it can be seen that, for the four test cases of MPEG4, MWD, VOPD, 263 demomp 3dec, the power consumption of the present invention is reduced significantly, and for the MWD, the power consumption can be reduced by up to 70.53%, which greatly reduces the power consumption of the topology generation algorithm (PDF). For the two 263encmp3dec and mp3enmp3dec test cases, the result of the invention is not satisfactory, and we have conducted deep analysis and optimization on the two test cases of G5 and G6 in the following. But the correctness of our method can be proved as a whole.

Further, the average traffic of each test case is compared, and the traffic size and the power consumption are related to analyze, and table 5 shows the average core traffic data of each test case.

Test case	Average traffic
		G1	533.2308
G2	93.3333
		G3	232.9333
G4	1006.3571
		G5	18696.6364
G6	1293.4167

Through analysis, the relation between average core traffic and power consumption is obtained, and is shown in fig. 5 and fig. 6.

From fig. 5 and fig. 6, it can be seen that when the average core traffic of the test cases is less than 1000Mbps, the optimization effect of the optimization algorithm is better than that of the PDF algorithm; and the smaller the traffic, the more obvious the optimization effect is, and when the traffic is less than 500Mbps, the power consumption is much lower than that of PDF and LPTGA.

Through research and analysis of coordinate positions of specific layout schemes of G5 and G6, the distances between IP cores with relatively large communication traffic in G5 and G6 are not very close, and therefore power consumption is deviated.

In the following, we use test case VOPD as an example to explain the solving process and result analysis of the algorithm, and obtain the final layout scheme.

In connection with fig. 7, we can get the traffic from table to table between IP cores, as shown in table 6. The first row and the first column in the table correspond to each IP core respectively.

Table 6 IP core traffic from to table

Next, we define the closeness levels, which include A, E, I, O, U, with the levels having the meanings given in Table 7.

TABLE 7 affinity class Table for individual IP cores

Symbol	A	E	I	O	U
						Of significance	Of absolute importance	Of particular importance	Of importance	In general	Is not important

The closeness degree of dividing the IP cores according to the communication relationship mainly refers to the communication strength between the IP cores, that is, the size of the communication traffic. The closeness between each IP core is determined from the from table of the IP core traffic shown in table 7, as shown in fig. 8.

Finally, we analyze quantitatively and qualitatively through the close correlation degree graph between the IP cores, and optimize and evaluate the layout scheme, and finally obtain the layout scheme, as shown in FIG. 9.

The method obtains the layout scheme by applying the SLP method idea of macroscopic layout to a microscopic network-on-chip layout and combining a genetic algorithm. Experimental results show that the algorithm not only can effectively reduce the power consumption of the network on chip, but also can qualitatively and quantitatively optimize the layout scheme. When the average core communication traffic between the IP cores is less than 1000Mbps, the power consumption optimization effect is obvious.

Claims

1. A method for reducing the power consumption of a network layout on a heterogeneous three-dimensional chip is mainly characterized in that the method is combined with an SLP thought, and the power consumption can be reduced by the method for a classical test case task communication graph;

the method comprises the following steps:

s1, analyzing the test case by SLP method and establishing a power consumption model and an affinity model from the communication angle, seeking a layout scheme to make the power consumption as small as possible and the affinity of each IP core as high as possible, namely the core with large communication quantity is relatively close to the position as much as possible, the method assumes that the power consumption of unit distance unit bit is fixed and unchanged;

s2, solving the objective function by using a genetic algorithm, and obtaining the final optimal layout through heredity, intersection and variation;

the genetic algorithm comprises the following specific steps:

a1, randomly generating an initial population, and setting the initial population to be 200;

a2, encoding: the coding is a base stone solved by using a genetic algorithm, namely, parameters are converted into symbols which can be identified by a genetic program, and the coding adopts a binary system;

a3, cross mutation: similar to gene recombination, gene recombination of two individuals in the parent generation generates a new individual, and the cross probability is set to be 0.9; the mutation is to change a certain gene value with a tiny probability, and the mutation is selected to be 0.02;

and A4, stopping the algorithm by setting a proper population size, or stopping the algorithm when a moderate value function fluctuates up and down in a certain tiny interval, wherein the iteration number is 100, and in the iteration process, the iteration process is ended if the optimal solution does not appear after the iteration number reaches 100, or the iteration process may be ended in advance if the optimal solution is met.

2. The model in S1 is solved by the S2 genetic algorithm, and a satisfactory solution is obtained by a sufficient number of experiments, and the final solution is the coordinates of the center position of each IP core, i.e., the position in the layout solution.

3. And analyzing the experimental result in the S2, verifying the correctness of the algorithm from each IP core position, and comparing the algorithm with the PDF algorithm and the LPTGA algorithm from the aspect of power consumption to verify the practicability and the efficiency of the algorithm.