CN110798183A - Pulse signal output device and method thereof - Google Patents
Pulse signal output device and method thereof Download PDFInfo
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Abstract
The invention discloses a pulse signal output device, which is used for generating a pulse signal, and comprises: a pulse signal generator for generating a pulse signal; the counter is connected with the pulse signal generator and is used for counting the number of the pulse signals generated by the pulse signal generator; the latch is connected with the pulse signal generator and the counter and used for receiving the pulse signals generated by the pulse signal generator and controlling the number of the output pulse signals according to the number of the pulse signals counted by the counter; the invention also discloses a pulse signal output method; the number of the pulse signals generated by the pulse signal generator is counted through the counter, and the latch controls the output, so that the pulse signals with specific number are output.
Description
Technical Field
The invention relates to the technical field of circuit signals, in particular to a pulse signal output device and a pulse signal output method.
Background
The pulse signal is a discrete signal with various shapes and common analog signal (such asSine wave) In contrast, the waveforms are discontinuous in the Y-axis (there is a significant separation between waveforms) but haveA certain periodicity. The waveform of the pulse signal generally exhibits a rectangular shape, a sine shape, a triangular shape, etc., and the most common pulse signal is a rectangular wave (i.e., a square wave).
At present, with the development of technology, pulse signals have been widely applied to industrial production in the electronic industry; however, for some specific pulse signal generating circuits, the circuit design and practical application have great differences, the existing pulse signal generator can only continuously generate pulse signals with fixed frequency and pulse width, and the number and parameters of the pulse signals cannot be changed according to different industries and different product requirements, so that more manpower and production equipment are required to be invested in industrial production to screen the number and adjust the parameters, and great inconvenience is caused; how to change the number and parameters of pulse signals according to the requirements in industrial production becomes a big problem.
Disclosure of Invention
The present invention is directed to overcome the disadvantages of the prior art, and to provide a pulse signal output apparatus and a method thereof for changing the number and parameters of pulse signals according to requirements.
In order to solve the above technical problem, the present invention provides a pulse signal output device for generating a pulse signal, the pulse signal output device comprising: a pulse signal generator for generating a pulse signal; the counter is connected with the pulse signal generator and is used for counting the number of the pulse signals generated by the pulse signal generator; and the latch is connected with the pulse signal generator and the counter and used for receiving the pulse signals generated by the pulse signal generator and controlling the number of the output pulse signals according to the number of the pulse signals counted by the counter.
The invention also provides a pulse signal output method, which is applied to a pulse signal output device and is characterized in that the method comprises the following steps:
step S1, generating a pulse signal by a pulse signal generator;
step S2, counting the number of pulse signals generated by the pulse signal generator through a counter;
and step S3, receiving the pulse signals generated by the pulse signal generator through the latch, and controlling the number of the output pulse signals according to the number of the pulse signals counted by the counter.
According to the pulse signal output device and the method thereof, the number of the output pulse signals is effectively controlled through the cooperation of the counter and the latch, so that the pulse signals generated by the pulse signal generator can be applied to the production process of more products, the input of labor cost and equipment cost in the production process is reduced, and the production efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a structural diagram of a pulse signal output device according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of the pulse signal generator of fig. 1.
Fig. 3 is a waveform diagram of a pulse signal generated by the pulse signal generator of fig. 1.
Fig. 4 is a circuit diagram of the counter of fig. 1.
Fig. 5 is a circuit diagram of the latch of fig. 1.
Fig. 6 is a flowchart of a pulse signal output method according to an embodiment of the invention.
Fig. 7 is a sub-flowchart of step S1 in fig. 6.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the embodiments of the present invention, it should be understood that the terms "first" and "second" are only used for convenience in describing the present invention and simplifying the description, and thus, should not be construed as limiting the present invention.
Fig. 1 is a structural diagram of a pulse signal output device according to an embodiment of the present invention.
As shown in fig. 1, the pulse signal output apparatus includes a pulse signal generator 10, a counter 20, and a latch 30.
And a pulse signal generator 10 for generating a pulse signal.
And the counter 20 is connected with the pulse signal generator 10 and is used for counting the number of the pulse signals generated by the pulse signal generator 10.
And the latch 30 is connected with both the pulse signal generator 10 and the counter 20, and is used for receiving the pulse signals generated by the pulse signal generator 10 and controlling the number of the output pulse signals according to the number of the pulse signals counted by the counter 20.
The invention effectively controls the quantity of the output pulse signals through the cooperation of the counter 20 and the latch 30, so that the pulse signals generated by the pulse signal generator 10 can be applied to the production process of more products, the labor cost and the equipment cost in the production process are reduced, and the production efficiency is improved.
Referring to fig. 2 to 5, fig. 2 is a circuit diagram of the pulse signal generator 10 in fig. 1; fig. 3 is a waveform diagram of a pulse signal generated by the pulse signal generator 10 in fig. 1; FIG. 4 is a circuit diagram of counter 20 of FIG. 1; fig. 5 is a circuit diagram of the latch 30 of fig. 1.
In some embodiments, the latch 30 controls to output the received pulse signal generated by the pulse signal generator 10 when the number of pulse signals counted by the counter 20 is less than a preset number; the latch 30 controls to stop outputting the received pulse signal when the number of the pulse signals counted by the counter 20 reaches the preset number.
As shown in fig. 2, wherein the pulse signal generator 10 refers to a device capable of providing electric signals of various frequencies, waveforms and output levels, the general pulse signal generator 10 may be divided into a function signal generator and an arbitrary waveform function generator, wherein the function signal generator outputs a standard waveform, such as a sine wave, a square wave, etc.
In this embodiment, the pulse signal generator 10 includes a pulse signal generating circuit 11, and the pulse signal generating circuit 11 employs an NE555 chip 111 for generating a square wave pulse signal; in addition, the pulse signal generating circuit 11 further includes a resistor R1, a resistor R2, a resistance wire R3, a resistor R7, a resistor R8, a slide rheostat R5, a slide rheostat R6, a capacitor C1, a capacitor C2, an input power Vcc, and the like.
In the pulse signal generating circuit 11 in this embodiment, an NE555 chip 111 is used to form a multivibrator for generating a continuous square wave pulse signal, the NE555 chip 111 includes a plurality of pins, and the pin 1 of the NE555 chip 111 is a GND ground; pin 2 is a low level trigger terminal, pin 6 is a high level trigger terminal, pin 3 is a pulse signal output terminal, and pin 4 is a low level reset terminal; pin 5 as control voltage terminal; the pin 7 is used as the output end of the discharge tube in the chip; pin 8 serves as an input voltage terminal.
The pulse signal generating circuit 11 comprises a charging circuit and a discharging circuit, wherein the charging circuit comprises an input power supply Vcc, a resistor R1, a diode D2, a slide rheostat R5, a slide rheostat R6 and a capacitor C2 which are connected in sequence, and the discharging circuit comprises a capacitor C2, a slide rheostat R6, a slide rheostat R5, a diode D1, a resistor R2 and a pin 7 of an NE555 chip 111 which are connected in sequence. When charging is performed, the current output by the input power Vcc flows to the capacitor C2 through the resistor R1, the diode D2, the sliding resistor R5, and the sliding resistor R6 in sequence, and charges the capacitor C2. When the charging process of the capacitor C2 is completed, the capacitor C2 starts the discharging process, and the discharging loop flows from the capacitor C2 to the pin 7 of the NE555 chip 111 through the slide rheostat R6, the slide rheostat R5, the diode D1 and the resistor R2 in sequence according to the circuit.
As shown in fig. 3, the continuous rectangular wave in the upper half is a waveform diagram of the pulse signal generated by the pulse signal generator 10, and the lower peak is a voltage variation diagram of the capacitor C2 in the pulse signal generating circuit 11, where the peak value (upper limit value) of the voltage variation diagram is 2/3Vcc and the bottom value (lower limit value) thereof is 1/3 Vcc.
When the capacitor C2 in the pulse signal generator 10 is in the above charging process, the voltage of the capacitor C2 gradually rises, and the pulse signal generated by the pin 3 of the NE555 chip 111 is at a high level; when the voltage of the capacitor C2 rises to 2/3Vcc, pins 2 and 6 of the NE555 chip 111 receive a high level, pin 6 serving as a high level trigger end is triggered, and at this time, the upper limit comparator inside the NE555 chip connected to pin 6 is inverted, so that the level of the pulse signal to be generated by the NE555 chip 111 changes from a high level to a low level. Corresponding to the capacitor C2, starting a discharging process, when the capacitor C2 in the pulse signal generator 10 is in the discharging process, the voltage of the capacitor C2 gradually decreases, when the voltage of the capacitor C2 decreases to 1/3Vcc, the pins 2 and 6 of the NE555 chip 111 receive a low level, the pin 2 serving as a low level trigger end is triggered, at this time, the lower limit comparator inside the NE555 chip 111 connected to the pin 2 is inverted again, so that the level of the pulse signal generated by the pin 3 of the NE555 chip 111 changes from the low level to the high level, and the capacitor C2 starts the charging process again; this is repeated cyclically so that the pulse signal generator 10 generates a continuous square wave pulse signal.
The pulse signal generating circuit 11 further comprises two output circuits connected with the pin 3, wherein one output circuit outputs a pulse signal 1 through a resistor R7, and the other output circuit outputs a pulse signal 2 through a resistor R8; the pulse signal 1 and the pulse signal 2 are the same continuous square wave pulse signals, that is, the pulse signals output by the pin 3 are output simultaneously through two output circuits.
One output circuit is connected to the counter 20 and is configured to output the pulse signal 1 to the counter 20, and the other output circuit is connected to the latch 30 and is configured to output the pulse signal 2 to the latch 30.
As shown in fig. 4, the counter 20 is used for counting the number of pulses to realize the functions of measurement, counting and control, the counter 20 is composed of a basic counting unit and a plurality of control gates, the counting unit is composed of a series of various flip-flops with the function of storing information, and the flip-flops include an RS flip-flop, a T flip-flop, a D flip-flop, a JK flip-flop, and the like.
The counter 20 in the present embodiment is a flip-flop formed by a chip 21 of 74LS90, and is used for counting the number of pulse signals generated by the pulse signal generator 10; the number of the pulse signals refers to the number of specific waveforms in the pulse signals; such as square waves, triangular waves, etc.; in this embodiment, the pin 1 of the 74LS90 chip 21 is connected to the pin 3 of the NE555 chip 111 in the pulse signal generator 10 through a resistor R8, and is configured to receive the pulse signal 2 generated by the pulse signal generator 10; the pin 3, the pin 6 and the pin 7 of the 74LS90 chip 21 are reset terminals, and when the reset terminals are at a low level, the counter 20 is in a counting state; when the end is at high level, the counter 20 is in a stop counting state; the pin 8 and the pin 11 of the 74LS90 chip 21 are output terminals, and when the counter 20 counts fully, the output of the pin 8 or the pin 11 is at a high level; the pin 14 of the 74LS90 chip 21 is an input voltage terminal, and is connected to an input power Vcc via a resistor R10. In addition, the chip further includes other pins, which are not described in detail since they are not included in the present embodiment.
The pin 11 of the 74LS90 chip 21 is connected with a resistor R11 and a diode D10 as an output end; the pin 8 of the counter 20 is connected to a resistor R12 and a diode D11 as an output terminal, and when the output of any one of the pin 8 and the pin 11 is high level, the output of the counter 20 is determined to be high level.
As shown in fig. 5, the latch 30 is a pulse level sensitive memory cell circuit, and is a logic element with memory function in a digital circuit, which can change state under the action of a specific input pulse level. Latching is to temporarily store a signal to maintain a certain level state, so that the state of the output terminal does not change with the state change of the input terminal. The most important function of the latch 30 is buffering, and in the present embodiment, a 74HC573 chip 31 is used as the latch 30.
The 74HC573 chip 31 is a transparent latch with eight paths of output, the output is a tri-state gate, and the chip is a high-performance silicon gate CMOS device, and the pin 1 of the 74HC573 chip 31 is a GND ground; pin 2 is a pulse signal input terminal, and is used for connecting with the output terminal of the pulse signal generator 10, that is, connected with pin 3 of the NE555 chip 111 in the pulse signal generating circuit 11 through a resistor R7, and is used for receiving a pulse signal 1 generated by the pulse signal generator 10; the pin 11 is a control terminal connected to the output terminal of the counter 20, that is, connected to the pin 11 and the pin 8 of the 74LS90 chip 21 of the counter 20, and is used for receiving a high level signal output from the pin 11 after the count of the chip 21 of the counter 2074LS90 is full; pin 19 serves as an output for outputting a pulse signal.
When the pin 11 of the 74HC573 chip 31 does not receive a high level signal, the 74HC573 chip 31 does not latch the pulse signal, i.e. the pulse signal 1 received by the pin 2 is equal to the pulse signal output by the pin 19, and at this time, the 74HC573 chip 31 is in a transparent state; when the pin 11 of the 74HC573 chip 31 receives a high level signal, the 74HC573 chip 31 performs a latch operation on the pulse signal, that is, the pin 2 still receives the pulse signal 1, but the pin 19 does not output the pulse signal, the pin 19 maintains a low level output state, and at this time, the 74HC573 chip 31 corresponds to a lock state.
The preset number refers to a preset maximum count value of the counter 20, and the preset number can be set by setting a numerical value of a corresponding port of the 74LS90 chip 21 in the counter 20; in the counting process of the 74LS90 chip 21, when the current counting value of the 74LS90 chip 21 is less than the preset number, the output of the 74LS90 chip 21 is low level; when the current count value of the 74LS90 chip 21 is greater than or equal to the preset number, the 74LS90 chip 21 output is high.
Specifically, the values of the corresponding ports of the 74LS90 chip 21 are set in advance according to the number of pulses to be output, and the setting of the preset number is completed.
As shown in fig. 4 and fig. 5, in the counting process of the 74LS90 chip 21, when the current count value of the 74LS90 chip 21 is less than the preset number, that is, the number of square waves in the pulse signal 2 received by the 74LS90 chip 21 is less than the preset number, both the pin 11 and the pin 8 of the 74LS90 chip 21 output a low level; the pin 11 of the 74HC573 chip 31 does not receive the high level signal, and the 74HC573 chip 31 does not latch the received pulse signal 1, i.e. the 74HC573 chip 31 directly outputs the pulse signal 1 after receiving the pulse signal 1.
When the current count value of the 74LS90 chip 21 is greater than or equal to the preset number, that is, when the number of square waves in the pulse signal 2 received by the 74LS90 chip 21 reaches the preset number, either the pin 11 or the pin 8 of the 74LS90 chip 21 outputs a high level, and after the pin 11 of the 74HC573 chip 31 receives the high level, the 74HC573 chip 31 performs a latch operation on the pulse signal, that is, in a case where the pin 2 of the 74HC573 chip 31 continues to receive the pulse signal 1, the control pin 19 stops outputting the pulse signal.
In other embodiments, the pulse signal generator 10 may be implemented by different chips to generate sine wave, triangle wave, etc. for example, the chip of the pulse signal generator 10 may be implemented by ICL8038, XR-2206, etc.
In other embodiments, the counter 20 may be formed by chips such as 74LS109, 74ALS109, 74HC109, 74HCT109, and the like in the counter 20.
In other embodiments, the latch 30 may be implemented with chips 74LS244, 74LS373, 74hc373, and so on.
Therefore, the counter 20 counts the number of the pulse signals, determines whether the number of the pulse signals generated by the pulse signal generator 10 reaches a preset number, and controls the output of the pulse signals through the latch 30, so that the accurate control of the output number of the pulse signals is realized, and the application range of the pulse signal output device in the production process is expanded. For example, when a double pulse test is performed on the IGBT, the present technical solution may be adopted, so that the latch 30 outputs only two square wave pulse signals.
In some embodiments, when the number of the pulse signals counted by the counter 20 reaches a preset number, the latch 30 sends an output prohibition signal, and after receiving the output prohibition signal sent by the counter 20, the latch 30 stops outputting the pulse signals and continues to be in a low level output state.
The output prohibition signal refers to a high level signal output by the control pin 11 or the control pin 8 after the counted number of the pulse signals of the chip 21 74LS90 reaches a preset number.
As shown in fig. 4 and 5, specifically, when the 74LS90 chip 21 detects that the number of square waves in the pulse signal 2 received by the pin 1 reaches the preset number, the control pin 11 or the pin 8 continuously outputs a high level, and continuously sends a high level signal to the pin 11 of the 74HC573 chip 31, that is, the output signal is disabled; when the disable output signal is received at the pin 11 of the 74HC573 chip 31, the pulse signal 1 received at the pin 2 is latched, and the control pin 19 stops outputting the pulse signal and continues outputting the low level.
When the pin 11 output of the chip 21 74LS90 is at high level and the pin 8 is at low level, D10 is turned on, the output high level passes through the resistors R11 to D10, and finally the output disable signal is output to the chip 31 74HC 573; while pin 3, pin 6, and pin 7 of the 74LS90 chip 21 are all set high to maintain the output disable output signal.
When the pin 8 output of the chip 21 74LS90 is at high level and the pin 11 is at low level, D11 is turned on, the output high level passes through the resistors R12 to D11, and finally the output prohibition signal is output to the chip 31 74HC 573; also causing 74LS90 chip 21 to have pin 3, pin 6, and pin 7 all set high.
Therefore, when the number of pulses in the pulse signal reaches the preset number, the counter 20 continuously sends an output inhibiting signal to the latch 30, the latch 30 stops outputting the pulse signal in time and continuously outputs a low level, the stability of the pulse signal output device and the accuracy of the output pulse number are ensured, and the working efficiency is improved.
In some embodiments, the counter 20 is an edge triggered counter 20, which is used to detect a preset level transition in the pulse signal generated by the pulse signal generator 10, count the number of preset level transitions, and determine the number of pulse signals generated by the pulse signal generator 10 according to the counted number of preset level transitions.
The edge triggered counter 20 refers to the input data when a predetermined transition (positive transition or negative transition) of the received clock pulse CP arrives. And the trigger does not receive data when the CP is 1 and 0 and the CP unconventional jump arrives.
The preset level transition refers to a condition for triggering a counting operation, which is preset in the edge triggered counter 20, and is generally set to a state where a high level changes to a low level (positive to negative) corresponding to a falling edge of the pulse signal, or a state where a low level changes to a high level (negative to positive) corresponding to a rising edge of the pulse signal. The 74LS90 chip 21 in this embodiment triggers a count operation by detecting a falling edge in the pulse signal.
Specifically, when the chip 21 of the 74LS90 in the edge triggered counter 20 detects that the level of the pulse signal 1 received by the pin 1 changes, and only one falling edge exists in one pulse signal of the square wave pulse signal, it can be determined that one pulse signal is generated when the level of the pulse signal changes from high level to low level, so as to trigger the operation of counting and adding one; finally, the number of the pulse signals generated by the pulse signal generator 10 can be determined by counting the number of preset level transitions.
In other embodiments, the counter 20 may adopt a T-trigger counter 20, and determine the number of pulse signals by detecting the rising edges in the pulse signals and counting the number of rising edges in the pulse signals.
Therefore, the edge trigger counter 20 detects the level conversion in the pulse signals and determines the number of the generated pulse signals, so that the pulse signals are counted more accurately, counting errors are reduced, and loss caused in the production process is avoided.
In some embodiments, the pulse signal generator 10 includes a frequency knob 12 and a pulse width knob 13, the frequency knob 12 is used for adjusting the frequency of the pulse signal generated by the pulse signal generator 10, and the pulse width knob 13 is used for adjusting the pulse width and the frequency of the pulse signal generated by the pulse signal generator 10.
As shown in fig. 1 and 2, the pulse width knob 13 is connected to the slide rheostat R5 for changing the resistance value of the slide rheostat R5, and the frequency knob 12 is connected to the slide rheostat R6 for changing the resistance value of the slide rheostat R6. The pulse width knob 13 adjusts the pulse width and the frequency of the pulse signal generated by the pulse signal generator 10 by adjusting the resistance value of the slide rheostat R5, and the frequency knob 12 adjusts only the frequency of the pulse signal generated by the pulse signal generator 10 by adjusting the resistance value of the slide rheostat R6.
Specifically, the pulse width knob 13 is connected to a slider on the slide rheostat R5, and the pulse width knob 13 rotates to drive the slider of the slide rheostat R5 to move correspondingly, so that the resistance value of the slide rheostat R5 changes, and the resistance values on the charging circuit and the discharging circuit change to different degrees, and the time required by the charging process and the time required by the discharging process of the capacitor C2 are changed due to the change of the resistance values on the charging circuit and the discharging circuit, so that the pulse width and the frequency of the pulse signal generated by the pulse signal generator 10 are adjusted according to the high-level time and the low-level time of the generated pulse signal influenced by different degrees.
The frequency knob 12 is connected with a slider on the slide rheostat R6, the pulse width knob 12 drives the slider of the slide rheostat R6 to move correspondingly when rotating, so that the resistance value of the slide rheostat R6 changes, the resistance values on the charging loop and the discharging loop change in the same amplitude, and the high level time and the low level time of the pulse signal in one period are changed in the same degree, so that the frequency of the square wave pulse signal is adjusted.
For example, if the resistance value of the left side of the slider on the slide rheostat R5 is R5a, the resistance value of the right part of the slide rheostat R5 is R5b, the change of the resistance R5a corresponds to the resistance value on the adjusting charging circuit, and the change of the resistance R5b corresponds to the resistance value on the adjusting discharging circuit; if the high level time and the low level time of the square wave pulse in one period are Th and Tl, Th is 0.693 (R1+ R5a + R6) C2.
Tl＝0.693*(R5b+R6)*C2。
The square wave pulse frequency is F ═ 1/(Th + Tl).
Therefore, the adjustment of the sliding rheostat R5 affects the high level time and the low level time of the square wave pulse in one period at the same time to different degrees, thereby affecting the frequency and the pulse width of the pulse signal. Therefore, in this embodiment, the pulse width knob 13, i.e. the slide rheostat R5, should be adjusted to adjust the pulse width of the pulse signal to a proper value, and then the frequency knob 12, i.e. the slide rheostat R6, should be adjusted to adjust the frequency of the pulse signal to a proper value; the appropriate values refer to the pulse width value and the frequency value of the pulse signal to be output.
Therefore, the resistance value of the sliding rheostat in the circuit of the pulse signal generator 10 is adjusted, the time of a charging loop and the time of a discharging loop in the pulse signal generator 10 are changed, the frequency and the pulse width of the pulse signal are adjusted, the pulse signal output device is favorably applied to more production links, the adjustability of the pulse performance is improved, and the working efficiency is improved.
Referring to fig. 6, fig. 6 is a flowchart illustrating a pulse signal output method according to an embodiment of the present invention.
In some embodiments, the method comprises: in step S1, a pulse signal is generated by the pulse signal generator 10.
In step S2, the number of pulse signals generated by the pulse signal generator 10 is counted by the counter 20.
In step S3, the latch 30 receives the pulse signals generated by the pulse signal generator 10, and controls the number of output pulse signals according to the number of pulse signals counted by the counter 20.
In some embodiments, the latch 30 controls to output the received pulse signal generated by the pulse signal generator 10 when the number of pulse signals counted by the counter 20 is less than a preset number;
the latch 30 controls to stop outputting the received pulse signal when the number of the pulse signals counted by the counter 20 reaches the preset number.
Specifically, the values of the corresponding ports of the 74LS90 chip 21 are set in advance according to the number of pulses to be output, and the setting of the preset number is completed.
As shown in fig. 4 and fig. 5, in the counting process of the 74LS90 chip 21, when the current count value of the 74LS90 chip 21 is less than the preset number, that is, the number of square waves in the pulse signal 2 received by the 74LS90 chip 21 is less than the preset number, both the pin 11 and the pin 8 of the 74LS90 chip 21 output a low level; the pin 11 of the 74HC573 chip 31 does not receive the high level signal, and the 74HC573 chip 31 does not latch the received pulse signal 1, i.e. the 74HC573 chip 31 directly outputs the pulse signal 1 after receiving the pulse signal 1.
When the current count value of the 74LS90 chip 21 is greater than or equal to the preset number, that is, when the number of square waves in the pulse signal 2 received by the 74LS90 chip 21 reaches the preset number, either the pin 11 or the pin 8 of the 74LS90 chip 21 outputs a high level, and after the pin 11 of the 74HC573 chip 31 receives the high level, the 74HC573 chip 31 performs a latch operation on the pulse signal, that is, in a case where the pin 2 of the 74HC573 chip 31 continues to receive the pulse signal 1, the control pin 19 stops outputting the pulse signal.
In other embodiments, the pulse signal generator 10 may be implemented by different chips to generate sine wave, triangle wave, etc. for example, the chip of the pulse signal generator 10 may be implemented by ICL8038, XR-2206, etc.
In other embodiments, the counter 20 may be formed by chips such as 74LS109, 74ALS109, 74HC109, 74HCT109, and the like in the counter 20.
In other embodiments, the latch 30 may be implemented with chips 74LS244, 74LS373, 74hc373, and so on.
Therefore, the counter 20 counts the number of the pulse signals, determines whether the number of the pulse signals generated by the pulse signal generator 10 reaches a preset number, and controls the output of the pulse signals through the latch 30, so that the accurate control of the output number of the pulse signals is realized, and the application range of the pulse signal output device in the production process is expanded.
In some embodiments, the controlling, by the latch 30, to stop outputting the received pulse signal when the number of pulse signals counted by the counter 20 reaches the preset number includes: when the number of the pulse signals counted by the counter 20 reaches a preset number, an output inhibiting signal is sent to the latch 30, and after the latch 30 receives the output inhibiting signal sent by the counter 20, the output of the pulse signals is stopped, and the pulse signals are continuously in a low level output state.
As shown in fig. 4 and 5, specifically, when the 74LS90 chip 21 detects that the number of square waves in the pulse signal 2 received by the pin 1 reaches the preset number, the control pin 11 or the pin 8 continuously outputs a high level, and continuously sends a high level signal to the pin 11 of the 74HC573 chip 31, that is, the output signal is disabled; when the disable output signal is received at the pin 11 of the 74HC573 chip 31, the pulse signal 1 received at the pin 2 is latched, and the control pin 19 stops outputting the pulse signal and continues outputting the low level.
When the pin 11 output of the chip 21 74LS90 is at high level and the pin 8 is at low level, D10 is turned on, the output high level passes through the resistors R11 to D10, and finally the output disable signal is output to the chip 31 74HC 573; while pin 3, pin 6, and pin 7 of the 74LS90 chip 21 are all set high to maintain the output disable output signal.
When the pin 8 output of the chip 21 74LS90 is at high level and the pin 11 is at low level, D11 is turned on, the output high level passes through the resistors R12 to D11, and finally the output prohibition signal is output to the chip 31 74HC 573; also causing 74LS90 chip 21 to have pin 3, pin 6, and pin 7 all set high.
Therefore, when the number of pulses in the pulse signal reaches the preset number, the counter 20 continuously sends an output inhibiting signal to the latch 30, the latch 30 stops outputting the pulse signal in time and continuously outputs a low level, the stability of the pulse signal output device and the accuracy of the output pulse number are ensured, and the working efficiency is improved.
In some embodiments, the counter 20 is an edge triggered counter 20, and the step S2 includes: detecting a preset level transition in the pulse signal generated by the pulse signal generator 10 through the edge trigger counter 20, and counting the number of times of the preset level transition; the number of pulse signals generated by the pulse signal generator 10 is determined according to the counted preset level transition times.
Specifically, when the chip 21 of the 74LS90 in the edge triggered counter 20 detects that the level of the pulse signal 1 received by the pin 1 changes, and only one falling edge exists in one pulse signal of the square wave pulse signal, it can be determined that one pulse signal is generated when the level of the pulse signal changes from high level to low level, so as to trigger the operation of counting and adding one; finally, the number of the pulse signals generated by the pulse signal generator 10 can be determined by counting the number of preset level transitions.
In other embodiments, the counter 20 may adopt a T-trigger counter 20, and determine the number of pulse signals by detecting the rising edges in the pulse signals and counting the number of rising edges in the pulse signals.
Therefore, the edge trigger counter 20 detects the level conversion in the pulse signals and determines the number of the generated pulse signals, so that the pulse signals are counted more accurately, counting errors are reduced, and loss caused in the production process is avoided.
Referring to fig. 7, fig. 7 is a sub-flowchart of step S1 in fig. 6.
In some embodiments, the pulse signal generator 10 includes a frequency knob 12 and a pulse width knob 13, and the step S1 includes: in step S11, the pulse width and frequency of the pulse signal generated by the pulse signal generator 10 are adjusted by the pulse width knob 13.
In step S13, the frequency of the pulse signal generated by the pulse signal generator 10 is adjusted by the frequency knob 12.
Specifically, the pulse width knob 13 is connected to a slider on the slide rheostat R5, and the pulse width knob 13 rotates to drive the slider of the slide rheostat R5 to move correspondingly, so that the resistance value of the slide rheostat R5 changes, and the resistance values on the charging circuit and the discharging circuit change to different degrees, and the time required by the charging process and the time required by the discharging process of the capacitor C2 are changed due to the change of the resistance values on the charging circuit and the discharging circuit, so that the pulse width and the frequency of the pulse signal generated by the pulse signal generator 10 are adjusted according to the high-level time and the low-level time of the generated pulse signal influenced by different degrees.
The frequency knob 12 is connected with a slider on the slide rheostat R6, the pulse width knob 12 drives the slider of the slide rheostat R6 to move correspondingly when rotating, so that the resistance value of the slide rheostat R6 changes, the resistance values on the charging loop and the discharging loop change in the same amplitude, and the high level time and the low level time of the pulse signal in one period are changed in the same degree, so that the frequency of the square wave pulse signal is adjusted.
For example, if the resistance value of the left side of the slider on the slide rheostat R5 is R5a, the resistance value of the right part of the slide rheostat R5 is R5b, the change of the resistance R5a corresponds to the resistance value on the adjusting charging circuit, and the change of the resistance R5b corresponds to the resistance value on the adjusting discharging circuit; if the high level time and the low level time of the square wave pulse in one period are Th and Tl, Th is 0.693 (R1+ R5a + R6) C2.
Tl＝0.693*(R5b+R6)*C2。
The square wave pulse frequency is F ═ 1/(Th + Tl).
Therefore, the adjustment of the sliding rheostat R5 affects the high level time and the low level time of the square wave pulse in one period at the same time to different degrees, thereby affecting the frequency and the pulse width of the pulse signal. Therefore, in this embodiment, the pulse width knob 13, i.e. the slide rheostat R5, should be adjusted to adjust the pulse width of the pulse signal to a proper value, and then the frequency knob 12, i.e. the slide rheostat R6, should be adjusted to adjust the frequency of the pulse signal to a proper value; the appropriate values refer to the pulse width value and the frequency value of the pulse signal to be output.
Therefore, the resistance value of the sliding rheostat in the circuit of the pulse signal generator 10 is adjusted, the time of a charging loop and the time of a discharging loop in the pulse signal generator 10 are changed, the frequency and the pulse width of the pulse signal are adjusted, the pulse signal output device is favorably applied to more production links, the adjustability of the pulse performance is improved, and the working efficiency is improved.
The pulse signal output method of the present invention is applied to the aforementioned pulse signal output apparatus, and the steps of the executed method correspond to the functions executed by the aforementioned pulse signal output apparatus, and more specific description can refer to the relevant contents of the aforementioned pulse signal output apparatus.
Therefore, the pulse signal output device and the method thereof provided by the invention effectively control the number of the output pulse signals through the cooperation of the counter 20 and the latch 30, so that the pulse signals generated by the pulse signal generator 10 can be applied to the production process of more products, the manpower and equipment cost investment in the production process is reduced, and the production efficiency is improved.
The foregoing is illustrative of embodiments of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the embodiments of the present invention and are intended to be within the scope of the present invention.
Claims (10)
1. A pulse signal output apparatus for generating a pulse signal, comprising:
a pulse signal generator for generating a pulse signal;
the counter is connected with the pulse signal generator and is used for counting the number of the pulse signals generated by the pulse signal generator;
and the latch is connected with the pulse signal generator and the counter and used for receiving the pulse signals generated by the pulse signal generator and controlling the number of the output pulse signals according to the number of the pulse signals counted by the counter.
2. The pulse signal output device according to claim 1, wherein the latch controls to output the received pulse signal generated by the pulse signal generator when the number of pulse signals counted by the counter is smaller than a preset number; and the latch controls to stop outputting the received pulse signals when the number of the pulse signals counted by the counter reaches the preset number.
3. The pulse signal output device according to claim 2, wherein when the number of pulse signals counted by the counter reaches a preset number, an output prohibition signal is sent to the latch, and the latch stops outputting the pulse signal and continues to be in the low level output state after receiving the output prohibition signal sent by the counter.
4. A pulse signal output apparatus according to claim 1, wherein the counter is an edge triggered counter for detecting a predetermined level transition in the pulse signal generated by the pulse signal generator and counting the number of the predetermined level transitions, and the number of the pulse signals generated by the pulse signal generator is determined based on the counted number of the predetermined level transitions.
5. A pulse signal output device according to claim 1, wherein the pulse signal generator includes a frequency knob for adjusting a frequency of the pulse signal generated by the pulse signal generator and a pulse width knob for adjusting a pulse width and a frequency of the pulse signal generated by the pulse signal generator.
6. A pulse signal output method is applied to a pulse signal output device, and is characterized by comprising the following steps:
step S1, generating a pulse signal by a pulse signal generator;
step S2, counting the number of pulse signals generated by the pulse signal generator through a counter;
and step S3, receiving the pulse signals generated by the pulse signal generator through the latch, and controlling the number of the output pulse signals according to the number of the pulse signals counted by the counter.
7. A pulse signal output method according to claim 6, wherein said step S3 includes:
the latch controls the output of the received pulse signals generated by the pulse signal generator when the number of the pulse signals counted by the counter is smaller than a preset number;
and the latch controls to stop outputting the received pulse signals when the number of the pulse signals counted by the counter reaches the preset number.
8. The pulse signal output method according to claim 7, wherein said controlling the latch to stop outputting the received pulse signal when the number of pulse signals counted by the counter reaches the preset number includes:
and when the number of the pulse signals counted by the counter reaches a preset number, the latch sends an output inhibiting signal to the latch, and after the latch receives the output inhibiting signal sent by the counter, the latch stops outputting the pulse signals and is continuously in a low-level output state.
9. The pulse signal output method according to claim 6, wherein the counter is an edge triggered counter, and the step S2 includes:
detecting preset level conversion in the pulse signal generated by the pulse signal generator through the edge trigger counter, and counting the times of the preset level conversion; and determining the number of the pulse signals generated by the pulse signal generator according to the counted preset level conversion times.
10. A pulse signal output method according to claim 6, wherein said pulse signal generator includes a frequency knob and a pulse width knob, said step S1 includes:
step S11, adjusting the pulse width and frequency of the pulse signal generated by the pulse signal generator through the pulse width knob;
and step S13, adjusting the frequency of the pulse signal generated by the pulse signal generator through the frequency knob.
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