CN110531825B - Amplifier circuit system, voltage regulating circuit and signal compensation method - Google Patents

Amplifier circuit system, voltage regulating circuit and signal compensation method Download PDF

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Publication number
CN110531825B
CN110531825B CN201810500148.XA CN201810500148A CN110531825B CN 110531825 B CN110531825 B CN 110531825B CN 201810500148 A CN201810500148 A CN 201810500148A CN 110531825 B CN110531825 B CN 110531825B
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output signal
bias current
mode output
common
resistor
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CN110531825A (en
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王銣傑
李易霖
陈彦中
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Global Unichip Corp
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Global Unichip Corp
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
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Abstract

An amplifier circuit system, a voltage regulating circuit and a signal compensation method. The amplifier circuit system comprises a current source circuit, a voltage regulating circuit and a first amplifier. The current source circuit generates a first bias current. The voltage regulation circuit regulates a reference voltage to generate a supply voltage. The voltage regulating circuit comprises a first compensating resistor and a second compensating resistor, wherein the first compensating resistor and the second compensating resistor are used for generating a reference voltage according to a reference current and a second bias current, and a first proportion is formed between the second bias current and the first bias current. The first amplifier comprises a plurality of first load resistors, and the first load resistors generate a first common-mode output signal based on a supply voltage and a first bias current. The second compensation resistor has a second ratio with one of the first load resistors, and the first ratio and the second ratio are set to compensate the first common mode output signal. The scheme can be realized through simple operation and electronic elements so as to stabilize the output of the circuit system and reduce the influence of environmental factors on the circuit system.

Description

Amplifier circuit system, voltage regulating circuit and signal compensation method
Technical Field
The present disclosure relates to amplifier circuitry, and more particularly to amplifier circuitry including a voltage regulation circuit for compensating for common mode signals.
Background
Amplifier circuits are common in a variety of applications. The amplifier circuit can amplify an input signal to generate an output signal. However, in practice the output voltage produced by the amplifier circuit may be affected by environmental parameters (e.g. temperature, especially at the time of manufacture, on the integrated circuit). As such, an offset will be caused to the output of the amplifier circuitry.
Disclosure of Invention
Accordingly, the present disclosure provides an amplifier circuit system and a signal compensation method for compensating a signal by a voltage regulator circuit, so as to solve the problems described in the prior art.
One embodiment of the present disclosure relates to an amplifier circuitry comprising a current source circuit, a voltage regulating circuit, and a first amplifier. The current source circuit is used for generating a first bias current. The voltage regulating circuit is used for regulating the reference voltage to generate a supply voltage. The voltage regulating circuit comprises a first compensating resistor and a second compensating resistor, wherein the first compensating resistor and the second compensating resistor are used for generating a reference voltage according to a reference current and a second bias current, and a first proportion is formed between the second bias current and the first bias current. The first amplifier comprises a plurality of first load resistors, and the first load resistors are used for generating a first common-mode output signal based on a supply voltage and a first bias current. The second compensation resistor has a second ratio with one of the first load resistors, and the first ratio and the second ratio are set to compensate the first common mode output signal.
In some embodiments, the first amplifier further comprises a variable resistor coupled to the plurality of first load resistors, the variable resistor configured to receive the supply voltage to adjust the first common-mode output signal in cooperation with the plurality of first load resistors.
In some embodiments, the first common-mode output signal satisfies the following equation:
VCM1＝IB1(MNRL1-RV1-0.5RL1)+IREF(RC1+NRL1)
wherein VCM1For the first common-mode output signal, IREFIs the current value of the reference current, RC1Is the resistance value, R, of the first compensation resistorL1Is the resistance value, I, of one of the first load resistorsB1Is the current value of the first bias current, RV1M is the first ratio and N is the second ratio.
In some embodiments, the first ratio, the second ratio and the resistance of the variable resistor are set to cancel an offset associated with the first common mode output signal.
In some embodiments, the first ratio, the second ratio and the resistance of the variable resistor are set to set the correlation between the first common mode output signal and the first bias current.
In some embodiments, the amplifier circuitry further includes a second amplifier coupled to the first amplifier, the second amplifier including a plurality of second load resistors configured to generate a second common mode output signal based on the supply voltage and the first bias current.
In some embodiments, the second amplifier further includes a variable resistor coupled to the second load resistors, the variable resistor being configured to receive the supply voltage to adjust the second common mode output signal in cooperation with the second load resistors.
In some embodiments, the voltage regulating circuit further comprises a regulator for generating the supply voltage according to the reference voltage, wherein the first compensation resistor is coupled to the second compensation resistor for generating the reference voltage according to the reference current and the second bias current.
In some embodiments, a first terminal of the first compensation resistor is configured to receive the reference current and output the reference voltage, a second terminal of the first compensation resistor is configured to be coupled to a first terminal of the second compensation resistor, the first terminal of the second compensation resistor is configured to receive the second bias current, and a second terminal of the second compensation resistor is coupled to ground.
In some embodiments, the first common-mode output signal satisfies the following equation:
VCM1＝IB1(MNRL1-0.5RL1)+IREF(RC1+NRL1)
wherein VCM1For the first common-mode output signal, IREFIs the current value of the reference current, RC1Is the resistance value, R, of the first compensation resistorL1Is the resistance value, I, of one of the first load resistorsB1The current value of the first bias current, M is the first ratio, and N is the second ratio.
In some embodiments, the first ratio and the second ratio are set to cancel an offset associated with the first common-mode output signal.
One embodiment of the present disclosure relates to a voltage regulating circuit for compensating a common mode output signal generated by an amplifier circuit through two load resistors, the amplifier circuit biased by a supply voltage and a first bias current, and the voltage regulating circuit comprising a first compensation resistor, a second compensation resistor, and a regulator. The first compensation resistor is used for receiving a reference current. The second compensation resistor is coupled between the first compensation resistor and ground, wherein the second compensation resistor is used for cooperating with the first compensation resistor to generate a reference voltage according to a second bias current and a reference current, wherein a first proportion exists between the second bias current and the first bias current, a second proportion exists between the second compensation resistor and one of the load resistors, and the first proportion and the second proportion are set to compensate the common-mode output signal. The regulator is used for regulating the reference voltage to generate the supply voltage.
One embodiment of the present disclosure relates to a signal compensation method. The signal compensation method comprises the following steps: generating a first bias current by a current source circuit; adjusting, by a voltage adjustment circuit, a reference voltage to generate a supply voltage; a first common mode output signal is generated by a first amplifier. The voltage regulating circuit comprises a first compensating resistor and a second compensating resistor, wherein the first compensating resistor and the second compensating resistor are used for generating a reference voltage according to a reference current and a second bias current, and a first proportion is formed between the second bias current and the first bias current. The first amplifier comprises a plurality of first load resistors, and the first load resistors are used for generating a first common-mode output signal based on a supply voltage and a first bias current. The second compensation resistor has a second ratio with one of the first load resistors, and the first ratio and the second ratio are configured to compensate the first common mode output signal.
In some embodiments, generating the first common-mode output signal further comprises adjusting the first common-mode output signal in cooperation with the plurality of first load resistors through a variable resistor, wherein the variable resistor is coupled to the plurality of first load resistors and configured to receive the supply voltage.
In some embodiments, the first ratio, the second ratio and the variable resistance are set to cancel an offset associated with the first common mode output signal or to set a correlation between the first common mode output signal and the first bias current.
In some embodiments, the signal compensation method further comprises generating a second common-mode output signal by a second amplifier, wherein the second amplifier comprises a plurality of second load resistors configured to generate the second common-mode output signal based on the supply voltage and the first bias current.
In some embodiments, generating the second common mode output signal further comprises adjusting the second common mode output signal by a variable resistor in cooperation with the plurality of second load resistors, wherein the variable resistor is coupled to the plurality of second load resistors and configured to receive the supply voltage.
In some embodiments, generating the supply voltage further comprises generating the supply voltage according to the reference voltage through a regulator, wherein the first compensation resistor is coupled to the second compensation resistor to generate the reference voltage according to the reference current and the second bias current.
In some embodiments, generating the reference voltage further comprises receiving the reference current through a first terminal of the first compensation resistor and outputting the reference voltage, and receiving the second bias current through the first terminal of the second compensation resistor. The second terminal of the first compensation resistor is coupled to the first terminal of the second compensation resistor. The second terminal of the second compensation resistor is coupled to ground.
In some embodiments, the first ratio and the second ratio are arranged to cancel an offset associated with the first common-mode output signal or to set a correlation between the first common-mode output signal and the first bias current.
In summary, the amplifier circuit system and the signal compensation method thereof provided by the present disclosure can be implemented by simple operations and electrical elements, so as to stabilize the output of the circuit system and reduce the influence of environmental factors on the circuit system.
Drawings
The disclosure may be more completely understood in consideration of the following detailed description of exemplary embodiments in connection with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of amplifier circuitry according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of amplifier circuitry according to some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of amplifier circuitry according to some embodiments of the present disclosure; and
fig. 4 is a flow chart of a signal compensation method according to some embodiments of the present disclosure and the method shown in fig. 3.
Detailed Description
The following detailed description of the embodiments is provided in conjunction with the appended drawings, but the embodiments described are merely illustrative of the embodiments and are not intended to limit the scope of the embodiments, and the description of the structural operations is not intended to limit the order of execution, any arrangement of elements that can be rearranged to produce a device with equal efficacy, all of which are intended to cover the scope of the disclosure.
As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.
Refer to fig. 1. Fig. 1 is a schematic diagram of amplifier circuitry 100 according to some embodiments of the present disclosure. In some embodiments, the current source circuit 120 is used to provide the first bias current IB1The first amplifier circuit 140 is provided with a voltage regulation circuit 160 for providing a supply voltage VDDRTo the first amplifier circuit 140. Accordingly, the first amplifier circuit 140 can be based on the first bias current IB1 and the supply voltage VDDRIs biased. Under this condition, the first amplifier circuit 140 may be responsive to the input signal VinOutputting a first common-mode output signal VCM1。
In some embodiments, the input signal VinHaving a dc signal component (e.g., a common mode input voltage) and an ac signal component. In some embodiments, the first amplifier circuit 140 may be biased by a first bias current IB1A supply voltage VDDRAnd an input signal VinIs biased to amplify the input signal VinExchange ofThe signal component generates an output signal (not shown). In some embodiments, the first common-mode output signal VCM1Is a dc signal component of the output signal of the first amplifier circuit 140.
In some embodiments, the amplifier circuitry 100 may further comprise an alternating current-coupled (AC-coupled) circuit (not shown) for providing a DC bias to the gates of the transistors T1-T2 and for transmitting the input signal Vin(in this case, an AC signal) to the transistors T1-T2. In some embodiments, the ac coupling circuit may be implemented by one or more resistive elements, capacitive elements, and bias circuits, but the disclosure is not limited thereto.
Taking the example of fig. 1, in some embodiments, the first amplifier circuit 140 includes two first load resistors RL1And two transistors T1, T2. In some embodiments, the first load resistors RL1Are identical to each other. These first load resistors RL1Is coupled to the voltage regulating circuit 160 to receive the supply voltage VDDRThese first load resistors RL1Respectively coupled to the first terminals of the transistors T1-T2 to output a first common mode output signal VCM1. The second terminals of the transistors T1-T2 are coupled to the current source circuit 120. The control terminals of the transistors T1-T2 are used for receiving an input signal Vin。
In some embodiments, the transistors T1-T2 are configured as a differential input pair. The transistors T1-T2 are all the same size. Under this condition, the transistors T1, T2 are driven by the input signal VinWhen conducting, there will be half of the first bias current IB1Through transistor T1 or through transistor T2. Similarly, the half of the first bias current IB1Will also flow through each first load resistor RL1. Therefore, when the transistors T1, T2 are turned on, the first load resistors RL1May be based on the supply voltage VDDRAnd a first bias current IB1Generating a first common-mode output signal VCM1。
In some embodiments, the current source circuit 120 includes a current mirror (not shown). For example, the current source circuit 120 may be implemented by a current mirror circuit with fixed transconductance-gm. The above-described implementation of the current source circuit 120 is merely exemplary, and various components that can implement the current source circuit 120 are within the scope of the disclosure.
In some embodiments, the voltage regulation circuit 160 may regulate the reference voltage VREFTo generate a supply voltage VDDRWherein the reference voltage VREFMay be generated by one or more resistive elements and one or more bias currents.
For example, in some embodiments, the voltage regulation circuit 160 includes a first compensation resistor RC1A second compensation resistor RC2And a regulator 165. First compensation resistor RC1First end of (i.e., node n)1) For receiving a reference current IREFFirst compensation resistor RC1A second terminal of the first resistor is coupled to a second compensation resistor RC2First end of (i.e., node n)2). Second compensation resistor RC2The first terminal of the first transistor is used for receiving a second bias current IB2. Second compensation resistor RC2Is coupled to ground. First compensation resistor RC1Is used for generating a reference voltage VREF. First compensation resistor RC1And a second compensation resistor RC2For determining the reference current IREFAnd a second bias current IB2Generating a supply voltage VREF。
Regulator 165 is coupled to first compensation resistor RC1To receive a reference voltage VREF. The regulator 165 is used for regulating the reference voltage VREFTo generate a supply voltage VDDRAt node n3. In some embodiments, the reference voltage VREFAbout the same as the supply voltage VDDR. In still other embodiments, voltage regulation circuit 160 may not include regulator 165, but directly regulate reference voltage VREFOutput as a supply voltage VDDR。
In some embodiments, the reference current IREFThe current that can be generated by a semiconductor bandgap (bandgap) reference circuit. In some embodiments, the semiconductor bandgap referenceThe current generated by the circuit is substantially unaffected by environmental parameters, such as temperature. Various reference currents I to be realizedREFAre within the scope of the present disclosure.
In some embodiments, the second bias current IB2Is a shunt (not shown) of the current mirror circuit of the current source circuit 120, and the second bias current IB2Less than the first bias current IB1. Various kinds of second bias currents I are realizedB2Are within the scope of the present disclosure.
In some embodiments, the second bias current IB2And a first bias current IB1Has a first ratio M, and this relationship can be expressed by the following formula (1):
IB2＝M×IB1…(1)
wherein, in some embodiments, the first ratio M may be set to be less than 1.
In some embodiments, the second compensation resistor RC2And a first load resistor RL1Has a second ratio N, and this relationship can be expressed by the following equation (2):
RC2＝N×RL1…(2)。
in some embodiments, at reference voltage VREFThis can be obtained by the following equation (3):
VREF＝MIB1×NRL1+IREF(RC1+NRL1)…(3)
wherein the reference voltage VREFIs a node n1The voltage value of (2).
As previously described, in some embodiments, the reference voltage VREFAbout the same as the supply voltage VDDR(i.e., node n)1Voltage value of and node n3Equal in voltage value). Under this condition, when the transistors T1-T2 are all turned on, the first common mode output signal VCM1The voltage value of (2) can be derived from the following equations (1) and (3):
VCM1＝VDDR-0.5×IB1×RL1…(4)
as can be seen from the formula (4), the first load resistance RL1May be based on the supply voltage VDDRAnd a first bias current IB1Generating a first common-mode output signal VCM1。
Substituting the formula (3) into the formula (4) leads to the following formula (5):
VCM1＝IB1(MNRL1-0.5RL1)+IREF(RC1+NRL1)…(5)
in some embodiments, the first ratio M and the second ratio N may be set to compensate for the first common-mode output signal VCM1. For example, if M is set to 1/8 and N is set to 4, the product of M and N is 0.5. Under this condition, the above formula (5) can be expressed as the following formula (6):
VCM1＝IREF(RC1+NRL1)…(6)。
the values M, N are exemplary only, and other values that can be used in the embodiments of the disclosure are within the scope of the disclosure.
In some related art, the common-mode output voltage of the amplifier circuit (e.g., V of FIG. 1)CM1) Constant bias current (e.g. I of FIG. 1)B1) Are directly related. In these related arts, the bias current may be affected by various variations (e.g., process, voltage, temperature variations) to generate an offset, so that the common-mode output voltage of the amplifier also has an offset. As a result, the accuracy of the amplifier may be degraded or the operation of the amplifier may be faulty.
Compared to the related art, according to the formula (6), the first common-mode output signal V is obtained by the voltage regulating circuit 160 of the present disclosureCM1Can be matched with the first bias current IB1Is irrelevant. Thus, the first common-mode output signal VCM1Will not be caused by the first bias current IB1A deviation occurs due to the variation of (c). In other words, in the present disclosure, the first common-mode output signal V can be compensated by setting the first ratio M and the second ratio NCM1Is subjected to a first bias current IB1The effect of the offset.
Further, according to the formula (6), 1A common mode output signal VCM1With respect to reference current I onlyREF. As previously mentioned, reference current IREFThe current generated by the semiconductor bandgap reference circuit is not susceptible to variation. Thus, the first common-mode output signal VCM1Can have a more stable voltage value.
Refer to fig. 2. Fig. 2 is a schematic diagram of amplifier circuitry 200 according to some embodiments of the present disclosure. For ease of understanding, like elements of FIG. 2 are numbered in FIG. 1.
In contrast to fig. 1, the amplifier circuitry 200 of fig. 2 includes multiple stages of amplifier circuits 240 and 250. In some embodiments, the current source circuit 220 is used for providing the first bias current IB1The first amplifier circuit 240 and the second amplifier circuit 250, and the voltage regulator circuit 260 for providing the supply voltage VDDRTo the first amplifier circuit 240 and the second amplifier circuit 250. Accordingly, the bias conditions of the first amplifier circuit 240 and the second amplifier circuit 250 can be based on the first bias current IB1And a supply voltage VDDRAnd (4) setting. Under this condition, the first amplifier circuit 240 may be responsive to the input signal VinOutputting a first common-mode output signal VCM1And the second amplifier circuit 250 may be responsive to the first common-mode output signal VCM1Outputting a second common mode output signal VCM2. By providing the second amplifier circuit 250, the amplifier circuitry 200 may have a higher gain compared to fig. 1.
Compared to the first amplifier circuit 140 of fig. 1, the first amplifier circuit 240 further includes a first variable resistor RV1. In some embodiments, the first variable resistor RV1And the first load resistors RL1To be based on a supply voltage VDDRAnd a first bias current IB1Generating a first common-mode output signal VCM1。
A first terminal of the first variable resistor RV1 is coupled to the voltage regulating circuit 260, and the first variable resistor RV1Is coupled to the first load resistors RL1The first end of (a). These first load resistors RL1The second terminal of the first transistor is used for outputting the first voltageCommon mode output signal VCM1And are coupled to first terminals of the transistors T1 and T2, respectively. The second terminals of the transistors T1 and T2 are coupled to the current source circuit 220. The control terminals of the transistors T1 and T2 are used for receiving an input signal Vin。
In this case, the aforementioned formula (5) can be modified to the following formula (7):
VCM1＝IB1(MNRL1-RV1-0.5RL1)+IREF(RC1+NRL1)…(7)
according to equation (7), if it is related to the first bias current IB1Coefficient of (MNR)L1-RV1-0.5RL1) Is positive, then the first common-mode output signal VCM1And a first bias current IB1Is positively correlated. Or, in an alternative embodiment, the first bias current I in equation (7)B1Coefficient of (MNR)L1-RV1-0.5RL1) Negative, the first common-mode output signal VCM1And a first bias current IB1Is a negative correlation. In other embodiments, the first bias current I in equation (7)B1Coefficient of (MNR)L1-RV1-0.5RL1) Can be set to 0 to eliminate the first common mode output signal VCM1Is subjected to a first bias current IB1The resulting offset.
In other words, in this example, the first variable resistor RV1Arranged in conjunction with these first load resistors RL1Adjusting a first common-mode output signal VCM1. By the arrangement, the first common mode output signal V can be adjusted more flexiblyCM1And a first bias current IB1The correlation of (c). Thus, the first variable resistor R can be adjusted according to the actual variationV1To compensate the first common mode output signal VCM1Of (3) is detected.
With continued reference to fig. 2, and by way of example in fig. 2, in some embodiments the second amplifier circuit 250 includes two second load resistors RL2A second variable resistor RV2And two transistors T3, T4. Second variable resistor RV2Is coupled to the voltage regulating circuit 260 and the second variable resistorRV2Is coupled to the second load resistors RL2The second load resistors RL2Is used for outputting a second common mode output signal VCM2And are coupled to first terminals of the transistors T3 and T4, respectively. The second terminals of the transistors T3 and T4 are coupled to the current source circuit 220. The control terminals of the transistors T3 and T4 are respectively used for receiving the first common mode output signal VCM1. Second variable resistor RV2And these second load resistors RL2To be based on a supply voltage VDDRAnd a first bias current IB1Generating a second common-mode output signal VCM2. The configuration of the second amplifier circuit 250 can refer to the configuration of the first amplifier circuit 240, and thus, the description thereof is not repeated.
In addition, in various embodiments, the variable resistor RV1And RV2Is a selective setting. For example, in some embodiments, the second amplifier circuit 250 may not employ the second variable resistor RV2. Alternatively, in some embodiments, only the first amplifier circuit 240 may employ the first variable resistor RV1. All such arrangements are within the scope of the present disclosure.
Refer to fig. 3. Fig. 3 is a schematic diagram of amplifier circuitry 300 according to some embodiments of the present disclosure and as shown in fig. 2. For ease of understanding, like elements of FIG. 3 are numbered in FIG. 2.
In contrast to fig. 2, the amplifier circuitry 300 of fig. 3 includes only a single stage of the first amplifier circuit 340. In other words, in various embodiments, various stages of amplifier circuits are within the scope of the present disclosure. In some embodiments, the first amplifier circuit 340 is substantially similar to the first amplifier circuit 140 in fig. 1 and the first amplifier circuit 240 and the second amplifier circuit 250 in fig. 2, and therefore, the description thereof is omitted here.
It should be noted that the numbers of the elements such as the load resistor, the variable resistor, and the like in fig. 1 to 3 are merely examples, and the disclosure is not limited thereto. Various amounts of load resistance and/or variable resistance are within the contemplation of this disclosure.
Refer to fig. 4. Fig. 4 is a flow chart of a signal compensation method 400 according to some embodiments of the present disclosure and shown in fig. 3. The signal compensation method 400 includes steps S410, S420, S430, S440 and S450. In some embodiments, the signal compensation method 400 may be applied in the amplifier circuitry of fig. 1-3. For a better understanding of the present disclosure, the signal compensation method 400 will be discussed in conjunction with the amplifier circuitry 300 of fig. 3, but the present disclosure is not limited thereto.
In step S410, a first bias current I with a first ratio MB1Through a second compensation resistor RC2To ground and a reference current IREFThrough a first compensation resistor RC1And a second compensation resistor RC2Flows to ground and at node n1To generate a reference voltage VREF. The first ratio M is less than 1. Second compensation resistor RC2And a first load resistor RL1There is a second ratio N.
In step S420, the regulator 165 in the voltage regulating circuit 360 receives the reference voltage VREFAnd at node n3To generate a supply voltage VDDRAnd will supply the voltage VDDROutput to the first amplifier circuit 340.
In step S430, the current source circuit 320 provides a first bias current IB1To the first amplifier circuit 340.
In step S440, the first bias current IB1Through a first variable resistor RV1And is substantially equally divided into two first load resistors RL1。
In step S450, the divided first bias current IB1Through a first load resistor RL1And at node n4To generate a first common-mode output signal VCM1。
In some embodiments, the first bias current IB1May be influenced by environmental parameters (e.g. temperature, especially when manufacturing temperature affects the integrated circuit) and thereby influence the first common mode output signal VCM1. In this disclosure, to eliminate environmental parametersInfluence of the number on the supply voltage VDDRAdding the same environmental parameter factor (e.g., the first bias current I)B1). In some embodiments, the first common-mode output signal V is shown in equation (6)CM1And a first bias current IB1Independent, and thus an ambient parameter independent first common mode output signal V is obtainedCM1. Therefore, the output of the amplifier circuitry may be more stable.
In other embodiments, as shown in formula (7), the signal compensation method 400 can also be used to make the first common-mode output signal VCM1Is related to an environmental parameter. First bias current I in equation (7)B1Coefficient of (MNR)L1-RV1-0.5RL1) Is positive, then the first common-mode output signal VCM1Positively correlated with the first bias current IB 1.
In an alternative embodiment, the first bias current I in equation (7)B1Coefficient of (MNR)L1-RV1-0.5RL1) Negative, the first common-mode output signal VCM1And a first bias current IB1Is a negative correlation.
The above description of the signal compensation method 400 includes exemplary operations, but the operations of the signal compensation method 400 need not be performed in the order shown. It is within the spirit and scope of the embodiments of the present disclosure that the order of the operations of the signal compensation method 400 be altered or that the operations be performed concurrently, partially concurrently, or omitted where appropriate.
As described above, the amplifier circuit system provided by the present disclosure is provided with the first ratio, the second ratio and the variable resistor, so that the common mode output signal is not affected by various variations (such as temperature) and can generate offset. Alternatively, the offset of the common mode output signal may have a positive or negative correlation in response to various variations (e.g., temperature).
Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention as defined by the appended claims.

Claims (20)

1. An amplifier circuitry, comprising:
a current source circuit for generating a first bias current;
a voltage regulating circuit for regulating a reference voltage to generate a supply voltage,
the voltage regulating circuit comprises a first compensating resistor and a second compensating resistor, wherein the first compensating resistor and the second compensating resistor are used for generating the reference voltage according to a reference current and a second bias current, and a first proportion is formed between the second bias current and the first bias current; and
a first amplifier including a plurality of first load resistors for generating a first common-mode output signal based on the supply voltage and the first bias current,
wherein a second ratio exists between the second compensation resistor and one of the plurality of first load resistors, and the first ratio and the second ratio are configured to compensate the first common mode output signal.
2. The amplifier circuitry of claim 1, wherein the first amplifier further comprises:
a variable resistor coupled to the plurality of first load resistors, the variable resistor configured to receive the supply voltage and cooperate with the plurality of first load resistors to adjust the first common mode output signal.
3. The amplifier circuitry of claim 2, wherein the first common-mode output signal satisfies the following equation:
VCM1＝IB1(MNRL1-RV1-0.5RL1)+IREF(RC1+NRL1)
wherein VCM1For the first common-mode output signal, IREFIs thatCurrent value of reference current, RC1Is the resistance value, R, of the first compensation resistorL1Is the resistance value, I, of one of the first load resistorsB1Is the current value of the first bias current, RV1M is the first ratio and N is the second ratio.
4. The amplifier circuitry of claim 2 or 3, wherein the first ratio, the second ratio and the resistance of the variable resistor are configured to cancel an offset of the first common-mode output signal.
5. The amplifier circuitry of claim 2 or 3, wherein the first ratio, the second ratio and the resistance of the variable resistor are configured to set the correlation between the first common-mode output signal and the first bias current.
6. The amplifier circuitry of claim 1, further comprising:
a second amplifier coupled to the first amplifier, the second amplifier comprising a plurality of second load resistors for generating a second common mode output signal based on the supply voltage and the first bias current.
7. The amplifier circuitry of claim 6, wherein the second amplifier further comprises:
and the variable resistor is coupled with the second load resistors and used for receiving the supply voltage so as to cooperate with the second load resistors to adjust the second common-mode output signal.
8. The amplifier circuitry of claim 1, wherein the voltage regulation circuit further comprises:
a regulator for generating the supply voltage according to the reference voltage,
the first compensation resistor is coupled to the second compensation resistor to generate the reference voltage according to the reference current and the second bias current.
9. The amplifier circuitry of claim 8, wherein a first terminal of the first compensation resistor is coupled to receive the reference current and output the reference voltage, a second terminal of the first compensation resistor is coupled to a first terminal of the second compensation resistor, the first terminal of the second compensation resistor is coupled to receive the second bias current, and a second terminal of the second compensation resistor is coupled to ground.
10. The amplifier circuitry of claim 1, wherein the first common-mode output signal satisfies the following equation:
VCM1＝IB1(MNRL1-0.5RL1)+IREF(RC1+NRL1)
wherein VCM1For the first common-mode output signal, IREFIs the current value of the reference current, RC1Is the resistance value, R, of the first compensation resistorL1Is the resistance value, I, of one of the first load resistorsB1The current value of the first bias current, M is the first ratio, and N is the second ratio.
11. The amplifier circuitry of claim 1 or 10, wherein the first ratio and the second ratio are configured to cancel an offset of the first common-mode output signal.
12. A voltage regulation circuit for compensating a common mode output signal generated by an amplifier circuit through two load resistors, the amplifier circuit biased by a supply voltage and a first bias current, the voltage regulation circuit comprising:
a first compensation resistor for receiving a reference current; and
a second compensation resistor coupled between the first compensation resistor and ground, wherein the second compensation resistor is used to cooperate with the first compensation resistor to generate a reference voltage according to a second bias current and the reference current,
wherein a first ratio exists between the second bias current and the first bias current, and a second ratio exists between the second compensation resistor and one of the two load resistors, and the first ratio and the second ratio are set to compensate the common mode output signal; and
a regulator for regulating the reference voltage to generate the supply voltage.
13. A method of signal compensation, comprising:
generating a first bias current through a current source circuit;
adjusting a reference voltage by a voltage adjusting circuit to generate a supply voltage, wherein the voltage adjusting circuit comprises a first compensation resistor and a second compensation resistor, the first compensation resistor and the second compensation resistor are used for generating the reference voltage according to a reference current and a second bias current, and a first proportion is formed between the second bias current and the first bias current; and
generating a first common-mode output signal by a first amplifier, wherein the first amplifier comprises a plurality of first load resistors for generating a first common-mode output signal based on the supply voltage and the first bias current,
wherein a second ratio exists between the second compensation resistor and one of the plurality of first load resistors, and the first ratio and the second ratio are configured to compensate the first common mode output signal.
14. The signal compensation method of claim 13, wherein generating the first common-mode output signal further comprises:
the first common mode output signal is adjusted by a variable resistor in cooperation with the first load resistors, wherein the variable resistor is coupled to the first load resistors and is used for receiving the supply voltage.
15. The method of claim 14, wherein the first ratio, the second ratio and the variable resistor are configured to cancel an offset of the first common-mode output signal or to set a correlation between the first common-mode output signal and the first bias current.
16. The signal compensation method of claim 13, further comprising:
a second common mode output signal is generated by a second amplifier, wherein the second amplifier comprises a plurality of second load resistors for generating the second common mode output signal based on the supply voltage and the first bias current.
17. The signal compensation method of claim 16, wherein generating the second common-mode output signal further comprises:
the second common mode output signal is adjusted by a variable resistor in cooperation with the second load resistors, wherein the variable resistor is coupled to the second load resistors and is used for receiving the supply voltage.
18. The signal compensation method of claim 13, wherein generating the supply voltage further comprises:
the supply voltage is generated by a regulator according to the reference voltage, wherein the first compensation resistor is coupled to the second compensation resistor to generate the reference voltage according to the reference current and the second bias current.
19. The signal compensation method of claim 18, wherein generating the reference voltage further comprises:
receiving the reference current and outputting the reference voltage through a first terminal of the first compensation resistor, wherein a second terminal of the first compensation resistor is coupled to a first terminal of the second compensation resistor; and
the second bias current is received through the first terminal of the second compensation resistor, wherein a second terminal of the second compensation resistor is coupled to ground.
20. The method of claim 13, wherein the first ratio and the second ratio are configured to cancel an offset of the first common-mode output signal or to set a correlation between the first common-mode output signal and the first bias current.
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