CN110489297B - FPGA debugging signal setting method based on graphical interface - Google Patents
FPGA debugging signal setting method based on graphical interface Download PDFInfo
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Abstract
The invention relates to the field of FPGA design, and particularly provides a method for setting an FPGA debugging signal based on a graphical interface. Compared with the prior art, the method has the advantages that the design files in the design project are divided into two parts by a user, the two parts are respectively placed in two folders, one folder stores the top-layer design files, the other folder stores all the remaining design files, and then the following steps are carried out: s1, compiling a design engineering instantiation hierarchical search script; s2, compiling a signal retrieval script; s3, writing a signal debugging labeling script; s4, using a graphical interface library to write graphical interface software, and completing debugging, labeling and modification on the designated signals in the design file according to the input information; after the software completes the whole design engineering signal debugging and labeling work, the signal debugging and labeling information is popped up to export a successful dialog box, and a debugging signal file is printed out at the same time. The invention has the advantages of greatly shortening the time for manually writing the signal debugging and labeling and has good popularization value.
Description
Technical Field
The invention relates to the field of FPGA design, and particularly provides a method for setting an FPGA debugging signal based on a graphical interface.
Background
At present, the electronic information technology industry develops rapidly, the performance requirement on a special chip is higher and higher, the complexity of an integrated circuit is exponentially increased while the integrated circuit technology is rapidly advanced, the research and development production period is greatly prolonged, and the method cannot well adapt to changeable market demands. A large-scale field programmable logic device (FPGA) provides a method for flexibly realizing a circuit, and balances the contradiction between product performances in a product research and development period.
As the FPGA design scale is larger and larger, the signal quantity is increased rapidly, and the debugging difficulty is larger and larger. FPGA companies mostly offer a test software based on online debugging for board level debugging, such as chiprope, etc. The use of the online debugging software requires that a user set debugging labels such as mark_debug, key wire and the like in the design in advance, so that the FPGA implementation tool is prevented from optimally removing signals to be debugged when codes are integrated, and specific signals cannot be found and added in the follow-up set up debug process. In the process of designing the FPGA engineering codes, due to the fact that front-end design codes are modified, functions of different design modules in debugging design engineering are realized, and the like, debugging signals for chiprope are required to be adjusted for many times, due to the fact that debugging labels are distributed in all sub-modules, users do not have an intuitive mode to conveniently find the labels, labels cannot be conveniently added or deleted according to needs, manual operation is complex, and mistakes are easy to occur.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the FPGA debugging signal setting method based on the graphical interface, which has strong practicability, is quick and convenient.
The technical scheme adopted for solving the technical problems is as follows:
the FPGA debugging signal setting method based on the graphic interface is characterized in that a user divides a design file in a design project into two parts, the two parts are respectively placed in two folders, one folder stores a top layer design file, the other folder stores all the remaining design files, and then the following steps are carried out:
s1, compiling a design engineering instantiation hierarchical search script;
s2, compiling a signal retrieval script;
s3, writing a signal debugging labeling script;
s4, using a graphical interface library to write graphical interface software, and completing debugging, labeling and modification on the designated signals in the design file according to the input information;
after the software completes the whole design engineering signal debugging and marking work, popping up a successful dialog box derived from signal debugging and marking information, and simultaneously printing and outputting a debugging signal file;
and finally, performing setting debugging, adding a debugging signal according to the debugging signal file, and storing.
Furthermore, the design project instantiation hierarchical search script is used for searching the design file of the whole project, the module of the top-level design file is named as a tree root through a search module and an instantiation format, each instantiation module of the design project and the subordinate relation between each instantiation module of the design project are found out from top to bottom through a recursion traversal method, instantiation hierarchical information of the design project is established, and the instantiation hierarchical information is stored as a tree node information file.
Further, the tree node is composed of four parts, namely a file name, a signal file name, a module name and an instantiation name.
Further, the signal retrieval script is configured to traverse the entire tree node information file according to a method that the tree node information file traverses from the tree root node in a preface, find the file from the design file and retrieve a signal keyword in the file according to a file name in the node information every time the tree node information file traverses, where the signal refers to an input/output port in the design file, retrieve whether a mark_debug or a key keyword exists at the head of a declaration line of the signal every time a signal is retrieved, determine whether the signal has been added as a debug signal label, and store the retrieved signal information output as a signal file, where the signal file is the order in which the design file is retrieved.
Further, the signal file includes a plurality of entries, each of which is composed of five parts, including a debug flag, a signal name, a signal input/output type, a signal bit width, and a signal type.
Preferably, the signal key input, output, inout, wire and/or reg.
Furthermore, the signal debugging labeling script is provided with three inputs, namely a design file name, a signal name and a signal addition and subtraction labeling mark;
when the script is called, the script finds the line where the signal name is located in the designated design file name according to the input information when the script is called, reads and stores the line text as a whole in a character string variable, replaces the line text where the signal name is located in the design file name with a space character, adds the debugging label or deletes the original debugging label in the character string variable according to the signal addition and subtraction label, and replaces the modified character string variable with the space character where the signal name is located in the design file name, thereby completing the debugging label modification of the signal name.
Further, using the software for writing the graphic interface library to read the generated tree node information file and the signal name file corresponding to each design file name, and displaying each instantiation module of the design project by using a tree directory, wherein each module is provided with an information frame and a sub-module unfolding button in front;
the information frame represents whether the module and an instantiation sub-module thereof have debugging marking signals or not, after the information frame is clicked to cancel selection, the debugging marking signals in the module and the instantiation sub-module thereof are cancelled, when the name of the module is clicked, a secondary interface is popped up, and the condition that the signals in the module are added with the debugging marking is displayed;
clicking the submodule unfolding button, and displaying the submodule instantiated under the module, wherein the information and the operation of each module are the same as those of the information frame;
after the signal debugging and labeling of each module are completed, clicking a toolbar saving button to save the current software operation state, clicking an export button, traversing each node by software from a top-level module, namely a tree root node in a preface traversing mode, calling a signal debugging and labeling script for each node module according to the saved debugging signal labeling operation information, and completing the signal debugging and labeling of each design file.
Further, the secondary interface is in a form of a table and consists of five columns and a plurality of rows, and each row displays detailed information of a signal;
the first column of the five columns is whether the signal is added with a debugging marking information frame, the signal debugging marking can be added or cancelled by clicking to select or cancel the frame, the second column is a signal name, the third column is the signal input/output port information, the fourth column is the signal type information, and the fifth column is the signal bit width information.
Compared with the prior art, the FPGA debugging signal setting method based on the graphical interface has the following outstanding beneficial effects:
aiming at the method for manually adding and deleting signal debugging labels in the existing FPGA design flow, the invention provides a platform and a method for completing highly-automatic signal debugging labels setting by using a scripting language and a graphical interface.
The method is convenient to implement, simple in flow, efficient and stable, can greatly shorten the time for manually writing the signal debugging and labeling, reduces the trouble of complicated manual operation and easy error, and further improves the development and development efficiency of the FPGA.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for setting a debug signal of an FPGA based on a graphical interface.
Detailed Description
In order to provide a better understanding of the aspects of the present invention, the present invention will be described in further detail with reference to specific embodiments. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A preferred embodiment is given below:
as shown in the flow chart in fig. 1, the design file in the user design project is divided into two parts, the two parts are respectively placed in two folders, and one folder stores the top design file and is named as top; the other folder holds all other files, named dsg.
Firstly, writing an instantiation hierarchical search script of a design project, wherein the script can search design files in the whole project, the script can search modules, instantiation formats and the like, the module name of a top-level design file in a top folder is used as a tree root, the subordinate relation between each instantiation module of the design project and each instantiation module is found out from top to bottom by a recursion traversal method, instantiation hierarchical information of the design project is established, and the instantiation hierarchical information is stored as a tree node information file. Each tree node file consists of four parts, namely a file name, a signal file name, a module name and an instantiation name.
And then writing a signal retrieval script, wherein the script traverses the whole tree node information file according to the tree node information file by a method of traversing the tree root node in an order, and each time one node is traversed, the signal retrieval script finds out a file from the design file according to the file name in the node information and retrieves the signal key word in the file, and the signal refers to an input/output port in the design file, wherein the retrieved signal key word is input, output, inout, wire, reg and the like. And each time a signal is searched, searching whether the signal is added with a key word such as mark_debug or key turn, judging whether the signal is marked by the added debug signal, and then outputting and storing the searched signal information as a signal file.
The signal storage file consists of five parts, namely a debugged label, a signal name, a signal input and output type, a signal bit width and a signal file name, wherein the signal file name is used as the order in which the design file is searched, the signal file name corresponding to the top-layer design file is 1, and the submodules are sequentially increased.
Then, when a signal debugging labeling script is written, three inputs are respectively designed file names, signal names and signal addition and subtraction labeling marks;
when the script is called, the script finds the line where the signal name is located in the designated design file name according to the input information when the script is called, reads and stores the line text as a whole in a character string variable, replaces the line text where the signal name is located in the design file name with a space character, adds the debugging label or deletes the original debugging label in the character string variable according to the signal addition and subtraction label, and replaces the modified character string variable with the space character where the signal name is located in the design file name, thereby completing the debugging label modification of the signal name. The signal debugging script is used as a sample and is written once and recorded in the circulation step,
and writing graphic interface software by using qt, wherein the software reads the tree node information file and the signal file corresponding to each design file generated in the steps, each instantiation module of the design file is displayed in a tree directory, an information frame and a sub-module unfolding button are arranged in front of each module, the information frame represents that debugging marking signals in the module and the sub-modules are cancelled, and when the name of the module is clicked, a secondary interface is popped up to display the condition of adding debugging marking to the signal in the module. Clicking a sub-module unfolding button, and displaying sub-modules instantiated under the sub-modules, wherein the information and the operation of each module are the same as those of the information frame. After the signal debugging and labeling of each module are completed, clicking a toolbar saving button to save the current software operation state, clicking an export button, traversing each node by software from a top-level module, namely a tree root node in a preface traversing mode, calling a signal debugging and labeling script for each node module according to the saved debugging signal labeling operation information, and completing the signal debugging and labeling of each design file.
The secondary interface is in a form of a table and consists of five columns and a plurality of rows, and each row displays detailed information of a signal; the first column of the five columns is whether the signal is added with a debugging marking information frame, the signal debugging marking can be added or cancelled by clicking to select or cancel the frame, the second column is a signal name, the third column is the signal input/output port information, the fourth column is the signal type information, and the fifth column is the signal bit width information.
Finally, after the software completes the whole design engineering signal debugging and labeling work, a successful dialog box is exported by popping up the signal debugging and labeling information, and meanwhile, a debugging signal list file is printed and output. And executing set up debug by using the comprehensive program, adding a debug signal according to the debug signal list file, and storing.
The above specific embodiments are merely illustrative of specific cases of the present invention, and the scope of the present invention includes, but is not limited to, the specific embodiments described above, any suitable changes or substitutions made by those skilled in the art, which are consistent with the method and system claims of FPGA-based USB interface interconnection of the present invention, shall fall within the scope of the present invention.
Claims (2)
1. The FPGA debugging signal setting method based on the graphic interface is characterized in that a user divides a design file in a design project into two parts, the two parts are respectively placed in two folders, one folder stores a top layer design file, the other folder stores all the remaining design files, and then the following steps are carried out:
s1, compiling a design engineering instantiation hierarchical search script;
the instantiation hierarchical search script searches design files in the whole project, the module name of the top design file in the top folder is used as a tree root through a search module and an instantiation format thereof, each instantiation module of the design project and the subordinate relation between the instantiation modules are found out from top to bottom through a recursion traversal method, instantiation hierarchical information of the design project is established, and the instantiation hierarchical information is stored as a tree node information file;
each tree node file consists of four parts, namely a file name, a signal file name, a module name and an instantiation name;
s2, compiling a signal retrieval script;
the signal retrieval script traverses the whole tree node information file according to the tree node information file by a method of traversing the tree root node in an order, and each time one node is traversed, the signal retrieval script finds out the file from the design file according to the file name in the node information and retrieves the signal key words in the file, wherein the signal refers to an input/output port in the design file;
wherein, the signal keywords searched are input, output, inout, wire and reg; each time a signal is retrieved, retrieving whether the signal is added with a key word mark_debug or key feature, judging whether the signal is marked by the added debug signal, and then outputting and storing the retrieved signal information as a signal file;
the signal file consists of five parts, namely whether debug marks, signal names, signal input and output types, signal bit widths and signal file names are set or not, the signal file names are used as the order in which design files are searched, the signal file name corresponding to the top-layer design file is 1, and the sub-modules are sequentially increased;
s3, writing a signal debugging labeling script;
the signal debugging labeling script has three inputs, namely a design file name, a signal name and a signal addition and subtraction labeling mark;
when a signal debugging labeling script is called, the script finds out a line where a signal name is located in a specified design file name according to input information when the signal debugging labeling script is called, the text in the line where the signal name is located in the design file name is read as a whole and stored in a character string variable, then the text in the line where the signal name is located in the design file name is replaced by a space character, then a debugging label is added in the character string variable or the original debugging label is deleted according to a signal addition and subtraction label, and the modified character string variable is replaced by the space character in the line where the signal name is located in the design file name, so that the debugging label modification of the signal name is completed;
the signal debugging script is used as a sample and is written once and recorded in the circulating step;
s4, using a graphical interface library to write graphical interface software, and completing debugging, labeling and modification on the designated signals in the design file according to the input information;
using qt to write graphic interface software, wherein the graphic interface software reads the tree node information files and the signal files corresponding to the design files generated in the steps, and displays each instantiation module of the design files in a tree catalog, and each instantiation module is preceded by an information frame and a sub-module unfolding button;
clicking a sub-module unfolding button, and displaying the sub-module instantiated under the instantiation module;
the information frame represents whether the instantiation module and an instantiation sub-module thereof have debugging marking signals, the information frame is clicked, after the information frame is deselected, the debugging marking signals in the instantiation module and the instantiation sub-module thereof are all cancelled, when the name of the instantiation module is clicked, a secondary interface is popped up, and the condition of adding the debugging marking to the signals in the instantiation module is displayed;
after the signal debugging and labeling of each instantiation module are completed, clicking a toolbar saving button to save the current software operation state, clicking an export button, traversing each node by software from a top-level module, namely a tree root node in a preface traversing mode, calling a signal debugging and labeling script for each node module according to the saved debugging signal labeling operation information, and completing the signal debugging and labeling of each design file;
after the software completes the whole design engineering signal debugging and marking work, popping up a successful dialog box derived from signal debugging and marking information, and simultaneously printing and outputting a debugging signal file;
and finally, performing setting debugging, adding a debugging signal according to the debugging signal file, and storing.
2. The method for setting the debugging signals of the FPGA based on the graphic interface according to claim 1, wherein the secondary interface is in a form of a table and consists of five columns and a plurality of rows, and each row displays detailed information of one signal;
the first column of the five columns is whether the signal is added with a debugging marking information frame, the signal debugging marking is added or cancelled by clicking to select or cancel the debugging marking information frame, the second column is a signal name, the third column is the signal input/output port information, the fourth column is the signal type information, and the fifth column is the signal bit width information.
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| GB0709105D0 (en) * | 2007-05-11 | 2007-06-20 | Univ Leicester | Debugging tool |
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| CN1967521A (en) * | 2005-11-17 | 2007-05-23 | 腾讯科技（深圳）有限公司 | Method for labeling computer resource and system therefor |
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