CN110324040A - A kind of method and device of clock frequency adjustment - Google Patents
A kind of method and device of clock frequency adjustment Download PDFInfo
- Publication number
- CN110324040A CN110324040A CN201910372800.9A CN201910372800A CN110324040A CN 110324040 A CN110324040 A CN 110324040A CN 201910372800 A CN201910372800 A CN 201910372800A CN 110324040 A CN110324040 A CN 110324040A
- Authority
- CN
- China
- Prior art keywords
- frequency
- clock
- coefficient
- frequency division
- division coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of method and devices of clock frequency adjustment.The method of above-mentioned clock frequency adjustment, comprising: S01, variable coefficient frequency divider receive stable high frequency clock signal；S02, frequency division coefficient control unit distribute corresponding frequency division coefficient to variable coefficient frequency divider according to current time slots number；S03, variable coefficient frequency divider are transmitted to corresponding hardware system after being divided high frequency clock signal according to frequency division coefficient.The present invention does not need to save context, and CPU and hardware system continue to remain operational.And due to the configuration for having no need to change system clock PLL, clock stable is exported in handoff procedure, and switch speed is fast；It only needs to reduce system complexity using a system clock source input and a system clock PLL；Adjustable arbitrary system performance output, is not limited by frequency division coefficient.
Description
Technical field
The present invention relates to clock frequencies to adjust field, in particular to CPU/SoC/ASIC system clock frequency adjusts field.
Background technique
For various CPU/SoC/ASIC systems, such as mobile phone and SSD hard disk, it is contemplated that it improves performance and reduces power consumption,
It needs to carry out dynamic adjustment to the frequency of system clock.Improve the frequency of system clock such as to improve instantaneous system performance.One
As method of adjustment be first CPU to be made to stop working, into dormant state, adjust system clock frequency, forced again after clock stable
Wake up CPU.CPU needs to save context and enters dormant state in this method, realizes complicated；And it needs to wait new system
Clock stable, time-consuming.
Summary of the invention
The present invention proposes a kind of method and device of clock frequency adjustment, which does not need to save context, CPU and hard
Part system remains operational.And due to the configuration for having no need to change system clock PLL, clock stable is exported in handoff procedure, is cut
Throw-over degree is fast.
A kind of method of clock frequency adjustment, comprising:
S01, variable coefficient frequency divider receive stable high frequency clock signal；
S02, frequency division coefficient control unit distribute corresponding frequency division coefficient to variable coefficient frequency divider according to current time slots number；
S03, variable coefficient frequency divider are transmitted to corresponding hard after being divided high frequency clock signal according to frequency division coefficient
Part system.
The frequency division coefficient control unit supports M time slot, and M is positive integer, the corresponding frequency division coefficient of each time slot；Often
The corresponding frequency division coefficient of a time slot is preset by CPU or is generated by dedicated hardware logic.
Each time slot in the frequency division coefficient control unit corresponds to different frequency division coefficients.
Each time slot in the frequency division coefficient control unit corresponds to identical frequency division coefficient.
A kind of device of clock frequency adjustment, comprising:
Phaselocked loop, for receiving external low-frequency clock signal and exporting stable high frequency clock signal；
Variable coefficient frequency divider, for receiving the high frequency clock signal, exported after being divided according to frequency division coefficient to
In corresponding hardware system；
Frequency division coefficient control unit is divided for distributing corresponding frequency division coefficient to variable coefficient according to current time slots number
Device；
The variable coefficient frequency divider be 1/2/4/6/ ... the frequency divider of/N coefficient, wherein N be even number.
The hardware system includes cpu system, SoC system or asic chip hardware logic system.
The present invention has the advantages that 1, propose a kind of method by system clock frequency modulation dynamically to adjust frequency, the party
Method does not need to save context, and CPU and hardware system continue to remain operational.And due to having no need to change system clock PLL's
It configures, clock stable output, switch speed are fast in handoff procedure.
2, this method only needs to reduce system complexity using a system clock source input and a system clock PLL.
3, the adjustable arbitrary system performance output of this method, is not limited by frequency division coefficient.
Detailed description of the invention
This patent is described further with embodiment with reference to the accompanying drawing.
Fig. 1 is system architecture schematic diagram of the invention.
Fig. 2 is the system architecture schematic diagram of the embodiment of the present invention.
Fig. 3 is the flow diagram of clock frequency of embodiment of the present invention method of adjustment.
Specific embodiment
As shown in Figure 1, Figure 3, the present invention in clock frequency adjustment device include phase-locked loop pll, variable coefficient frequency divider,
Frequency division coefficient control unit and CPU/SoC system and asic chip hardware logic system.
Phase-locked loop pll: locking external input clock generates stable system clock according to configuration information.
Variable coefficient frequency divider: support 1/2/4/6/ ... the frequency divider of/N coefficient, wherein N is even number, for PLL is defeated
Clock division is to suitable system clock out.1 frequency dividing indicates not divide, and directly exports the clock of phase-locked loop pll.Different coefficients it
Between can be switched with dynamic random, output clock keep stablize.
CPU/SoC system: including CPU, bus and peripheral hardware etc..
Asic chip hardware logic system: the dedicated hardware logic except CPU/SoC system.
Frequency division coefficient control unit: it supports M time slot, records the corresponding frequency division coefficient of each time slot.According to it is current when
Gap number is inquired corresponding frequency division coefficient and is configured in variable coefficient frequency divider.The frequency division coefficient of each time slot can be preparatory by CPU
Configuration or dynamic generate, and can also be generated by dedicated hardware logic.
In the present invention phaselocked loop receive outside low-frequency clock signal and export stable high frequency clock signal；Variable coefficient
Frequency divider receives the high frequency clock signal, and output is into corresponding hardware system after being divided according to frequency division coefficient；Frequency dividing
Degree control unit distributes corresponding frequency division coefficient to variable coefficient frequency divider according to current time slots number.
As illustrated in fig. 2, it is assumed that phase-locked loop pll exports 800MHz clock, variable coefficient frequency divider N is configured to 8, i.e. frequency divider
It supports 1/2/4/6/8 frequency dividing, indicates that frequency divider can export 800MHz/400MHz/200MHz/133MHz/100MHz frequency
Clock.For the accuracy for guaranteeing time slot units, clock number of the time slot units 1us under every kind of frequency dividing is needed to configure.With confidence
Breath is as shown in the table.
| Frequency division coefficient | Unit slot clock number |
| 1 | 800 |
| 2 | 400 |
| 4 | 200 |
| 6 | 133 |
| 8 | 100 |
Slot clock counter in frequency division coefficient control unit, when its counting reaches the corresponding unit of current frequency division coefficient
When slot clock number, indicate that current time slots terminate, slot clock counter resets restart the counting of next time slot.
Frequency division coefficient control unit supports 16 time slots.Time slot units are 1us.
Time slot is defined as follows, and timeslot number is recycled from 1 to 16.
For 16 time slots, the corresponding frequency division coefficient of each time slot is recorded, i.e. time slot frequency dividing table is as follows.
| Timeslot number | Frequency division coefficient |
| 1 | x |
| 2 | y |
| 3 | z |
| 4 | x |
| 5 | y |
| 6 | z |
| 7 | x |
| 8 | y |
| 9 | z |
| 10 | x |
| 11 | y |
| 12 | z |
| 13 | x |
| 14 | y |
| 15 | z |
| 16 | x |
Wherein: frequency division coefficient system performance as needed or clock determine.
Timeslot number in frequency division coefficient control unit, initial value is since 1, when counter counts count to current to time slot always
At the end of gap, timeslot number increases by 1, when timeslot number is more than 16, is automatically adjusted to timeslot number 1.Frequency division coefficient control unit according to
Current timeslot number selects corresponding clock division coefficient.
When the clock of system requirements is one of 800MHz/400MHz/200MHz/133MHz/100MHz, directly select
Select corresponding frequency dividing output.Such as system requirements 200MHz clock, it is as follows to configure time slot frequency dividing table.
| Timeslot number | Frequency division coefficient |
| 1 | 4 |
| 2 | 4 |
| 3 | 4 |
| 4 | 4 |
| 5 | 4 |
| 6 | 4 |
| 7 | 4 |
| 8 | 4 |
| 9 | 4 |
| 10 | 4 |
| 11 | 4 |
| 12 | 4 |
| 13 | 4 |
| 14 | 4 |
| 15 | 4 |
| 16 | 4 |
When the clock of system requirements is 333MHz, need to realize the corresponding system of 333MHz clock using clock combination
System performance.By can be calculated (400MHz x 11+200MHz x 4+133MHz x 1)/16=333MHz.It needs using 11
The 400MHz clock of a time slot, the 200MHz clock of 4 time slots, in addition the 133MHz clock of 1 time slot is realized to combine
The system performance of 333MHz clock.It is as follows to configure time slot frequency dividing table.
| Timeslot number | Frequency division coefficient |
| 1 | 2 |
| 2 | 2 |
| 3 | 2 |
| 4 | 4 |
| 5 | 2 |
| 6 | 2 |
| 7 | 2 |
| 8 | 4 |
| 9 | 2 |
| 10 | 2 |
| 11 | 2 |
| 12 | 4 |
| 13 | 2 |
| 14 | 2 |
| 15 | 4 |
| 16 | 6 |
System performance corresponding for certain clocks is come what is when combining generation, actually generated by multiple frequency-dividing clocks
It unites performance and desired value may there is a certain error, the error can be reduced or eliminated by increasing timeslot number.
Disclosed above is only specific embodiments of the present invention, but the present invention is not limited to this, the technology of this field
Various changes and modifications can be made to the invention by personnel without departing from the spirit and scope of the present invention.Obviously these changes and change
Type should belong to the present invention claims protection scope protection in.In addition, although being used some specific terms in this specification,
These terms are merely for convenience of description, does not constitute to the present invention any specifically limited.
Claims (7)
1. a kind of method of clock frequency adjustment, comprising:
S01, variable coefficient frequency divider receive stable high frequency clock signal；
S02, frequency division coefficient control unit distribute corresponding frequency division coefficient to variable coefficient frequency divider according to current time slots number；
S03, variable coefficient frequency divider are transmitted to corresponding hardware system after being divided high frequency clock signal according to frequency division coefficient
System.
2. the method for clock frequency adjustment according to claim 1, it is characterised in that: the frequency division coefficient control unit branch
M time slot is held, M is positive integer, the corresponding frequency division coefficient of each time slot.
3. the method for clock frequency adjustment according to claim 2, it is characterised in that: in the frequency division coefficient control unit
Each time slot correspond to different frequency division coefficients.
4. the method for clock frequency adjustment according to claim 2, it is characterised in that: in the frequency division coefficient control unit
Each time slot correspond to identical frequency division coefficient.
5. a kind of device of clock frequency adjustment, comprising:
Phaselocked loop, for receiving external low-frequency clock signal and exporting stable high frequency clock signal；
Variable coefficient frequency divider exports after being divided according to frequency division coefficient to corresponding for receiving the high frequency clock signal
Hardware system in；
Frequency division coefficient control unit, for distributing corresponding frequency division coefficient to variable coefficient frequency divider according to current time slots number.
6. the device of clock frequency adjustment according to claim 5, it is characterised in that: the variable coefficient frequency divider is 1/
The frequency divider of 2/4/6/ .../N coefficient, wherein N is even number.
7. the device of clock frequency adjustment according to claim 5, it is characterised in that: the hardware system includes CPU system
System, SoC system or asic chip hardware logic system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910372800.9A CN110324040A (en) | 2019-05-06 | 2019-05-06 | A kind of method and device of clock frequency adjustment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910372800.9A CN110324040A (en) | 2019-05-06 | 2019-05-06 | A kind of method and device of clock frequency adjustment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110324040A true CN110324040A (en) | 2019-10-11 |
Family
ID=68118933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910372800.9A Pending CN110324040A (en) | 2019-05-06 | 2019-05-06 | A kind of method and device of clock frequency adjustment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110324040A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033517A (en) * | 1989-05-31 | 1991-01-09 | Matsushita Electric Ind Co Ltd | Clock generator |
| US5052031A (en) * | 1990-08-14 | 1991-09-24 | At&T Bell Laboratories | Phase locked loop including non-integer multiple frequency reference signal |
| US6075834A (en) * | 1997-02-21 | 2000-06-13 | Matsushita Electric Industrial Co., Ltd. | Frequency divider |
| US20010036239A1 (en) * | 2000-03-03 | 2001-11-01 | Nec Corporation | Phase locked loop circuit and method of frequency modulation in phase locked loop circuit |
| JP2004236141A (en) * | 2003-01-31 | 2004-08-19 | Icom Inc | Phase locked loop circuit and noise component eliminating method |
| KR20050040289A (en) * | 2003-10-28 | 2005-05-03 | 매그나칩 반도체 유한회사 | Input clock generating device of universal asynchronous receiver transmitter |
| US20110234272A1 (en) * | 2010-03-25 | 2011-09-29 | Qicheng Yu | Method and apparatus for charge pump linearization in fractional-n plls |
| JP2013042358A (en) * | 2011-08-16 | 2013-02-28 | Kawasaki Microelectronics Inc | Frequency synthesizer |
| WO2014017472A1 (en) * | 2012-07-25 | 2014-01-30 | 日本電気株式会社 | Clock signal generation device for generating clock signal having non-integer-multiple dividing ratio |
| US20160225348A1 (en) * | 2015-02-03 | 2016-08-04 | Qualcomm Incorporated | Clock rate adjustment for processing unit |
| US20190074842A1 (en) * | 2016-03-15 | 2019-03-07 | Board Of Regents, The University Of Texas System | Fractional-n phase lock loop apparatus and method using multi-element fractional dividers |
-
2019
- 2019-05-06 CN CN201910372800.9A patent/CN110324040A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033517A (en) * | 1989-05-31 | 1991-01-09 | Matsushita Electric Ind Co Ltd | Clock generator |
| US5052031A (en) * | 1990-08-14 | 1991-09-24 | At&T Bell Laboratories | Phase locked loop including non-integer multiple frequency reference signal |
| US6075834A (en) * | 1997-02-21 | 2000-06-13 | Matsushita Electric Industrial Co., Ltd. | Frequency divider |
| US20010036239A1 (en) * | 2000-03-03 | 2001-11-01 | Nec Corporation | Phase locked loop circuit and method of frequency modulation in phase locked loop circuit |
| JP2004236141A (en) * | 2003-01-31 | 2004-08-19 | Icom Inc | Phase locked loop circuit and noise component eliminating method |
| KR20050040289A (en) * | 2003-10-28 | 2005-05-03 | 매그나칩 반도체 유한회사 | Input clock generating device of universal asynchronous receiver transmitter |
| US20110234272A1 (en) * | 2010-03-25 | 2011-09-29 | Qicheng Yu | Method and apparatus for charge pump linearization in fractional-n plls |
| JP2013042358A (en) * | 2011-08-16 | 2013-02-28 | Kawasaki Microelectronics Inc | Frequency synthesizer |
| WO2014017472A1 (en) * | 2012-07-25 | 2014-01-30 | 日本電気株式会社 | Clock signal generation device for generating clock signal having non-integer-multiple dividing ratio |
| US20160225348A1 (en) * | 2015-02-03 | 2016-08-04 | Qualcomm Incorporated | Clock rate adjustment for processing unit |
| US20190074842A1 (en) * | 2016-03-15 | 2019-03-07 | Board Of Regents, The University Of Texas System | Fractional-n phase lock loop apparatus and method using multi-element fractional dividers |
Non-Patent Citations (2)
| Title |
|---|
| 刘毓林: "《应用于锁相环的Flying-Adder电路研究》", 《知网》 * |
| 殷卫真: "《基于FPGA的电子***设计》", 28 February 2017 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105577178B (en) | A kind of broadband low phase noise Sigma-Delta phaselocked loop | |
| US7996704B2 (en) | Asynchronous first in first out interface and operation method thereof | |
| EP3573242A1 (en) | Frequency generator and frequency generation method | |
| TWI523432B (en) | Reference frequency calibration module and apparatus using the same | |
| CN103929173A (en) | Frequency divider and wireless communication device | |
| US10312923B2 (en) | Electronic circuit, phase-locked loop, transceiver circuit, radio station and method of frequency dividing | |
| KR100777460B1 (en) | Polar transmitter speed up modulation using multi-phase generator | |
| KR0178619B1 (en) | Apparatus and method for operating a phase locked loop frequency synthesizer responsive to radio frequency channel spacing | |
| CN108037332B (en) | Multi-channel reference clock generation module | |
| US8806260B2 (en) | Method and apparatus for generating a clock signal and for controlling a clock frequency using the same | |
| CN109521834A (en) | A kind of DP signal generation device and method | |
| JP3516590B2 (en) | Frequency divider with prescaler followed by a programmable counter, and corresponding prescaler and frequency synthesizer | |
| US20090245449A1 (en) | Semiconductor integrated circuit device and method for clock data recovery | |
| US10897242B2 (en) | Frequency demultiplication adjustment method of PLL | |
| CN100426899C (en) | Apparatus and method for regulating interface transmission rate of transmission device | |
| CN110324040A (en) | A kind of method and device of clock frequency adjustment | |
| CN102291119B (en) | Frequency divider and method | |
| CN107846222A (en) | A kind of digital analog converter gain self-calibration circuit | |
| US20160006421A1 (en) | Frequency synthesiser circuit | |
| TW201711396A (en) | Apparatus and method for clock data recovery and phase detector | |
| CN104242929B (en) | A kind of frequency modulated system with modulation depth compensation | |
| CN110504961B (en) | Multimode prescaler and frequency division method thereof | |
| US7756231B2 (en) | Digital clock generating circuit and method of operation | |
| CN212137687U (en) | Local vibration source based on phase-locked loop technology | |
| US11936385B2 (en) | Apparatus and methods for producing stable clock signals based on a varying frequency source clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |