CN109509836A - 形成存储器电容的方法 - Google Patents
形成存储器电容的方法 Download PDFInfo
- Publication number
- CN109509836A CN109509836A CN201710826528.8A CN201710826528A CN109509836A CN 109509836 A CN109509836 A CN 109509836A CN 201710826528 A CN201710826528 A CN 201710826528A CN 109509836 A CN109509836 A CN 109509836A
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- layer
- bottom electrode
- electrode layer
- patterning
- supporting layer
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/40—Capacitors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
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Abstract
本发明公开一种形成存储器电容的方法。首先提供一基底,基底中具有多个存储垫,然后在基底上形成一图案化支撑层。在图案化支撑层上形成一底电极层,底电极层共形地形成在图案化支撑层上以及其开口的表面上,并接触存储垫。接着在底电极层上形成一牺牲层。后续进行一软蚀刻工艺,以移除位于图案化支撑层的顶面上以及位于开口的部分侧壁上的底电极层,其中软蚀刻工艺包含使用一含氟化合物、一含氮与氢化合物以及一含氧化合物。接着完全移除牺牲层,并移除部分的图案化支撑层,在底电极层上形成一电容介电层,最后在电容介电层上形成一顶电极层。
Description
技术领域
本发明涉及一种形成存储器电容的方法,特别来说,是涉及了种具有软蚀刻工艺的形成存储器电容的方法。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)由许多存储单元(memory cell)组成。通常存储单元是由一存取晶体管及一存储电容(storage capacitor)所组成的半导体存储装置。通过存储电荷于存储电容上,每一存储单元可存储一位(bit)的信号。
存储电容通常由一上电极、一介电层、及一下电极所组成。存储电容所能存储的电容值和上下电极与介电层之间的面积大小成比例。然而随着各种电子产品朝小型化发展的趋势,每个存储单元的面积也必须进一步缩小,以使DRAM的设计得以符合高集中度、高密度的要求,但这却造成存储单元能存储的电荷量减小,导致了高读写频率(refreshfrequency)而影响效能。目前有二种方法可进一步增加存储电容的电荷存储量。一种方法是增加介电层所使用材质的介电系数(dielectric constant),如使利用高介电常数的介电层。另一种方法是增加上下电极与介电层之间的面积。
公知常识已有提出几种增加电容电极面积的方法,例如使用冠状电容(crown-type stacked capacitor),是通过其侧壁来增加电容电极的表面积。但此种电容的制作工艺复杂,在使用光刻工艺以形成冠状电容时,常受限于现有光刻工艺中光掩模图形的设计,而无法得到一深度以及预设形状的侧壁结构。这些问题已经地限制了存储器电容的存储电量以及存取的速度,而成了现在存储器产业必须解决的问题。
发明内容
本发明因此提供了一种制作存储器电容的方法,可以增加制作冠状电极的成功率。
根据本发明的其中一个实施方式,本发明是提供了一种形成存储器电容的方法。首先提供一基底,基底中具有多个存储垫,然后在基底上形成一图案化支撑层,图案化支撑层具有多个开口,每个开口对应每个存储垫。在图案化支撑层上形成一底电极层,底电极层共形地形成在图案化支撑层上以及开口的表面上,并接触存储垫。接着在底电极层上形成一牺牲层,牺牲层填入开口中。后续进行一软蚀刻工艺,以移除位于图案化支撑层的顶面上以及位于开口的部分侧壁上的底电极层,其中软蚀刻工艺包含使用一含氟化合物、一含氮与氢化合物以及一含氧化合物。接着完全移除牺牲层,并移除部分的图案化支撑层,在底电极层上形成一电容介电层,最后在电容介电层上形成一顶电极层。
根据本发明另一个实施例,本发明公开了一种形成存储器电容的方法。首先提供一基底,基底中具有多个存储垫,在基底上形成一图案化支撑层,图案化支撑层具有多个开口,每个开口对应每个存储垫。在图案化支撑层上形成一底电极层,底电极层共形地形成在图案化支撑层上以及开口的表面上,并接触存储垫。后续在底电极层上形成一牺牲层,牺牲层填入开口中。接着进行一软蚀刻工艺,以移除位于图案化支撑层的顶面上以及位于开口的部分侧壁上的底电极层,使得底电极的一顶面低于牺牲层的顶面,从而在图案化支撑层、牺牲层以及底电极层之间形成多个凹槽。然后完全移除所述牺牲层,并移除部分的图案化支撑层,在底电极层上形成一电容介电层,并在电容介电层上形成一顶电极层。
本发明所提供的形成存储器电容的方式,使用了软蚀刻工艺,以提升底电极层在形成时的正确性,可以形成可靠度更高的存储器电容。
附图说明
图1到图10为本发明一种形成存储器电容的方法的步骤示意图。
主要元件符号说明
300 基板 322 底电极层
302 介电层 323 开口
304 存储点接触 324 牺牲层
306 支撑结构 326 软蚀刻工艺
308 第一支撑层 328 凹槽
310 第一填入层 330 覆盖层
312 第二填入层 332 图案化层
314 第二支撑层 334 掩模层
316 第三填入层 334A SHB层
318 第三支撑层 334B OLD层
320 第一掩模层 336 开口
320’ 图案化第一掩模层 338 电容介电层
321 第二图案化掩模层 340 顶电极层
321A 开口
具体实施方式
为使本发明的一般技术人员可以进一步了解本发明,在以下的描述中会列出本发明的优选实施例,并配合附图,详细说明本发明的构成内容及希望实现的效果。
请参考图1至图10,其表示为本发明一种形成存储器电容的步骤示意图。如图1所示,首先提供一基板300,基板300可以包含具有半导体材质的基底,例如是硅基底(siliconsubstrate)、外延硅基底(epitaxial silicon substrate)、硅锗半导体基底(silicongermanium substrate)、碳化硅基底(silicon carbide substrate)或硅覆绝缘(silicon-on-insulator,SOI)基底。在一实施例中,半导体基底上可以具有电子元件例如存取晶体管(图未示),其可以是具有水平式栅极、凹入式栅极或垂直式栅极的存取晶体管。接着在基底300上形成一介电层302以及设置在介电层302中的多个存储点接触(Storage NodeContact)304,或称接合点(landing pad),其与存取晶体管的源极/漏极区(图未示)电连接。接着,在介电层302上依次地形成一支撑结构306、一第一掩模层320以及一第二图案化掩模层321。在一实施例中,支撑结构306由下而上包含一第一支撑层308、一第一填入层310、一第二填入层312、一第二支撑层314、一第三填入层316以及一第三支撑层318。第一填入层310以及第三填入层316的厚度大于第二填入层312的厚度;第三支撑层318的厚度大于第一支撑层308与第二支撑层314的厚度。在一实施例中,第一填入层310的材质是硼磷硅玻璃(boro-phospho-silicate-glass,BPSG),第二填入层310与第三填入层316包含氧化硅(SiO2);第一支撑层308、第二支撑层314与第三支撑层318包含氮化硅(SiN)。
支撑结构306最顶部(即第三支撑层318)、第一掩模层320、第二图案化掩模层321的材质彼此之间具有蚀刻选择比,在本实施例中,第一掩模层320包含非晶硅(amorphoussilicon),第二图案化掩模层321包含氧化硅。第二图案化掩模层321具有多个开口321A,其位置对应设置在存储点接触304上。
接着如图2所示,以第二图案化掩模层321为掩模,进行一蚀刻工艺以将其图案转移到第一掩模层320上,从而形成一图案化第一掩模层320’,然后去除第二图案化掩模层321。然后,再以第一图案化掩模层320’为掩模,图案化支撑结构306,以在支撑结构306中形成多个开口323,每个开口323对应并且暴露出存储点接触304,然后去除第二图案化掩模层321。
接着如图3所示,在基板300上形成一下电极层322,下电极层322优选会共形地(conformal)沿着第三支撑层318的顶面、开口323的侧壁以及底面上形成,但并不填满开口323。然后,在下电极层322上形成一牺牲层324,牺牲层324会完全填满开口323。在本发明其中一个实施例中,下电极层322例如是氮化钛(TiN),而牺牲层324例如是氧化硅,但并不以此为限。
接着如图4所示,通过一回蚀刻工艺,将牺牲层324蚀刻直到牺牲层324的顶面低于开口323的开口处,也就是低于第三支撑层318的顶面。在本发明优选的实施例中,牺牲层324的顶面会仍高于第三支撑层318的底面,也就是高于第三支撑层318与第三填入层316的交界。因此,位于第三支撑层318的顶面以及部分侧壁的底电极层322会被暴露出来。
如图5所示,接着进行一软蚀刻(soft etching)工艺326,以将暴露的底电极层322移除。值的注意的是,这里的软蚀刻工艺会将暴露的底电极层322移除直到其顶面低于牺牲层324的顶面,但优选仍会高于第三支撑层318的底面,也就是高于第三支撑层318与第三填入层316的交界。本发明由于在进行软蚀刻工艺时,是刻意将底电极层322蚀刻至低于牺牲层324,故最后蚀刻底电极层322时是在第三支撑层318、牺牲层324以及底电极层322之间形成的凹槽328中进行,由于凹槽328两侧均为垂直侧壁,因此底电极层322的顶面可以均匀底被蚀刻,而不会有蚀刻倾斜一边的情况,因此蚀刻后的底电极层322可以具有相对水平的顶面。因此,本发明的底电极层322在末端并不会呈现尖角而有尖端放电的情况,可以确保整个存储器的储电稳定度。
在本发明一个实施例中,软蚀刻工艺326是一干蚀刻工艺,包含使用一含氟化合物、一含氮与氢化合物以及一含氧化合物,蚀刻温度控制在摄氏200~300度,且优选不使用等离子。在一个实施例中,含氟化合物包含氟气(F2)、二氟化氙(XeF2)或三氟化氮(NF3),含氮含氢化合物包含氨气(NH3)、联氨(N2H4)或二亚氨(N2H2),含氧化合物包含氧气(O2)、臭氧(O3)或水(H2O)。而在本发明另外一个实施例中,软蚀刻326工艺是一湿蚀刻工艺,包含使用氢氧化铵/过氧化氢/去离子水(NH4OH/H2O2/H2O)的蚀刻剂,例如是标准清洗一号溶液(Standard clean,SC1),或是使用硫酸/过氧化氢/去离子水(H2SO4/H2O2/H2O),例如是标准清洗二号溶液(Standard clean,SC2)。在以往的技术中,若蚀刻气体具有氯,且以等离子蚀刻时,具有氮化钛(TiN)的底氧化层322容易产生四氯化钛(TiCl4)的残渣,非常难以去除。而本发明采用的软蚀刻工艺,由于采用了不含有氯的蚀刻方式,因此可避免底电极层322在蚀刻产生残渣。在使用含氟化合物、含氮与氢化合物以及含氧化合物的实施例中,是会产生Ti(OxNyHz)的错化物,而容易被清洗去除。另外一面,此种含氟化合物、含氮与氢化合物以及含氧化合物的蚀刻方式对于底电极层322(TiN)与第三支撑层318(SiN)有良好的蚀刻选择比,不易造成第三支撑层318的损失,故可以降低冠状电极倒塌的机率。此外,在进行软蚀刻工艺326时,牺牲层324是完全填满开口320,可以保护位于开口323底部的底电极层322不被蚀刻,也增加了底电极层322整体的可靠度。
在进行完软蚀刻工艺326后,如图6所示,在基板300上形成一覆盖层330,较佳会共形地沿着第三支撑层318的顶面与侧壁,且覆盖在牺牲层324以及底电极层322上。覆盖层330的材料例如是四乙氧基硅烷(tetraethoxysilane,TEOS)。
接着,如图7所示,在覆盖层330上形成一图案化层332以及一掩模层334。图案化层332具有开口336,其位于两个开口323之间,较佳开口336的侧壁分别垂直对齐在开口323的中央。在本发明的一实施例中,光致抗蚀剂层332以及掩模层334可以视工艺规格而有不同的选择,举例来说,图案化层332例如是适合193纳米(nm)波长的光致蚀刻材质,且图案化层332下方可以选择性的包含一底抗反射层(bottom anti-reflection coating,BARC);掩模层334可以是各种适合作为硬掩模的材质,其可以包含一层或多层的掩模材料,这些材料例如是氮化硅(silicon nitride,SiN)、氮氧化硅(silicon oxynitride,SiON)、碳化硅(silicon carbide,SiC)或是含碳的有机材料,例如是应用材料公司提供的进阶图案化薄膜(advanced pattern film,APF)。在优选实施例中,掩模层334例如由中国台湾信越化学公司(Shin-Etsu Chemical Co.Ltd.)提供的含硅的抗反射层(silicon-containing hard-mask bottom anti-reflection coating,SHB)334A与有机介电层(organic dielectriclayer,ODL)334B,其中SHB层334A直接位于图案层的光致抗蚀刻剂层332下,可作为一底抗反射层以及掩模层,而ODL层334B则是作为一最终的掩模层。
然后如图8所示,进行一蚀刻工艺,先将图案化层332的图案转移到掩模层334后,移除图案化层332;再将掩模层334的图案转移到下方的层中,也就会移除两个开口323之间的第三支撑层318,以及此两个开口323之间部分的覆盖层330、部分的牺牲层324与部分的底电极层322,然后移除图案化层332。
如图9所示,完全地移除覆盖层330、牺牲层324以及第一填入层310、第二填入层312以及第三填入层316,仅保留底电极层324以及第一支撑层308、第二支撑层314与第三支撑层318,其中底电极层324得以被第一支撑层308、第二支撑层314与第三支撑层318支持着。在本发明其中一个实施例中,上述步骤分段的实施的,例如先以一湿蚀刻工艺完全地移除覆盖层330、牺牲层324以及第二填入层310,后续再移除此两个开口323之间的第二支撑层314,最后再移除第一填入层310。
最后,如图10所示,在基板300上依次形成一电容介电层338以及一顶电极层340,其会覆盖在底电极层324上。电容介电层338例如是二氧化硅或是高介电材料,高介电材料包含金属氧化物,其可以是稀土金属氧化物层,例如是氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium siliconoxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、铝酸镧(lanthanum aluminum oxide,LaAlO)、氧化钽(tantalum oxide,Ta2O5)、氧化锆(zirconium oxide,ZrO2)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)或钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)等,但并不以此为限。顶电极层340例如是金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、钽(Ta)、镉(Cd)、或上述的氮化物、或上述的氧化物、或上述的合金、或上述的组合。通过上述步骤,即可形成存储器的电容结构,包含冠状电极的底电极层324、介电层338以及顶电极层340。
综上所述,本发明是公开了一种形成存储器电容的方式,其使用了软蚀刻工艺,以提升底电极层在形成时的正确性,可以形成可靠度更高的存储器电容。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (10)
1.一种形成存储器电容的方法,其特征在于包含:
提供一基底,所述基底中具有多个存储垫;
在所述基底上形成一图案化支撑层,所述图案化支撑层具有多个开口,每个所述开口对应每个所述存储垫;
在所述图案化支撑层上形成一底电极层,所述底电极层共形地形成在所述图案化支撑层上以及所述开口的侧壁与底面上,并接触所述存储垫;
在所述底电极层上形成一牺牲层,所述牺牲层填入所述开口中;
进行一软蚀刻工艺,以移除位于所述图案化支撑层上以及位于所述开口的部分侧壁上的所述底电极层,其中所述软蚀刻工艺包含使用一含氟化合物、一含氮与氢化合物以及一含氧化合物;
完全移除所述牺牲层;
移除部分的所述图案化支撑层;
在所述底电极层上形成一电容介电层;以及
在所述电容介电层上形成一顶电极层。
2.根据权利要求1所述的形成存储器电容的方法,其特征在于,所述含氟化合物包含氟气(F2)、二氟化氙(XeF2)或三氟化氮(NF3)。
3.根据权利要求1所述的形成存储器电容的方法,其特征在于,所述含氮含氢化合物包含氨气(NH3)、联氨(N2H4)或二亚氨(N2H2)。
4.根据权利要求1所述的形成存储器电容的方法,其特征在于,所述含氧化合物包含氧气(O2)、臭氧(O3)或水(H2O)。
5.根据权利要求1所述的形成存储器电容的方法,其特征在于,在进行所述软蚀刻工艺前,所述牺牲层的一顶面低于所述图案化支撑层的一顶面。
6.一种形成存储器电容的方法,包含:
提供一基底,所述基底中具有多个存储垫;
在所述基底上形成一图案化支撑层,所述图案化支撑层具有多个开口,每个所述开口对应每个所述存储垫;
在所述图案化支撑层上形成一底电极层,所述底电极层共形地形成在所述图案化支撑层上以及所述开口的底面与侧壁上,并接触所述存储垫;
在所述底电极层上形成一牺牲层,所述牺牲层填入所述开口中;
进行一软蚀刻工艺,以移除位于所述图案化支撑层上以及位于所述开口的部分侧壁上的所述底电极层,使得所述底电极层的一顶面低于所述牺牲层的一顶面,从而在所述图案化支撑层、所述牺牲层以及所述底电极层之间形成多个凹槽;
完全移除所述牺牲层;
移除部分的所述图案化支撑层;
在所述底电极层上形成一电容介电层;以及
在所述电容介电层上形成一顶电极层。
7.根据权利要求6所述的形成存储器电容的方法,其特征在于,在进行所述软蚀刻工艺前,所述牺牲层的所述顶面低于所述图案化支撑层的一顶面。
8.根据权利要求6所述的形成存储器电容的方法,其特征在于,所述图案化支撑层由下至上依次包含一第一支撑层、一第一填入层、一第二填入层、一第二支撑层、一第三填入层以及一第三支撑层,在进行完所示软蚀刻工艺后,所述底电极层的所述顶面高于所述第三支撑层与所述第三填入层的一边界。
9.根据权利要求6所述的形成存储器电容的方法,其特征在于,移除部分的所述图案化支撑层的步骤,是移除所述第一填入层、所述第二填入层以及所述第三填入层。
10.根据权利要求6所述的形成存储器电容的方法,其特征在于,所述底电极层的所述顶面实质上平行于一水平方向。
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