CN109302430B - Low-delay ARINC818 bus transceiving method - Google Patents

Abstract

The invention provides a low-delay ARINC818 bus transceiving method, in the process of realizing mutual conversion of a VESA protocol and an ARINC818 protocol according to an FPGA, due to optimization of a control algorithm, the data buffer amount at a transmitting end can be reduced from one current frame to 1 line, and the data buffer amount at a receiving end can be reduced from one current frame to 40 lines, so that the real-time performance of video transmission is improved to a great extent, and meanwhile, the required resources are cached by a new algorithm, the internal resources of the FPGA can be met, a plug-in memory is not required, the difficulty of hardware design is reduced, the resource overhead is reduced, and the power consumption is reduced.

Description

Low-delay ARINC818 bus transceiving method

Technical Field

The invention relates to the field of aviation buses, in particular to an ARINC818 transceiving method without external memory, with less cache and low time delay based on FPGA.

Background

In recent years, in the field of aeronautical buses, the amount of transmitted data is increasing, and the requirement on the delay performance of the data is also increasing. The transmission rate of the traditional digital aviation bus, such as ARINC429, cannot meet the requirement, on the basis of which the ARINC818 bus protocol formulated according to the FC-AV protocol becomes a new generation aviation video bus protocol and is well applied to various types of air passenger and boeing.

In the research of an ARINC818 bus in China, the relative start is late, the current design basically adopts an FPGA to realize the protocol conversion and transmission of video data, and the protocol conversion algorithm and the current flow adopted need to buffer the video data of one frame to two frames at the transmitting end and the receiving end. Meanwhile, due to the fact that the amount of videos from one frame to two frames is large, the requirement of cache cannot be met by using resources inside the FPGA, and a plug-in memory is needed to meet the design, so that the difficulty of system design is increased, the cost of hardware is increased, and the power consumption of the whole system is correspondingly increased.

Therefore, the ARINC818 receiving and sending method with low time delay is designed, the hardware design difficulty of the system can be effectively reduced while the video transmission real-time performance is improved, the hardware cost is reduced, and the method has great practical significance.

Disclosure of Invention

The invention provides a low-delay ARINC818 bus transceiving method according to an ARINC818 bus protocol, aiming at videos with the resolution of 1024 x 1280@60Hz, only 1 line of video data needs to be cached when the VESA protocol is converted into the ARINC818 protocol, and only 40 lines of data needs to be cached when the ARINC818 protocol is converted into the VESA protocol by designing a new protocol conversion control algorithm. The buffer amount of data in the protocol conversion process is reduced to a great extent, the real-time performance of data transmission is improved, meanwhile, the data buffer amount can be realized by utilizing the internal resources of the FPGA, external storage equipment is not needed, and the design difficulty and the resource overhead of a hardware circuit are reduced.

The technical scheme of the invention is as follows:

the low-latency ARINC818 bus transceiving method is characterized by comprising the following steps:

at the transmitting end, the VESA protocol is converted into ARINC818 protocol control flow through the following steps:

step 1: detecting a horizontal synchronizing signal HS, a field synchronizing signal VS and an effective data strobe signal DE of a frame of video, judging whether the HS, VS and DE signals are correct or not, if so, carrying out the next step, and if not, continuing the detection;

step 2: judging whether a field synchronization signal VS of a next frame of video is valid, if the field synchronization signal VS of the next frame of video is invalid, continuing to wait for judging the next frame of video, and if the field synchronization signal VS of the next frame of video is valid, sending a first packet of data according to an ARINC818 protocol;

and step 3: after the first packet is sent, waiting for a line of video data to be cached in the FIFO, and sending IDLE data IDLE in the waiting process until the second line of video data is detected to be valid, and entering the next step;

and 4, step 4: transmitting the nth packet data according to ARINC818 protocol, wherein the initial value of n is 2;

and 5: judging whether n is an odd number, if not, continuously sending 128 IDLE data IDLE, then taking n as n +1, returning to the step 4, if so, continuously judging whether n is 2049, if so, indicating that one frame of video data is completely transmitted, resetting the FIFO, returning to the step 2, if not, waiting, and sending the IDLE data IDLE all the time in the waiting process until judging that one line of video is finished according to the line end signal, taking n as n +1, and returning to the step 4;

at the receiving end, the ARINC818 protocol signal receiving flow is carried out through the following steps:

step 6: judging whether a frame header starting character is received, if not, continuing to wait, if so, judging whether frame header signal information is correct, if not, continuing to wait for the next frame, and if so, opening a data receiving channel, and entering step 7;

and 7: judging whether a data packet initial symbol is received, if not, continuing to wait, if so, judging whether the data packet state information is correct, if so, storing the received data into FIFO, and if not, reporting an error; after receiving a data packet, performing CRC check to determine whether the data packet is correct, and reporting an error if the data packet is incorrect; circularly receiving the data packets, when 2048 data packets or a packet end symbol is received, indicating that one frame of data is ended, returning to the step 6, and receiving a new frame again; meanwhile, whether the number of the data packets is correct or not is judged, and if the number of the data packets is incorrect, an error is reported;

and 8: counting the reported errors, resetting the FIFO if the reported errors reach the set number within the set time, returning to the step 6, and receiving a new frame again;

at the receiving end, the VESA timing is regenerated for the received ARINC818 data by:

and step 9: judging whether the data in the FIFO has 40 lines, if so, jumping to the next step, and if not, continuing to wait; meanwhile, a check module is in parallel, after one frame of ARINC818 data is received, the check module judges the number of data lines in the FIFO, if the number of the lines is less than 20 lines, the line front shoulder parameter of the VESA time sequence is modified, one data is added to the line front shoulder of each line, and if the number of the lines is more than 55 lines, the line front shoulder parameter of the VESA time sequence is modified, and one data is reduced to the line front shoulder of each line;

step 10: and generating a frame of VESA time sequence video, judging whether data exist in the FIFO after the frame of video is finished, returning to the step 9 if no data exist, and continuously generating the next frame of VESA time sequence video if data exist.

Advantageous effects

The invention has the beneficial effects that: in the process of realizing mutual conversion between the VESA protocol and the ARINC818 protocol according to the FPGA, due to optimization of a control algorithm, the data caching amount at a sending end can be reduced from one current frame to 1 line, the data caching amount at a receiving end can be reduced from one current frame to 40 lines, the real-time performance of video transmission is improved to a great extent, and meanwhile, the new algorithm caches required resources, so that the internal resources of the FPGA can be met, a plug-in memory is not needed any more, the difficulty of hardware design is reduced, the resource overhead is reduced, and the power consumption is reduced.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic diagram of a low-latency ARINC818 transmit-side circuit.

Fig. 2 is a flow chart of a control algorithm for converting the VESA protocol to the ARINC818 protocol at the transmitting end of the low-latency ARINC818 system.

Fig. 3 is a schematic diagram of a low-latency ARINC818 receiving circuit.

Fig. 4 is a flow chart of a signal receiving algorithm of the ARINC818 protocol at the receiving end of the low-delay ARINC818 system.

Fig. 5 is a flow chart of an algorithm for generating the VESA protocol signal at the receiving end of the low-latency ARINC818 system.

Detailed Description

The following detailed description of embodiments of the invention is intended to be illustrative, and not to be construed as limiting the invention.

The invention provides a low-delay ARINC818 bus transceiving method according to an ARINC818 bus protocol, aiming at videos with the resolution of 1024 x 1280@60Hz, only 1 line of video data needs to be cached when the VESA protocol is converted into the ARINC818 protocol, and only 40 lines of data needs to be cached when the ARINC818 protocol is converted into the VESA protocol by designing a new protocol conversion control algorithm. The buffer amount of data in the protocol conversion process is reduced to a great extent, the real-time performance of data transmission is improved, meanwhile, the data buffer amount can be realized by utilizing the internal resources of the FPGA, external storage equipment is not needed, and the design difficulty and the resource overhead of a hardware circuit are reduced.

As shown in fig. 2, on the transmitting side, the VESA protocol conversion to ARINC818 protocol control flow is performed through the following steps:

step 1: detecting a horizontal synchronizing signal HS, a field synchronizing signal VS and an effective data strobe signal DE of a frame of video, judging whether the HS, VS and DE signals are correct or not, if so, carrying out the next step, and if not, continuing the detection;

step 2: judging whether a field synchronization signal VS of a next frame of video is effective or not, if the VS of the next frame of video is ineffective, continuing to wait for judging the next frame of video, and if the VS of the next frame of video is effective, sending first packet data according to an ARINC818 protocol, wherein the total number of the first packet data is 35 words, and the first packet data comprises information such as packet transmission, signal resolution, refreshing mode and the like;

and step 3: after the first packet is sent, waiting for a line of video data to be cached in the FIFO, and sending IDLE data IDLE in the waiting process until the second line of video data is detected to be valid, and entering the next step;

the conversion transmission of the data packet is started after the second line of video data is detected to arrive, and one line of video data needs two data packets of ARINC818 protocol to be transmitted, so that 128 IDLE Data (IDLE) are transmitted after the first packet of one line of data is transmitted, the number of the transmitted IDLE is determined according to the line end signal after the second packet of one line of data is transmitted, once the line signal is ended, the transmission of the IDLE data is immediately ended, and the transmission of a new data packet is jumped to. The problem that the video data clock is matched with the ARINC818 data clock according to the control algorithm, so that the FIFO cannot be read empty or written full, and the correctness of data transmission is ensured;

and 4, step 4: transmitting the nth packet data according to ARINC818 protocol, wherein the initial value of n is 2;

and 5: judging whether n is an odd number, if not, continuously sending 128 IDLE data IDLE, then taking n as n +1, returning to the step 4, if so, continuously judging whether n is 2049, if so, indicating that one frame of video data is transmitted, resetting the FIFO, returning to the step 2, if not, waiting, and continuously sending the IDLE data IDLE in the waiting process until the line of video is judged to be finished according to the line end signal, taking n as n +1, and returning to the step 4.

As shown in fig. 4, at the receiving end, the ARINC818 protocol signal receiving process is performed by the following steps:

step 6: judging whether a frame header starting character is received, if not, continuing to wait, if so, judging whether frame header signal information is correct, if not, continuing to wait for the next frame, and if so, opening a data receiving channel, and entering step 7;

and 7: judging whether a data packet initial symbol is received, if not, continuing to wait, if so, judging whether the data packet state information is correct, if so, storing the received data into FIFO, and if not, reporting an error; after receiving a data packet, performing CRC check to determine whether the data packet is correct, and reporting an error if the data packet is incorrect; circularly receiving the data packets, when 2048 data packets or a packet end symbol is received, indicating that one frame of data is ended, returning to the step 6, and receiving a new frame again; meanwhile, whether the number of the data packets is correct or not is judged, and if the number of the data packets is incorrect, an error is reported;

and 8: and (4) counting the reported errors, resetting the FIFO if the reported errors reach 5 in 30s, returning to the step 6, and receiving a new frame again.

As shown in fig. 5, at the receiving end, the VESA timing is regenerated for the received ARINC818 data by the following steps:

and step 9: judging whether the data in the FIFO has 40 lines, if so, jumping to the next step, and if not, continuing to wait; meanwhile, a check module is in parallel, after one frame of ARINC818 data is received, the check module judges the number of data lines in the FIFO, if the number of the lines is less than 20 lines, the line front shoulder parameter of the VESA time sequence is modified, one data is added to the line front shoulder of each line, and if the number of the lines is more than 55 lines, the line front shoulder parameter of the VESA time sequence is modified, and one data is reduced to the line front shoulder of each line;

step 10: and generating a frame of VESA time sequence video, judging whether data exist in the FIFO after the frame of video is finished, returning to the step 9 if no data exist, and continuously generating the next frame of VESA time sequence video if data exist.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention.

Claims (1)

1. A low-latency ARINC818 bus transceiving method is characterized in that:

at the transmitting end, the VESA protocol is converted into ARINC818 protocol control flow through the following steps:

step 1: detecting a horizontal synchronizing signal HS, a field synchronizing signal VS and an effective data strobe signal DE of a frame of video, judging whether the HS, VS and DE signals are correct or not, if so, carrying out the next step, and if not, continuing the detection;

step 2: judging whether a field synchronization signal VS of a next frame of video is valid, if the field synchronization signal VS of the next frame of video is invalid, continuing to wait for judging the next frame of video, and if the field synchronization signal VS of the next frame of video is valid, sending a first packet of data according to an ARINC818 protocol;

and step 3: after the first packet is sent, waiting for a line of video data to be cached in the FIFO, and sending IDLE data IDLE in the waiting process until the second line of video data is detected to be valid, and entering the next step;

and 4, step 4: transmitting the nth packet data according to ARINC818 protocol, wherein the initial value of n is 2;

and 5: judging whether n is an odd number, if not, continuously sending 128 IDLE data IDLE, then taking n as n +1, returning to the step 4, if so, continuously judging whether n is 2049, if so, indicating that one frame of video data is completely transmitted, resetting the FIFO, returning to the step 2, if not, waiting, and sending the IDLE data IDLE all the time in the waiting process until judging that one line of video is finished according to the line end signal, taking n as n +1, and returning to the step 4;

at the receiving end, the ARINC818 protocol signal receiving flow is carried out through the following steps:

step 6: judging whether a frame header starting character is received, if not, continuing to wait, if so, judging whether frame header signal information is correct, if not, continuing to wait for the next frame, and if so, opening a data receiving channel, and entering step 7;

and 7: judging whether a data packet initial symbol is received, if not, continuing to wait, if so, judging whether the data packet state information is correct, if so, storing the received data into FIFO, and if not, reporting an error; after receiving a data packet, performing CRC check to determine whether the data packet is correct, and reporting an error if the data packet is incorrect; circularly receiving the data packets, when 2048 data packets or a packet end symbol is received, indicating that one frame of data is ended, returning to the step 6, and receiving a new frame again; meanwhile, whether the number of the data packets is correct or not is judged, and if the number of the data packets is incorrect, an error is reported;

and 8: counting the reported errors, resetting the FIFO if the reported errors reach the set number within the set time, returning to the step 6, and receiving a new frame again;

at the receiving end, the VESA timing is regenerated for the received ARINC818 data by:

and step 9: judging whether the data in the FIFO has 40 lines, if so, jumping to the next step, and if not, continuing to wait; meanwhile, a check module is in parallel, after one frame of ARINC818 data is received, the check module judges the number of data lines in the FIFO, if the number of the lines is less than 20 lines, the line front shoulder parameter of the VESA time sequence is modified, one data is added to the line front shoulder of each line, and if the number of the lines is more than 55 lines, the line front shoulder parameter of the VESA time sequence is modified, and one data is reduced to the line front shoulder of each line;

step 10: and generating a frame of VESA time sequence video, judging whether data exist in the FIFO after the frame of video is finished, returning to the step 9 if no data exist, and continuously generating the next frame of VESA time sequence video if data exist.

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