CN109302430A - A kind of low delay ARINC818 bus receiving/transmission method - Google Patents
A kind of low delay ARINC818 bus receiving/transmission method Download PDFInfo
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- CN109302430A CN109302430A CN201811499707.6A CN201811499707A CN109302430A CN 109302430 A CN109302430 A CN 109302430A CN 201811499707 A CN201811499707 A CN 201811499707A CN 109302430 A CN109302430 A CN 109302430A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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Abstract
The present invention proposes a kind of low delay ARINC818 bus receiving/transmission method, during realizing that VESA agreement and ARINC818 agreement are converted mutually according to FPGA, due to the optimization of control algolithm, in the buffer memory for sending end data 1 row can be reduced to from a current frame, in the buffer memory for receiving end data 40 rows can be reduced to from a current frame, largely improve the real-time of transmission of video, resource required for being cached with stylish algorithm, FPGA internal resource can meet, no longer need plug-in memory, reduce the difficulty of hardware design, reduce resource overhead, reduce power consumption.
Description
Technical field
The present invention relates to Avionics data bus field, in particular to it is a kind of based on FPGA realize without external memory, few caching, low delay
ARINC818 receiving/transmission method.
Background technique
In recent years, in Avionics data bus field, the data volume of transmission is more and more, requires the delay performance of data also more next
It is higher.Traditional digital Avionics data bus, if the transmission rate of ARINC429 is no longer satisfied demand, on this basis, according to
The ARINC818 bus protocol that FC-AV agreement is worked out has become the aerial video bus protocol of a new generation, and in Air Passenger
And good application is obtained on the different types of machines of Boeing.
The country is opposite to start late in the research of ARINC818 bus, and current design substantially uses FPGA to realize
The protocol conversion and transmission of video data, and currently used protocol conversion algorithm and process, require sending and receiving end
Cache the video data of a frame to two frames.The very big problem of the transmission delay of video is brought in this way, simultaneously because a frame is to two
The amount of video of frame is very big, is not able to satisfy the requirement of caching using the resource inside FPGA, need plug-in memory meet design,
The difficulty for increasing system design in this way, increases the expense of hardware, the power consumption of whole system can also increase accordingly.
Therefore the ARINC818 receiving/transmission method of low delay a kind of is designed, it, can be with while promoting transmission of video real-time
The hardware design difficulty of system is effectively reduced, hardware spending is reduced, there is very big Practical significance.
Summary of the invention
The present invention is to propose a kind of low delay ARINC818 bus receiving/transmission method according to ARINC818 bus protocol, is led to
It crosses and designs new protocol conversion control algolithm, the video for being 1024 × 1280@60Hz for resolution ratio is from VESA protocol conversion
ARINC818 agreement need to only cache 1 row video data, be that VESA agreement only needs to cache 40 line numbers from ARINC818 protocol conversion
According to.The buffer memory for largely reducing data in protocol conversion process improves the real-time of data transmission, needs simultaneously
Data buffer storage amount it is achieved that do not need External memory equipment, reduces the design of hardware circuit using FPGA internal resource
Difficulty and resource overhead.
The technical solution of the present invention is as follows:
A kind of low delay ARINC818 bus receiving/transmission method, it is characterised in that:
In transmitting terminal, carrying out VESA protocol conversion by following steps is ARINC818 protocol integrated test system process:
Step 1: line synchronising signal HS, field sync signal VS, the valid data gating signal DE of one frame video of detection, judgement
Whether HS, VS, DE signal are correct, carry out in next step, continuing to test if incorrect if correct；
Step 2: judging whether the field sync signal VS of next frame video is effective, continued waiting for if invalid under judgement again
One frame sends the first bag data according to ARINC818 agreement if effectively；
Step 3: after having sent the first packet, waiting and cache a line video data, a straight hair in waiting process in FIFO
Idle data IDLE is sent, until detecting that the second row video data is effective, into next step；
Step 4: sending the n-th bag data according to ARINC818 agreement, the initial value of n is 2；
Step 5: judging whether n is odd number, if not odd number, then continue to send 128 idle data IDLE, then take n
=n+1, and return step 4 then continue to judge whether n is equal to 2049 if odd number, if being equal to 2049, then it represents that a frame video
Data have transferred, and reset to FIFO, return step 2, if being not equal to 2049, wait, and one in waiting process
Straight hair send idle data IDLE, after judging a line video according to row end signal, takes n=n+1, and return step 4；
In receiving end, ARINC818 protocol signal is carried out by following steps and receives process:
Step 6: judge whether to receive frame head bebinning character, if do not received, continue waiting for, if received,
Judge whether frame head signal message is correct, if incorrect, continues waiting for next frame, if correctly, opening reception data channel,
Enter step 7；
Step 7: judge whether to receive data packet starting character, if do not received, continue waiting for, if received,
Whether correct judge data packet status information, if correctly, received data are stored in FIFO, if incorrect, on
Report an error mistake；A data packet is received, whether progress CRC check is correct, if incorrect, reports mistake；Circulation receives data
Packet accords with, then it represents that a frame data terminate, and return step 6 is re-started when having received 2048 data packets or receiving end-of-packet
The reception of a new frame；Judge whether data packet number is correct simultaneously, if incorrect, reports mistake；
Step 8: the mistake reported is counted, it is right if mistake is reported to reach setting number within the set time
FIFO is resetted, and return step 6, re-starts the reception of a new frame；
In receiving end, VESA timing is regenerated to the ARINC818 data received by following steps:
Step 9: judging whether data have 40 rows in FIFO, if there is jumping in next step, if not provided, continuing waiting for；
Parallel inspection module simultaneously checks that module judges number of data lines in FIFO after the completion of a frame ARINC818 data receiver,
If line number modifies the row crop parameter of VESA timing less than 20 rows, a data will be increased per crop line by line, if row
Number is greater than 55 rows, then modifies the row crop parameter of VESA timing, will reduce by a data per crop line by line；
Step 10: a frame VESA timing video is generated, after a frame video, judges whether there are data in FIFO, if
There is no data, then return step 9, if there is data, then continues to generate next frame VESA timing video.
Beneficial effect
The beneficial effects of the present invention are: realizing the process that VESA agreement and ARINC818 agreement are converted mutually according to FPGA
In, due to the optimization of control algolithm, it can be reduced to 1 row from a current frame in the buffer memory for sending end data, in receiving end
The buffer memory of data can be reduced to 40 rows from a current frame, largely improve the real-time of transmission of video, simultaneously
Resource required for new algorithm caches, FPGA internal resource can meet, it is no longer necessary to which plug-in memory reduces hardware
The difficulty of design, reduces resource overhead, reduces power consumption.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is low delay ARINC818 transmitting terminal circuit diagram.
Fig. 2 is that low delay ARINC818 system transmitting terminal VESA protocol conversion is ARINC818 protocol integrated test system algorithm flow
Figure.
Fig. 3 is low delay ARINC818 receiving terminal circuit schematic diagram.
Fig. 4 is low delay ARINC818 system receiving terminal ARINC818 protocol signal receiving algorithm flow chart.
Fig. 5 is that low delay ARINC818 system receiving terminal generates VESA protocol signal algorithm flow chart.
Specific embodiment
The embodiment of the present invention is described below in detail, the embodiment is exemplary, it is intended to it is used to explain the present invention, and
It is not considered as limiting the invention.
The present invention is to propose a kind of low delay ARINC818 bus receiving/transmission method according to ARINC818 bus protocol, is led to
It crosses and designs new protocol conversion control algolithm, the video for being 1024 × 1280@60Hz for resolution ratio is from VESA protocol conversion
ARINC818 agreement need to only cache 1 row video data, be that VESA agreement only needs to cache 40 line numbers from ARINC818 protocol conversion
According to.The buffer memory for largely reducing data in protocol conversion process improves the real-time of data transmission, needs simultaneously
Data buffer storage amount it is achieved that do not need External memory equipment, reduces the design of hardware circuit using FPGA internal resource
Difficulty and resource overhead.
As shown in Fig. 2, carrying out VESA protocol conversion by following steps is ARINC818 protocol integrated test system stream in transmitting terminal
Journey:
Step 1: line synchronising signal HS, field sync signal VS, the valid data gating signal DE of one frame video of detection, judgement
Whether HS, VS, DE signal are correct, carry out in next step, continuing to test if incorrect if correct；
Step 2: judging whether the field sync signal VS of next frame video is effective, continued waiting for if invalid under judgement again
One frame sends the first bag data according to ARINC818 agreement if effectively, and totally 35 words, contain transmission, signal resolution
The information such as rate, refreshing mode；
Step 3: after having sent the first packet, waiting and cache a line video data, a straight hair in waiting process in FIFO
Idle data IDLE is sent, until detecting that the second row video data is effective, into next step；
The conversion for starting to carry out data packet after detecting that the second row video data arrives is sent, due to a line video data
The data packet of two ARINC818 agreements is needed to send, so sending 128 skies after sending first packet of data line
Not busy data (IDLE), after sending second packet of data line, the quantity for sending IDLE is determined according to row end signal, once
Row signal terminates, and is immediately finished and sends IDLE data, jumps to and sends new data packet.View is matched according to such control algolithm
Frequency data clock and the unmatched problem of ARINC818 data clock, it is ensured that FIFO will not be read empty or be write full, it is ensured that
The correctness of data transmission；
Step 4: sending the n-th bag data according to ARINC818 agreement, the initial value of n is 2；
Step 5: judging whether n is odd number, if not odd number, then continue to send 128 idle data IDLE, then take n
=n+1, and return step 4 then continue to judge whether n is equal to 2049 if odd number, if being equal to 2049, then it represents that a frame video
Data have transferred, and reset to FIFO, return step 2, if being not equal to 2049, wait, and one in waiting process
Straight hair send idle data IDLE, after judging a line video according to row end signal, takes n=n+1, and return step 4.
As shown in figure 4, carrying out ARINC818 protocol signal in receiving end by following steps and receiving process:
Step 6: judge whether to receive frame head bebinning character, if do not received, continue waiting for, if received,
Judge whether frame head signal message is correct, if incorrect, continues waiting for next frame, if correctly, opening reception data channel,
Enter step 7；
Step 7: judge whether to receive data packet starting character, if do not received, continue waiting for, if received,
Whether correct judge data packet status information, if correctly, received data are stored in FIFO, if incorrect, on
Report an error mistake；A data packet is received, whether progress CRC check is correct, if incorrect, reports mistake；Circulation receives data
Packet accords with, then it represents that a frame data terminate, and return step 6 is re-started when having received 2048 data packets or receiving end-of-packet
The reception of a new frame；Judge whether data packet number is correct simultaneously, if incorrect, reports mistake；
Step 8: the mistake reported being counted, if mistake is reported to reach 5 in 30s, FIFO is answered
Position, and return step 6, re-start the reception of a new frame.
As shown in figure 5, in receiving end, when regenerating VESA to the ARINC818 data received by following steps
Sequence:
Step 9: judging whether data have 40 rows in FIFO, if there is jumping in next step, if not provided, continuing waiting for；
Parallel inspection module simultaneously checks that module judges number of data lines in FIFO after the completion of a frame ARINC818 data receiver,
If line number modifies the row crop parameter of VESA timing less than 20 rows, a data will be increased per crop line by line, if row
Number is greater than 55 rows, then modifies the row crop parameter of VESA timing, will reduce by a data per crop line by line；
Step 10: a frame VESA timing video is generated, after a frame video, judges whether there are data in FIFO, if
There is no data, then return step 9, if there is data, then continues to generate next frame VESA timing video.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art are not departing from the principle of the present invention and objective
In the case where can make changes, modifications, alterations, and variations to the above described embodiments within the scope of the invention.
Claims (1)
1. a kind of low delay ARINC818 bus receiving/transmission method, it is characterised in that:
In transmitting terminal, carrying out VESA protocol conversion by following steps is ARINC818 protocol integrated test system process:
Step 1: detection one frame video line synchronising signal HS, field sync signal VS, valid data gating signal DE, judge HS,
Whether VS, DE signal are correct, carry out in next step, continuing to test if incorrect if correct；
Step 2: judging whether the field sync signal VS of next frame video is effective, it is next again that judgement is continued waiting for if invalid
Frame sends the first bag data according to ARINC818 agreement if effectively；
Step 3: after having sent the first packet, waiting and cache a line video data in FIFO, sent always in waiting process empty
Not busy data IDLE, until detecting that the second row video data is effective, into next step；
Step 4: sending the n-th bag data according to ARINC818 agreement, the initial value of n is 2；
Step 5: judging whether n is odd number, if not odd number, then continue to send 128 idle data IDLE, then take n=n+
1, and return step 4 then continues to judge whether n is equal to 2049 if odd number, if being equal to 2049, then it represents that one-frame video data
It has been transferred that, FIFO has been resetted, return step 2 waits, and a straight hair in waiting process if being not equal to 2049
Idle data IDLE is sent, after judging a line video according to row end signal, takes n=n+1, and return step 4；
In receiving end, ARINC818 protocol signal is carried out by following steps and receives process:
Step 6: judging whether to receive frame head bebinning character, if do not received, continue waiting for, if received, judge
Whether header signal information is correct, if incorrect, continues waiting for next frame, if correctly, opening reception data channel, enters
Step 7；
Step 7: judging whether to receive data packet starting character, if do not received, continue waiting for, if received, judge
Whether data packet status information correct, if correctly, by received data be stored in FIFO in, if incorrect, on report an error
Accidentally；A data packet is received, whether progress CRC check is correct, if incorrect, reports mistake；Received data packet is recycled, when
It has received 2048 data packets or receives end-of-packet symbol, then it represents that a frame data terminate, and return step 6 re-starts new one
The reception of frame；Judge whether data packet number is correct simultaneously, if incorrect, reports mistake；
Step 8: the mistake reported being counted, if reporting mistake to reach setting number within the set time, to FIFO
It is resetted, and return step 6, re-starts the reception of a new frame；
In receiving end, VESA timing is regenerated to the ARINC818 data received by following steps:
Step 9: judging whether data have 40 rows in FIFO, if there is jumping in next step, if not provided, continuing waiting for；Simultaneously
Parallel inspection module checks that module judges number of data lines in FIFO after the completion of a frame ARINC818 data receiver, if
Line number then modifies the row crop parameter of VESA timing less than 20 rows, will increase a data per crop line by line, if line number is big
In 55 rows, then the row crop parameter of VESA timing is modified, will reduce by a data per crop line by line；
Step 10: generating a frame VESA timing video, after a frame video, judge whether there is data in FIFO, if do not had
Data, then return step 9 then continue to generate next frame VESA timing video if there is data.
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Cited By (2)
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| CN112564864A (en) * | 2020-12-31 | 2021-03-26 | 洛阳伟信电子科技有限公司 | ARINC818 bus link rate automatic adaptation method |
| CN114520919A (en) * | 2022-02-21 | 2022-05-20 | 朱鹏程 | High-speed video signal processing system and method |
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