CN108735741B - 存储器元件中的存储点接触结构与其制作方法 - Google Patents
存储器元件中的存储点接触结构与其制作方法 Download PDFInfo
- Publication number
- CN108735741B CN108735741B CN201710239078.2A CN201710239078A CN108735741B CN 108735741 B CN108735741 B CN 108735741B CN 201710239078 A CN201710239078 A CN 201710239078A CN 108735741 B CN108735741 B CN 108735741B
- Authority
- CN
- China
- Prior art keywords
- layer
- tungsten metal
- metal layer
- conductive layer
- contact structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003860 storage Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 33
- 239000010937 tungsten Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 156
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开一种存储器元件中的存储点接触结构与其制作方法。该存储器元件中的存储点接触(storage node contact)结构包含一基底,该基底上有一介电层,该介电层中包含有一凹槽,一第一钨金属层,位于该凹槽中,并且填满该凹槽,一粘着层,位于该第一钨金属层上,以及一第二钨金属层,位于该粘着层上,其中该第二钨金属层由一物理气相沉积(Physical vapor deposition,PVD)的方式形成。
Description
技术领域
本发明涉及一种半导体结构及其制作方法,尤其是涉及一种存储器元件中的存储点接触(storage node contact)结构及其制作方法。
背景技术
动态随机存取存储器(dynamic random access memory,以下简称为DRAM)是一种主要的挥发性(volatile)存储器,且是很多电子产品中不可或缺的关键元件。DRAM由数目庞大的存储单元(memory cell)聚集形成一阵列区,用来存储数据,而每一存储单元则由一金属氧化半导体(metal oxide semiconductor,以下简称为MOS)晶体管与一电容(capacitor)串联组成。
电容通过存储电极(storage node)与形成于电极接触洞(node contact)中的导电结构电连接,并与MOS晶体管的漏极形成一位存取的通路,用于达到存储或输出数据的目的。上述连接存储电极与电容之间的通路,也就是存储点接触(storage node contact),其制作品质将会影响到整个存储器元件的运作速度与表现。
综上所述,本发明将原先由一体成形结构所形成的存储点接触结构导电层(例如钨),分成上下两层,并且分别以不同的制作工艺形成。尤其是上层导电层用物理气相沉积的方式形成,具有表面平整与更佳的导电率的优点,进而可以增加整体存储元件的品质。
发明内容
本发明提供一种存储器元件中的存储点接触(storage node contact)结构,包含一基底,该基底上有一介电层,该介电层中包含有一凹槽,一第一钨金属层,位于该凹槽中,并且填满该凹槽,以及一第二钨金属层,位于该粘着层上,其中该第二钨金属层由一物理气相沉积(Physical vapor deposition,PVD)的方式形成。
本发明另提供一种存储器元件中的存储点接触(storage node contact)结构的形成方法,包含:提供一基底,该基底上形成有一介电层,该介电层中包含有一凹槽,接着形成一第一钨金属层于该凹槽中,并且填满该凹槽,然后进行一平坦化步骤,移除部分该第一钨金属层,并且形成一粘着层于该第一钨金属层上,以及通过一物理气相沉积(Physicalvapor deposition,PVD)的方式形成一第二钨金属层于该粘着层上。
本发明还提供一种存储器元件中的存储点接触(storage node contact)结构的形成方法,包含:提供一基底,该基底上形成有一介电层,该介电层中包含有一凹槽,接着形成一第一钨金属层于该凹槽中,并且填满该凹槽,然后进行一平坦化步骤,移除部分该第一钨金属层,并形成一粘着层于该第一钨金属层上,之后通过一物理气相沉积(Physicalvapor deposition,PVD)的方式形成一第二钨金属层于该粘着层上,以及对该第一钨金属层、该粘着层以及该第二钨金属层进行一退火步骤。
附图说明
图1至图7为本发明存储器元件中的接触点结构的流程示意图;
图8为本发明另一实施例中制作存储器元件中的接触点结构的示意图;
图9为本发明另一实施例中制作存储器元件中的接触点结构的示意图。
主要元件符号说明
10 基底
12 位线
12A 硅化钛层
12B 硅化钨层
12C 导电层
12D 掩模层
13 介电层
14 外延层
15 间隙壁
16 金属硅化物层
18 凹槽
20 衬垫层
22 晶种层
24 介电层
24’ 间隙壁
26 导电层
26’ 导电层
26a 表面
26b 表面
28 导电层
29 粘着层
30 氧化层
P1 平坦化步骤
P2 退火步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明,下文特列举本发明的优选实施例,并配合所附的附图,详细说明本发明的构成内容及所欲达成的功效。
为了方便说明,本发明的各附图仅为示意以更容易了解本发明,其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系,在本领域的人都应能理解其是指物件的相对位置而言,因此都可以翻转而呈现相同的构件,此都应同属本说明书所公开的范围,在此容先叙明。
请参考图1至图7,其绘示制作本发明存储器元件中的接触点结构的流程示意图。首先,如图1所示,提供一基底10,基底10中设置有多条主动区域(图未示)与环绕该些主动区域的浅沟隔离(图未示),基底10上或基底10中有多条字符线以及多条位线,其中字符线较佳为埋入式字符线(buried word line,图未示)位于基底10内部且穿过该些主动区域与浅沟隔离,而位线12则位于基底10上方并电连接任两字符线间的主动区域。各个位线12可能包含有多层结构,以本实施例来说,其可能包含有硅化钛层12A、硅化钨层12B、导电层(钨)12C以及掩模层(材质包含绝缘材料)12D等,一介电层13完整覆盖各个位线12。在两位线12之间具有一凹槽18,凹槽18作为后续形成存储点接触(storage node contact)的位置,其将会连接相对应的主动区域的源/漏极以及后续形成的电容结构。凹槽18的底部包含有外延层14(本实施例中,例如为硅磷SiP),外延层14与源/漏极相连接。在外延层14上更包含有金属硅化物层16(材料例如为CoSi)。此外在定义出凹槽18的位线12的内侧壁上可能包含有间隙壁15,其材质例如为氮化硅或氧化硅等单层或复合层的绝缘材料,但不限于此。
接下来,如图2所示,依序形成一衬垫层20、一晶种层22以及一介电层24于凹槽18内。其中衬垫层20例如为一钛/氮化钛的复合层,本实施例中,以物理气相沉积(PVD)的方式形成钛层,厚度大约为20埃,再以原子层沉积(ALD)的方式形成氮化钛层,厚度大约为30埃。接下来形成钨的晶种层22,以利后续导电层(钨)的生长,其厚度大约为20埃,以及以原子层沉积的方式形成介电层24,材质例如为氮化硅,厚度大约为30埃。上述提及各层的材料与厚度为本发明其中一实施例的参数,但本发明各元件的材料与厚度不限于上述所述,而可以依照实际需求而调整。此外,本发明亦可利用衬垫层20中复合层结构的钛层来直接反应成金属硅化物层16,而省略前述在形成衬垫层20之前额外制备金属硅化物层16的步骤。
如图3所示,进行一回蚀刻步骤,移除部分的介电层24,尤其是移除位于晶种层22顶面的介电层24,而仅剩余位于凹槽18侧壁上的介电层(剩余的介电层定义为间隙壁24’)。接下来如图4所示,形成一导电层26于凹槽18内并且填满凹槽18,此外导电层26也同时会覆盖于各位线12上方。本实施例中,导电层26材质为钨,但本发明中也可采用其他合适的导电材质取代钨,并调整适当的晶种层22材质。此处值得注意的是,由于凹槽18内部的侧壁被间隙壁24’所覆盖,连带位于侧壁的晶种层22也被覆盖住,仅有位于凹槽18底部的晶种层22被曝露,因此在形成导电层26的过程中,导电层26垂直生长的速度将会远大于横向生长的速度(因为位于垂直侧壁的晶种层22被覆盖),如此一来将可有效减少突悬(overhang)现象,以降低导电层26完成后,在凹槽内部留下空洞(void)的机率。
另外值得注意的是,在图4的步骤中,导电层26是用化学气相沉积(CVD)的方式形成,然而申请人发现完成后的导电层26具有一粗糙表面26a,此粗糙表面将不利于后续存储点接触结构的形成。因此接下来如图5所示,进行一平坦化步骤P1,移除部分的导电层26以及晶种层22,并且曝露出位于各位线12上方的衬垫层20。当平坦化步骤P1完成后,剩余的导电层定义为26’,其具有一较为平坦的表面26b。另外,导电层26’的表面26b与衬垫层20的顶面切齐,而衬垫层20仍完整覆盖各位线12与凹槽18。
如图6所示,接下来以一物理气相沉积(PVD)的方式形成另一导电层28,与导电层26’电连接并且直接接触。导电层28材质例如为钨,值得注意的是,相较于化学气相沉积,本步骤中采用物理气相沉积形成导电层28,在物理气相沉积的过程中,使用的气体更为单纯(例如仅有氩气),申请人也发现以物理气相沉积形成导电层28,可以降低整体存储点接触的电阻值。举例来说,如果完全以化学气相沉积的方式形成存储点接触,其电阻值大约为12至20欧姆厘米,而以本发明所述的方式,先以化学气相沉积形成导电层26’,然后再以物理气相沉积的方式形成导电层28覆盖于导电层26’上,整体存储点接触电阻值大约可降至9至11欧姆厘米。
后续步骤中,如图7所示,将导电层28图案化,移除部分的导电层28与衬垫层20,直至各位线12上的衬垫层20曝露出介电层13,此时由剖视图来看,剩余的衬垫层20呈现倒Ω形状,而导电层28呈现一字型的结构,并且剩余的导电层28形成存储点接触与电容结构之间的接触垫(landing pad),之后再形成电容结构等。其步骤属于本领域的已知技术,本发明在此不多加赘述。
下文将针对本发明的存储器元件及其制作方法的不同实施样态进行说明,且为简化说明,以下说明主要针对各实施例不同之处进行详述,而不再对相同之处作重复赘述。此外,本发明的各实施例中相同的元件是以相同的标号进行标示,以利于各实施例间互相对照。
在本发明的第二实施例中,如图8所示,完成图5所述的步骤后(本发明第二实施例的步骤与前述图1至图5相同,在此不重复赘述),在以物理气相沉积的方式形成导电层28之前,会先形成一粘着层29于导电层26’表面。此外粘着层29可能一并覆盖于衬垫层20表面,但本发明不限于此。形成粘着层29的目的是增加导电层26’与导电层28之间的粘着度,并且降低两者之间的介面电阻。粘着层29材质例如为钛或是钽。因此结构上,以PVD方式形成的导电层28与以CVD方式形成的导电层26之间具有粘着层29,另外部分的衬垫层20与导电层28也存在有粘着层29。
另外,在本发明的一实施例中,如图9所示,若有形成粘着层29,则需注意在粘着层29与平坦化后的导电层26’表面之间可能会产生氧化反应,举例来说,可能形成一氧化层30位于粘着层29与平坦化后的导电层26’之间,氧化层30材质可能为氧化钛或氧化钽(取决于粘着层29的材质为钛或钽)。为了降低氧化层30造成的不利影响,图9更在导电层28完成之后,额外进行了一退火步骤P2。此退火步骤P2可以消除位于粘着层29与平坦化后的导电层26’之间的氧化层30,或是减少氧化层30造成的影响,因此降低粘着层29与平坦化后的导电层26’之间的介面电阻,进而增加整体接触结构的导电率。上述步骤也属于本发明的涵盖范围内。
综上所述,本发明将原先由一体成形结构所形成的存储点接触结构导电层(例如钨),分成上下两层,并且分别以不同的制作工艺形成。尤其是上层导电层用物理气相沉积的方式形成,具有表面平整与更佳的导电率的优点,进而可以增加整体存储元件的品质。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (3)
1.一种存储器元件中的存储点接触(storage node contact)结构的形成方法,包含:
提供一基底,该基底上形成有介电层,该介电层中包含有凹槽;
形成一第一钨金属层于该凹槽中,并且填满该凹槽;
进行一平坦化步骤,移除部分该第一钨金属层;
形成一粘着层于该第一钨金属层上;
通过一物理气相沉积(Physical vapor deposition,PVD)的方式形成一第二钨金属层于该粘着层上;以及
对该第一钨金属层、该粘着层以及该第二钨金属层进行一退火步骤,
其中该第一钨金属层与该粘着层之间产生一氧化层,且该退火步骤移除该氧化层。
2.如权利要求1所述的形成方法,其中该氧化层材料包含有氧化钛或是氧化钽。
3.如权利要求1所述的形成方法,其中该第一钨金属层由一化学气相沉积的方式形成。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710239078.2A CN108735741B (zh) | 2017-04-13 | 2017-04-13 | 存储器元件中的存储点接触结构与其制作方法 |
US15/922,899 US10756090B2 (en) | 2017-04-13 | 2018-03-15 | Storage node contact structure of a memory device and manufacturing methods thereof |
US16/931,397 US11877433B2 (en) | 2017-04-13 | 2020-07-16 | Storage node contact structure of a memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710239078.2A CN108735741B (zh) | 2017-04-13 | 2017-04-13 | 存储器元件中的存储点接触结构与其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108735741A CN108735741A (zh) | 2018-11-02 |
CN108735741B true CN108735741B (zh) | 2020-10-09 |
Family
ID=63790269
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710239078.2A Active CN108735741B (zh) | 2017-04-13 | 2017-04-13 | 存储器元件中的存储点接触结构与其制作方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US10756090B2 (zh) |
CN (1) | CN108735741B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10867848B2 (en) * | 2018-04-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2660359B2 (ja) | 1991-01-30 | 1997-10-08 | 三菱電機株式会社 | 半導体装置 |
US5420072A (en) | 1994-02-04 | 1995-05-30 | Motorola, Inc. | Method for forming a conductive interconnect in an integrated circuit |
JP3500707B2 (ja) | 1994-06-28 | 2004-02-23 | ソニー株式会社 | 接続構造の形成方法、及び接続構造の設計方法 |
US5747379A (en) * | 1996-01-11 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back |
JPH09298238A (ja) * | 1996-05-08 | 1997-11-18 | Yamaha Corp | 配線形成方法 |
US5893734A (en) * | 1998-09-14 | 1999-04-13 | Vanguard International Semiconductor Corporation | Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts |
TW405258B (en) * | 1999-04-30 | 2000-09-11 | Taiwan Semiconductor Mfg | Manufacture method of DRAM capacitor |
KR20010065288A (ko) * | 1999-12-29 | 2001-07-11 | 박종섭 | 반도체 소자의 금속 배선 형성 방법 |
KR20010093456A (ko) * | 2000-03-29 | 2001-10-29 | 박종섭 | 반도체장치의 배선연결부 형성방법 |
US6177341B1 (en) | 2000-06-15 | 2001-01-23 | Vanguard International Semiconductor Corporation | Method for forming interconnections in semiconductor devices |
US6350649B1 (en) * | 2000-10-30 | 2002-02-26 | Samsung Electronics Co., Ltd. | Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof |
US20050145908A1 (en) * | 2003-12-30 | 2005-07-07 | Moise Theodore S.Iv | High polarization ferroelectric capacitors for integrated circuits |
US7256454B2 (en) * | 2005-07-25 | 2007-08-14 | Freescale Semiconductor, Inc | Electronic device including discontinuous storage elements and a process for forming the same |
KR100876976B1 (ko) * | 2007-01-31 | 2009-01-09 | 삼성전자주식회사 | 반도체 소자의 배선 및 이의 형성 방법 |
US20080254617A1 (en) * | 2007-04-10 | 2008-10-16 | Adetutu Olubunmi O | Void-free contact plug |
JP2009253033A (ja) * | 2008-04-07 | 2009-10-29 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
US8405135B2 (en) * | 2010-10-05 | 2013-03-26 | International Business Machines Corporation | 3D via capacitor with a floating conductive plate for improved reliability |
US8648465B2 (en) * | 2011-09-28 | 2014-02-11 | International Business Machines Corporation | Semiconductor interconnect structure having enhanced performance and reliability |
US8853021B2 (en) * | 2011-10-13 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded transistor |
US9123706B2 (en) * | 2011-12-21 | 2015-09-01 | Intel Corporation | Electroless filled conductive structures |
KR102044275B1 (ko) | 2013-07-31 | 2019-11-14 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
KR20150093384A (ko) * | 2014-02-07 | 2015-08-18 | 에스케이하이닉스 주식회사 | 저저항 텅스텐계 매립게이트구조물을 갖는 트랜지스터 및 그 제조 방법, 그를 구비한 전자장치 |
US9859213B2 (en) * | 2015-12-07 | 2018-01-02 | Dyi-chung Hu | Metal via structure |
US9859215B1 (en) * | 2016-08-17 | 2018-01-02 | International Business Machines Corporation | Formation of advanced interconnects |
CN115831969A (zh) * | 2017-11-30 | 2023-03-21 | 英特尔公司 | 用于高级集成电路结构制造的鳍状物图案化 |
-
2017
- 2017-04-13 CN CN201710239078.2A patent/CN108735741B/zh active Active
-
2018
- 2018-03-15 US US15/922,899 patent/US10756090B2/en active Active
-
2020
- 2020-07-16 US US16/931,397 patent/US11877433B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20200350317A1 (en) | 2020-11-05 |
CN108735741A (zh) | 2018-11-02 |
US11877433B2 (en) | 2024-01-16 |
US10756090B2 (en) | 2020-08-25 |
US20180301458A1 (en) | 2018-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111684596B (zh) | 具有电介质支撑柱的多层三维存储器装置及其制造方法 | |
US8691680B2 (en) | Method for fabricating memory device with buried digit lines and buried word lines | |
US9142563B2 (en) | Three dimensional semiconductor memory devices and methods of fabricating the same | |
US7381989B2 (en) | Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors | |
US8278207B2 (en) | Methods of manufacturing semiconductor devices | |
US11233057B2 (en) | Semiconductor structure and fabrication method thereof | |
CN102339829A (zh) | 半导体器件及其制造方法 | |
US10312242B2 (en) | Semiconductor memory device | |
CN108735741B (zh) | 存储器元件中的存储点接触结构与其制作方法 | |
US20180211961A1 (en) | Semiconductor memory device and manufacturing method thereof | |
CN110707045A (zh) | 一种制作半导体元件的方法 | |
CN115835624B (zh) | 存储器及其制造方法 | |
TWI652770B (zh) | 半導體記憶體結構及其製備方法 | |
CN113437070B (zh) | 半导体装置及其形成方法 | |
US7074689B2 (en) | Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell | |
CN108987347B (zh) | 半导体结构的制作方法 | |
CN109309123B (zh) | 半导体元件及其制作方法 | |
CN216958033U (zh) | 半导体存储装置 | |
CN113764419B (zh) | 半导体装置及其形成方法 | |
US20060079064A1 (en) | Fabrication method for a trench capacitor having an insulation collar which on one side is electrically connected to a substrate via a buried contact, in particular for a semiconductor memory cell, and corresponding trench capacitor | |
CN114188282B (zh) | 半导体器件及其制备方法 | |
US10103150B1 (en) | Semiconductor device having insulating layer higher than a top surface of the substrate, and method for reducing the difficulty of filling an insulating layer in a recess | |
CN117440678A (zh) | 半导体结构的制造方法 | |
CN117542834A (zh) | 存储器结构、半导体结构及其制备方法 | |
TW202310201A (zh) | 半導體結構及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |