CN108735741B - 存储器元件中的存储点接触结构与其制作方法 - Google Patents

存储器元件中的存储点接触结构与其制作方法 Download PDF

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CN108735741B
CN108735741B CN201710239078.2A CN201710239078A CN108735741B CN 108735741 B CN108735741 B CN 108735741B CN 201710239078 A CN201710239078 A CN 201710239078A CN 108735741 B CN108735741 B CN 108735741B
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layer
tungsten metal
metal layer
conductive layer
contact structure
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CN108735741A (zh
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陈品宏
郑存闵
蔡志杰
陈姿洁
张凯钧
吴佳臻
黄怡安
陈意维
黄信富
许启茂
冯立伟
王嫈乔
冯仲彦
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to US15/922,899 priority patent/US10756090B2/en
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Priority to US16/931,397 priority patent/US11877433B2/en
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Abstract

本发明公开一种存储器元件中的存储点接触结构与其制作方法。该存储器元件中的存储点接触(storage node contact)结构包含一基底，该基底上有一介电层，该介电层中包含有一凹槽，一第一钨金属层，位于该凹槽中，并且填满该凹槽，一粘着层，位于该第一钨金属层上，以及一第二钨金属层，位于该粘着层上，其中该第二钨金属层由一物理气相沉积(Physical vapor deposition，PVD)的方式形成。

Description

存储器元件中的存储点接触结构与其制作方法
技术领域
本发明涉及一种半导体结构及其制作方法，尤其是涉及一种存储器元件中的存储点接触(storage node contact)结构及其制作方法。
背景技术
动态随机存取存储器(dynamic random access memory，以下简称为DRAM)是一种主要的挥发性(volatile)存储器，且是很多电子产品中不可或缺的关键元件。DRAM由数目庞大的存储单元(memory cell)聚集形成一阵列区，用来存储数据，而每一存储单元则由一金属氧化半导体(metal oxide semiconductor，以下简称为MOS)晶体管与一电容(capacitor)串联组成。
电容通过存储电极(storage node)与形成于电极接触洞(node contact)中的导电结构电连接，并与MOS晶体管的漏极形成一位存取的通路，用于达到存储或输出数据的目的。上述连接存储电极与电容之间的通路，也就是存储点接触(storage node contact)，其制作品质将会影响到整个存储器元件的运作速度与表现。
综上所述，本发明将原先由一体成形结构所形成的存储点接触结构导电层(例如钨)，分成上下两层，并且分别以不同的制作工艺形成。尤其是上层导电层用物理气相沉积的方式形成，具有表面平整与更佳的导电率的优点，进而可以增加整体存储元件的品质。
发明内容
本发明提供一种存储器元件中的存储点接触(storage node contact)结构，包含一基底，该基底上有一介电层，该介电层中包含有一凹槽，一第一钨金属层，位于该凹槽中，并且填满该凹槽，以及一第二钨金属层，位于该粘着层上，其中该第二钨金属层由一物理气相沉积(Physical vapor deposition，PVD)的方式形成。
本发明另提供一种存储器元件中的存储点接触(storage node contact)结构的形成方法，包含：提供一基底，该基底上形成有一介电层，该介电层中包含有一凹槽，接着形成一第一钨金属层于该凹槽中，并且填满该凹槽，然后进行一平坦化步骤，移除部分该第一钨金属层，并且形成一粘着层于该第一钨金属层上，以及通过一物理气相沉积(Physicalvapor deposition，PVD)的方式形成一第二钨金属层于该粘着层上。
本发明还提供一种存储器元件中的存储点接触(storage node contact)结构的形成方法，包含：提供一基底，该基底上形成有一介电层，该介电层中包含有一凹槽，接着形成一第一钨金属层于该凹槽中，并且填满该凹槽，然后进行一平坦化步骤，移除部分该第一钨金属层，并形成一粘着层于该第一钨金属层上，之后通过一物理气相沉积(Physicalvapor deposition，PVD)的方式形成一第二钨金属层于该粘着层上，以及对该第一钨金属层、该粘着层以及该第二钨金属层进行一退火步骤。
附图说明
图1至图7为本发明存储器元件中的接触点结构的流程示意图；
图8为本发明另一实施例中制作存储器元件中的接触点结构的示意图；
图9为本发明另一实施例中制作存储器元件中的接触点结构的示意图。
主要元件符号说明
10 基底
12 位线
12A 硅化钛层
12B 硅化钨层
12C 导电层
12D 掩模层
13 介电层
14 外延层
15 间隙壁
16 金属硅化物层
18 凹槽
20 衬垫层
22 晶种层
24 介电层
24’ 间隙壁
26 导电层
26’ 导电层
26a 表面
26b 表面
28 导电层
29 粘着层
30 氧化层
P1 平坦化步骤
P2 退火步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所公开的范围，在此容先叙明。
请参考图1至图7，其绘示制作本发明存储器元件中的接触点结构的流程示意图。首先，如图1所示，提供一基底10，基底10中设置有多条主动区域(图未示)与环绕该些主动区域的浅沟隔离(图未示)，基底10上或基底10中有多条字符线以及多条位线，其中字符线较佳为埋入式字符线(buried word line，图未示)位于基底10内部且穿过该些主动区域与浅沟隔离，而位线12则位于基底10上方并电连接任两字符线间的主动区域。各个位线12可能包含有多层结构，以本实施例来说，其可能包含有硅化钛层12A、硅化钨层12B、导电层(钨)12C以及掩模层(材质包含绝缘材料)12D等，一介电层13完整覆盖各个位线12。在两位线12之间具有一凹槽18，凹槽18作为后续形成存储点接触(storage node contact)的位置，其将会连接相对应的主动区域的源/漏极以及后续形成的电容结构。凹槽18的底部包含有外延层14(本实施例中，例如为硅磷SiP)，外延层14与源/漏极相连接。在外延层14上更包含有金属硅化物层16(材料例如为CoSi)。此外在定义出凹槽18的位线12的内侧壁上可能包含有间隙壁15，其材质例如为氮化硅或氧化硅等单层或复合层的绝缘材料，但不限于此。
接下来，如图2所示，依序形成一衬垫层20、一晶种层22以及一介电层24于凹槽18内。其中衬垫层20例如为一钛/氮化钛的复合层，本实施例中，以物理气相沉积(PVD)的方式形成钛层，厚度大约为20埃，再以原子层沉积(ALD)的方式形成氮化钛层，厚度大约为30埃。接下来形成钨的晶种层22，以利后续导电层(钨)的生长，其厚度大约为20埃，以及以原子层沉积的方式形成介电层24，材质例如为氮化硅，厚度大约为30埃。上述提及各层的材料与厚度为本发明其中一实施例的参数，但本发明各元件的材料与厚度不限于上述所述，而可以依照实际需求而调整。此外，本发明亦可利用衬垫层20中复合层结构的钛层来直接反应成金属硅化物层16，而省略前述在形成衬垫层20之前额外制备金属硅化物层16的步骤。
如图3所示，进行一回蚀刻步骤，移除部分的介电层24，尤其是移除位于晶种层22顶面的介电层24，而仅剩余位于凹槽18侧壁上的介电层(剩余的介电层定义为间隙壁24’)。接下来如图4所示，形成一导电层26于凹槽18内并且填满凹槽18，此外导电层26也同时会覆盖于各位线12上方。本实施例中，导电层26材质为钨，但本发明中也可采用其他合适的导电材质取代钨，并调整适当的晶种层22材质。此处值得注意的是，由于凹槽18内部的侧壁被间隙壁24’所覆盖，连带位于侧壁的晶种层22也被覆盖住，仅有位于凹槽18底部的晶种层22被曝露，因此在形成导电层26的过程中，导电层26垂直生长的速度将会远大于横向生长的速度(因为位于垂直侧壁的晶种层22被覆盖)，如此一来将可有效减少突悬(overhang)现象，以降低导电层26完成后，在凹槽内部留下空洞(void)的机率。
另外值得注意的是，在图4的步骤中，导电层26是用化学气相沉积(CVD)的方式形成，然而申请人发现完成后的导电层26具有一粗糙表面26a，此粗糙表面将不利于后续存储点接触结构的形成。因此接下来如图5所示，进行一平坦化步骤P1，移除部分的导电层26以及晶种层22，并且曝露出位于各位线12上方的衬垫层20。当平坦化步骤P1完成后，剩余的导电层定义为26’，其具有一较为平坦的表面26b。另外，导电层26’的表面26b与衬垫层20的顶面切齐，而衬垫层20仍完整覆盖各位线12与凹槽18。
如图6所示，接下来以一物理气相沉积(PVD)的方式形成另一导电层28，与导电层26’电连接并且直接接触。导电层28材质例如为钨，值得注意的是，相较于化学气相沉积，本步骤中采用物理气相沉积形成导电层28，在物理气相沉积的过程中，使用的气体更为单纯(例如仅有氩气)，申请人也发现以物理气相沉积形成导电层28，可以降低整体存储点接触的电阻值。举例来说，如果完全以化学气相沉积的方式形成存储点接触，其电阻值大约为12至20欧姆厘米，而以本发明所述的方式，先以化学气相沉积形成导电层26’，然后再以物理气相沉积的方式形成导电层28覆盖于导电层26’上，整体存储点接触电阻值大约可降至9至11欧姆厘米。
后续步骤中，如图7所示，将导电层28图案化，移除部分的导电层28与衬垫层20，直至各位线12上的衬垫层20曝露出介电层13，此时由剖视图来看，剩余的衬垫层20呈现倒Ω形状，而导电层28呈现一字型的结构，并且剩余的导电层28形成存储点接触与电容结构之间的接触垫(landing pad)，之后再形成电容结构等。其步骤属于本领域的已知技术，本发明在此不多加赘述。
下文将针对本发明的存储器元件及其制作方法的不同实施样态进行说明，且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件是以相同的标号进行标示，以利于各实施例间互相对照。
在本发明的第二实施例中，如图8所示，完成图5所述的步骤后(本发明第二实施例的步骤与前述图1至图5相同，在此不重复赘述)，在以物理气相沉积的方式形成导电层28之前，会先形成一粘着层29于导电层26’表面。此外粘着层29可能一并覆盖于衬垫层20表面，但本发明不限于此。形成粘着层29的目的是增加导电层26’与导电层28之间的粘着度，并且降低两者之间的介面电阻。粘着层29材质例如为钛或是钽。因此结构上，以PVD方式形成的导电层28与以CVD方式形成的导电层26之间具有粘着层29，另外部分的衬垫层20与导电层28也存在有粘着层29。
另外，在本发明的一实施例中，如图9所示，若有形成粘着层29，则需注意在粘着层29与平坦化后的导电层26’表面之间可能会产生氧化反应，举例来说，可能形成一氧化层30位于粘着层29与平坦化后的导电层26’之间，氧化层30材质可能为氧化钛或氧化钽(取决于粘着层29的材质为钛或钽)。为了降低氧化层30造成的不利影响，图9更在导电层28完成之后，额外进行了一退火步骤P2。此退火步骤P2可以消除位于粘着层29与平坦化后的导电层26’之间的氧化层30，或是减少氧化层30造成的影响，因此降低粘着层29与平坦化后的导电层26’之间的介面电阻，进而增加整体接触结构的导电率。上述步骤也属于本发明的涵盖范围内。
综上所述，本发明将原先由一体成形结构所形成的存储点接触结构导电层(例如钨)，分成上下两层，并且分别以不同的制作工艺形成。尤其是上层导电层用物理气相沉积的方式形成，具有表面平整与更佳的导电率的优点，进而可以增加整体存储元件的品质。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (3)

1.一种存储器元件中的存储点接触(storage node contact)结构的形成方法，包含：
提供一基底，该基底上形成有介电层，该介电层中包含有凹槽；
形成一第一钨金属层于该凹槽中，并且填满该凹槽；
进行一平坦化步骤，移除部分该第一钨金属层；
形成一粘着层于该第一钨金属层上；
通过一物理气相沉积(Physical vapor deposition，PVD)的方式形成一第二钨金属层于该粘着层上；以及
对该第一钨金属层、该粘着层以及该第二钨金属层进行一退火步骤，
其中该第一钨金属层与该粘着层之间产生一氧化层，且该退火步骤移除该氧化层。
2.如权利要求1所述的形成方法，其中该氧化层材料包含有氧化钛或是氧化钽。
3.如权利要求1所述的形成方法，其中该第一钨金属层由一化学气相沉积的方式形成。
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