CN108494394B - Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method - Google Patents

Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method Download PDF

Info

Publication number
CN108494394B
CN108494394B CN201810660099.6A CN201810660099A CN108494394B CN 108494394 B CN108494394 B CN 108494394B CN 201810660099 A CN201810660099 A CN 201810660099A CN 108494394 B CN108494394 B CN 108494394B
Authority
CN
China
Prior art keywords
pmos
nmos
output
tubes
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810660099.6A
Other languages
Chinese (zh)
Other versions
CN108494394A (en
Inventor
杨秋平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuhai Amicro Semiconductor Co Ltd
Original Assignee
Zhuhai Amicro Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuhai Amicro Semiconductor Co Ltd filed Critical Zhuhai Amicro Semiconductor Co Ltd
Priority to CN201810660099.6A priority Critical patent/CN108494394B/en
Publication of CN108494394A publication Critical patent/CN108494394A/en
Application granted granted Critical
Publication of CN108494394B publication Critical patent/CN108494394B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses a low-noise and high-elastic noise resistant output driving circuit and a method. The PMOS driving module and the pre-driving module are connected to the PMOS input node, and the NMOS driving module and the pre-driving module are connected to the NMOS input node, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the output driving circuit when the PMOS input node or the NMOS input node inputs dynamic signals; and when the PMOS input node or the NMOS input node inputs static signals, enhancing the effect of resisting the high-ground bounce noise by improving the output driving resistance. Compared with the prior art, the invention reduces the ground bounce noise by dynamically adjusting the output driving resistance of the output driving circuit, and improves the effect of resisting the ground bounce noise by improving the output resistance during static driving.

Description

Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a low-noise and high-ground bounce noise resistant output driving circuit and a method for reducing ground bounce noise based on the same.
Background
The power supply on the circuit board and the package shell power supply have package inductance, the package shell power supply and the semiconductor integrated circuit internal power supply have on-chip parasitic inductance, the ground wire on the circuit board and the package shell ground wire have package inductance, and the package shell wire and the semiconductor integrated circuit internal ground wire have on-chip parasitic inductance. In general, the package inductance is far greater than the on-chip parasitic inductance, and the power line and the ground line of the integrated circuit have larger transient current variation, and the transient current generates larger alternating current voltage difference fluctuation through the package inductance, so that the internal power supply and the internal ground line voltage of the semiconductor integrated circuit are different from the power supply and the ground line voltage on the circuit board. This phenomenon is called the ground bounce effect, which introduces ground bounce noise in the power and ground lines.
IO drive circuits are widely used as a general-purpose circuit in ICs, with the increasing functionality of ICs today, and with the increasing number of IO pins, the number of IO drive circuits naturally increases, but since the pins of the entire IC are limited, the corresponding power pin numbers tend not to increase proportionally. Because a plurality of common IO driving circuits can generate obvious ground bounce noise when working simultaneously, when the ground bounce noise reaches a certain value, the receiving end circuit can receive an error signal level. Wherein the formula of the ground bounce noise isWhereinThe parasitic inductance value of the power pin or the ground pin of the IC is L, and N is the number of simultaneous operations of the IO driving circuits, so that the number of simultaneous operations of the IO driving circuits is difficult to reduce in order to ensure that the IC has a plurality of functions.
At present, most of design technologies focus on how to reduce the ground bounce noise generated when an IO driving circuit works, as shown in fig. 1, in the case that an enable output end OE is at a high level, when a signal of a data output end DO is converted to a low level, an NMOS tube NMO1, an NMOS tube NMO2 and an NMOS tube NMO3 are turned off, a PMOS tube PMO1 is firstly conducted, after a buffer delay, the PMOS tube PMO2 and the PMOS tube PMO3 are subsequently conducted, and as the ground bounce noise is in direct proportion to a current change rate, the PMOS tube PMO2 and the PMOS tube PMO3 are subsequently conducted, and then current is sequentially pulled up to an output node VOUT, and although the circuit delay has a certain loss, the change rate of a pull-up current is reduced; when the signal of the data output terminal DO is converted from low level to high level, the PMOS tube PMO1, the PMOS tube PMO2 and the PMOS tube PMO3 are turned off, the NMOS tube NMO1 is firstly conducted, after the buffer delay, the NMOS tube NMO2 and the NMOS tube NMO3 are subsequently conducted, and the change rate of the pull-down current is greatly reduced because the ground bounce noise team is in direct proportion to the current change rate, the NMOS tube NMO2 is firstly pulled down by a small current to the output node VOUT after being started, and then the NMOS tube NMO2 is started and is pulled down by a large current to the output node VOUT after being started. The circuit still has the great disadvantage that the IO driving circuit has the advantages that the PMOS tube PMO1, the PMOS tube PMO2 and the PMOS tube PMO3 are almost simultaneously conducted, or the NMOS tube NMO1, the NMOS tube NMO2 and the NMOS tube NMO3 are almost simultaneously conducted to cause a large current to charge a load capacitor through the PMOS tube or discharge the load capacitor through the NMOS tube in a short time, so that larger ground bounce noise is generated; and secondly, in a static working state of the circuit, the PMOS tube or the NMOS tube is always kept on, so that ground bounce noise is introduced, and larger static power consumption is generated.
In addition, some IO driving circuit design technologies that intentionally reduce the ground bounce noise in the prior art, such as US4880997, control the pre-driver driving capability to make the last stage of driving PMOS transistor and NMOS transistor slowly conduct, still can not effectively eliminate the error phenomenon of output signal level caused by the ground bounce signal generated by the simultaneous operation of a plurality of IO driving circuits.
Disclosure of Invention
In order to improve the ground bounce noise interference resistance of an IO output driving circuit as much as possible, the invention provides an IO output driving circuit with low output noise and high power ground bounce resistance, which has the following technical scheme:
The output driving circuit with low noise and high ground bounce noise resistance comprises a pre-driving module taking a data output end and an enabling output end as inputs, a PMOS input node, a PMOS common node connected with the PMOS input node, an NMOS common node connected with the NMOS input node, an output node, a grounding end and a power supply voltage end; the output driving circuit further comprises a PMOS driving module and an NMOS driving module;
the PMOS driving module and the pre-driving module are connected to the PMOS input node, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the PMOS driving module when the PMOS input node inputs dynamic signals, and the effect of resisting the ground bounce noise is enhanced by improving the output driving resistance when the PMOS input node inputs static signals;
The NMOS driving module and the pre-driving module are connected to the NMOS input node, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the NMOS driving module when the NMOS input node inputs a dynamic signal, and the effect of resisting the ground bounce noise is enhanced by improving the output driving resistance when the NMOS input node inputs a static signal;
wherein the PMOS driving module and the NMOS driving module are connected to the output node; the dynamic signal is a signal with level inversion, and the static signal is a signal without level inversion.
Further, the PMOS driving module comprises a preset number of falling edge time-delay control submodules and PMOS tubes divided into preset groups; the grid electrodes of the first group of PMOS tubes are connected with the output end of the first phase inverter to the PMOS input node, the other groups of PMOS tubes are correspondingly connected with the output end of one falling edge time-delay control submodule through the grid electrodes of the first group of PMOS tubes, and the input ends of the preset number of falling edge time-delay control submodules are connected to the PMOS public node, so that when a dynamic signal is input to the PMOS public node, the falling edge time-delay control submodule adjusts the output driving resistance of the PMOS driving module to reduce the change rate of current by controlling the conduction time of each group of PMOS tubes, and the ground bounce noise is reduced; when the PMOS public node inputs a static signal, the falling edge delay control submodule increases the output driving resistance of the PMOS driving module by turning off all groups of PMOS tubes so as to enhance the effect of resisting high-ground-bounce noise;
The NMOS driving module comprises a preset number of rising edge time-delay control submodules and NMOS tubes divided into preset groups; the grid electrodes of the first group of NMOS tubes are connected with the output end of the second inverter to the NMOS input node, the other groups of NMOS tubes are correspondingly connected with the output end of a rising edge time-delay control submodule through the grid electrodes of the first group of NMOS tubes, and the input ends of the preset number of rising edge time-delay control submodules are connected to the NMOS common node, so that when a dynamic signal is input to the NMOS common node, the falling edge time-delay control submodule adjusts the output driving resistance of the NMOS driving module to reduce the change rate of current by controlling the conduction time of each group of NMOS tubes, and ground bounce noise is reduced; when the NMOS common node inputs a static signal, the falling edge delay control submodule increases the output driving resistance of the NMOS driving module by turning off all groups of NMOS tubes so as to enhance the effect of resisting high-ground-bounce noise;
Wherein the preset number is equal to the preset group number minus one; each of the other groups of PMOS tubes corresponds to one falling edge time delay control submodule; and each of the other NMOS tubes corresponds to one rising edge time delay control submodule.
Further, the PMOS driving module comprises PMOS tubes divided into preset groups, and the number of the PMOS tubes in the first group is smaller than that of the PMOS tubes in the other groups, so that the ground bounce noise of the data output end in a high level stage is reduced;
the number of the first group of NMOS tubes is smaller than that of the rest groups of NMOS tubes, so that the ground bounce noise of the data output end in a low level stage is reduced.
Further, sources of the PMOS tubes divided into preset groups in the PMOS driving module are connected to the power supply voltage end, and drains of the PMOS tubes are connected to the output node;
And the drains of the NMOS transistors divided into preset groups in the NMOS driving module are connected to the output node, and the sources of the NMOS transistors are connected to the grounding terminal.
Further, the value of the preset group number is set to 3 or more.
Further, the falling edge delay control submodule comprises a first input logic unit, a low-level delay unit, a fourth inverter and a second or gate, wherein the input end of the first input logic unit is connected with the PMOS input node, the output end of the first input logic unit is connected with the input end of the low-level delay unit, the output end of the low-level delay unit is connected with the input end of the fourth inverter, a common node, with the output end of the first input logic unit connected with the input end of the low-level delay unit, and the output end of the fourth inverter are connected to two input ends of the second or gate, and the output end of the second or gate is connected with the grid electrode of a corresponding group of PMOS pipes in the other groups of PMOS pipes;
the first input logic unit is a buffer or a delay unit, and the low-level delay unit determines the output low-level pulse width.
Further, the rising edge delay control submodule comprises a second input logic unit, a high-level delay unit, a fifth inverter and a second AND gate, wherein the input end of the second input logic unit is connected with the NMOS input node, the output end of the second input logic unit is connected with the input end of the high-level delay unit, the output end of the high-level delay unit is connected with the input end of the fifth inverter, a common node, with the output end of the second input logic unit connected with the input end of the high-level delay unit, and the output end of the fifth inverter are connected to two input ends of the second AND gate, and the output end of the second AND gate is connected with the grid electrode of a corresponding NMOS tube in the other groups of NMOS tubes;
The second input logic unit is a buffer or a delay unit, and the high-level delay unit determines the output high-level pulse width.
Further, the falling edge delay control submodule controls the conduction time length and the conduction starting time of the other groups of PMOS tubes; and the rising edge delay control submodule controls the conduction time length and the conduction starting time of the rest NMOS tubes.
A method of reducing ground bounce noise based on the output driver circuit, the method comprising:
When the data output end DO inputs a rising edge signal into the pre-driving module, the PMOS input node receives a falling edge signal, and the data output end DO turns on a first group of PMOS tubes in the PMOS driving module and triggers the falling edge delay control submodule to output a low-level pulse signal, and turns on the PMOS tubes corresponding to the other groups, so that the conduction time length and the conduction starting time of the PMOS tubes of the other groups are controlled, and the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the PMOS driving module;
When the data output end DO keeps a high-level state, the PMOS input node keeps a low-level signal, a first group of PMOS tubes in the PMOS driving module are continuously conducted, the falling edge delay control submodule outputs a high level, and other groups of PMOS tubes are turned off, so that the output driving resistance of the output driving circuit is increased, and the effect of resisting high-altitude elastic noise is enhanced;
when the data output end DO inputs a falling edge signal into the pre-driving module, the NMOS input node receives the rising edge signal, and the rising edge delay control submodule is triggered to output a high-level pulse signal to turn on the corresponding NMOS tubes of the other groups, so that the conduction time length and the conduction starting time of the NMOS tubes of the other groups are controlled, and the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the NMOS driving module;
When the data output terminal DO keeps a low level state, the PMOS input node keeps a high level signal, a first group of NMOS tubes in the NMOS drive module are continuously conducted, the rising edge delay control submodule outputs a low level, and other groups of NMOS tubes are turned off, so that the output drive resistance of the output drive circuit is increased, and the effect of resisting high-altitude elastic noise is enhanced.
Compared with the prior art, the invention has the advantages that in order to reduce the generated ground bounce noise as much as possible, the output driving capability is changed by dynamically adjusting the conduction time of the driving PMOS tube and the driving NMOS tube, and the current change rate is reduced, so that the ground bounce noise generated by the IO output driving circuit is reduced, the output driving resistance when static signals are input is increased, the high ground bounce noise resistance of the output driving resistance is improved, and the accuracy of the output driving circuit for outputting signals under various application conditions is ensured.
Drawings
FIG. 1 is a schematic diagram of a conventional single IO driver circuit;
FIG. 2 is a schematic diagram of an output driving circuit with low noise and high-elastic noise resistance according to the embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a control sub-module for controlling falling edge delay according to the embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a control sub-module for rising edge delay according to an embodiment of the present invention;
FIG. 5 is a signal timing diagram of an output driving circuit node according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the output driving circuit in the prior art generating ground bounce noise;
fig. 7 is a schematic diagram of the output driving circuit provided by the embodiment of the invention against ground bounce noise.
Detailed Description
The following is a further description of embodiments of the invention, taken in conjunction with the accompanying drawings:
In order to reduce the ground bounce noise generated by the IO output driving circuit as much as possible, the most feasible way is to reduce the current change rate generated by the operation of a single IO output driving circuit as much as possible and reduce the number of parasitic inductances of the power pins or the ground pins, but the power pins or the ground pins are often limited by the product packaging form and cannot be reduced, and meanwhile, in order to ensure that the IC has multiple functions, the parallel operation number of the IO output driving circuit is also difficult to reduce. Aiming at the problems, the invention provides a novel low-noise and anti-ground bounce effect output driving circuit, and the invention mainly aims to realize the reduction of ground bounce noise generated by the output driving circuit by dynamically adjusting the on-resistance of a driving PMOS tube and a driving NMOS tube and realize the anti-high ground bounce noise effect under a static signal.
FIG. 1 shows a low noise and high-elastic noise resistant output driving circuit provided by the embodiment of the invention, wherein the output driving circuit further comprises a PMOS driving module and an NMOS driving module; the PMOS driving module and the pre-driving module are connected to the PMOS input node A, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the PMOS driving module when the PMOS input node A inputs dynamic signals, and the effect of resisting the ground bounce noise is enhanced by improving the output driving resistance when the PMOS input node A inputs static signals;
The NMOS driving module and the pre-driving module are connected to the NMOS input node B, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the NMOS driving module when the NMOS input node B inputs dynamic signals, and the effect of resisting the ground bounce noise is enhanced by improving the output driving resistance when the NMOS input node B inputs static signals.
Specifically, the PMOS driving module and the NMOS driving module are connected to the output node OUT. The dynamic signal is a signal with high-low level turnover and comprises a rising edge signal and a falling edge signal; the static signal is a signal without level inversion, and comprises a high level signal and a low level signal.
As an embodiment of the present invention, as shown in fig. 1, the output driving circuit includes a pre-driving module having a data output terminal DO and an enable output terminal OE as inputs, a PMOS input node a, a PMOS common node A1 connected to the PMOS input node a, an NMOS input node B, an NMOS common node B1 connected to the NMOS input node B, an output node VOUT, a ground terminal VSS, and a supply voltage terminal VCC; the pre-driving module comprises a first inverter INV1 with an output end connected with the PMOS input node A and a second inverter INV2 with an output end connected with the NMOS input node B. As shown in fig. 1, to further illustrate the pre-driving module, the data output terminal DO AND the enable output terminal OE are respectively connected to a first AND gate AND1, the output terminal of the first AND gate AND1 is connected to the input terminal of a first inverter INV1, AND the output terminal of the first inverter INV1 is connected to a PMOS input node a; the enable output OE is connected to an input of the first OR gate OR1 through the third inverter INV3, the data output DO is connected to the other input of the first OR gate OR1, an output of the first OR gate OR1 is connected to an input of the second inverter INV2, and an output of the second inverter INV2 is connected to the NMOS input node B. On the premise that the enable output end OE is set high, as shown in fig. 4, when the data output end DO outputs the rising edge signal, the signal PU1 at the PMOS input node a is a falling edge signal, and the signal PD1 at the NMOS input node B is also a falling edge signal, but the signal PD1 is delayed with respect to the signal PU 1. As shown in fig. 2, the output driving circuit further includes a PMOS driving module connected to the pre-driving module through the PMOS input node a, and an NMOS driving module connected to the pre-driving module through the NMOS input node B.
As an implementation manner of the invention, the PMOS driving module includes a preset number of falling edge time-delay control sub-modules and PMOS transistors divided into preset groups, where the setting of the preset groups and the setting of the number of PMOS transistors in each group both meet the actual driving capability of the chip IO, and the preset number is equal to the preset group minus one; each of the other groups of PMOS tubes except the first group of PMOS tubes corresponds to a falling edge time-delay control submodule; in the embodiment of the invention, for simplifying the explanation, the preset number of groups is set to 3, the preset number is set to 2, all the PMOS tubes in each group are connected in parallel, and can be simplified to be an equivalent PMOS tube, as shown in fig. 2, the first group of PMOS tubes is simplified to be a first PMOS tube PM1, the second group of PMOS tubes is simplified to be a second PMOS tube PM2, and the third group of PMOS tubes is simplified to be a third PMOS tube PM3. The gate of the first PMOS tube PM1 and the output end of the first inverter INV1 are connected to the PMOS input node a. And each PMOS tube in the other groups of PMOS tubes is connected with the output end of one falling edge time delay control submodule through the grid electrode of the PMOS tube, namely the grid electrode of the second PMOS tube PM2 is connected with the first falling edge time delay control submodule OSL1, the grid electrode of the third PMOS tube PM3 is connected with the second falling edge time delay control submodule OSL2, and the input ends of the first falling edge time delay control submodule OSL1 and the second falling edge time delay control submodule OSL2 are connected to the PMOS public node A1. After the signal PU1 of the PMOS input node a turns on the first PMOS tube PM1, the signal PU1 drives the second PMOS tube PM2 after passing through the first falling edge delay control submodule OSL1, the signal PU1 drives the third PMOS tube PM3 after passing through the second falling edge delay control submodule OSL2, and after the PMOS input node a inputs the falling edge signal, the PMOS tubes of each group are controlled to be turned on, wherein the turn-on time width of the second PMOS tube PM2 is limited by the first falling edge delay control submodule OSL1, and the turn-on time width of the third PMOS tube PM3 is limited by the second falling edge delay control submodule OSL 2.
Specifically, the number of the driving PMOS transistors in the first group of PMOS transistors is set to be minimum because the group of PMOS transistors is always turned on during the period when the data output terminal DO outputs the high level, i.e., the PMOS input node a is low level, and the PMOS input node a is first turned on when it is the falling edge signal, according to the ground bounce noise formulaDue toThe maximum value of the value is in direct proportion to the number of the PMOS tubes which are conducted first, so that the current change rate in the level conversion process of the PMOS input node A can be reduced by reducing the number of the first group of PMOS tubes, and then the ground bounce noise of the output driving circuit in the stage of outputting high level at the data output end DO is reduced. When the PMOS common node A1 inputs a dynamic signal, the first falling edge delay control submodule OSL1 controls the on time width of the second PMOS tube PM2, and the second falling edge delay control submodule OSL2 controls the on time width of the third PMOS tube PM3, so as to control the output driving resistor of the PMOS driving module to reduce the rate of change of current, thereby reducing the ground bounce noise; when the PMOS common node A1 inputs a static signal, the first falling edge delay control submodule OSL1 turns off the second PMOS tube PM2, and the second falling edge delay control submodule OSL2 turns off the third PMOS tube PM3, so as to increase the output driving resistance of the PMOS driving module to enhance the effect of resisting high-ground-bounce noise, so that the equivalent output driving resistance of the PMOS driving module under the static working condition is larger than the resistance value when the PMOS tubes of each group of the output driving circuit are simultaneously turned on in the prior art, the influence of ground bounce noise on the output signal of the output driving circuit is weakened, and the ground bounce resistance of the output driving circuit is enhanced.
As an implementation manner of the invention, the NMOS driving module includes a preset number of rising edge control submodules and NMOS transistors divided into preset groups, where the setting of the preset groups and the setting of the number of NMOS transistors in each group both meet the actual driving capability of the chip IO, and the preset number is equal to the preset group minus one; each of the other NMOS tubes except the first NMOS tube corresponds to a rising edge time-delay control submodule; in the embodiment of the present invention, for simplifying the description, the preset number of groups is set to 3, the preset number is set to 2, and all NMOS tubes in each group are connected in parallel, so that the NMOS tubes can be simplified to an equivalent NMOS tube, as shown in fig. 2, the first group of NMOS tubes is simplified to a first NMOS tube NM1, the second group of NMOS tubes is simplified to a second NMOS tube NM2, and the third group of NMOS tubes is simplified to a third NMOS tube NM3. The gate of the first NMOS transistor NM1 and the output end of the second inverter INV2 are connected to the NMOS input node B. And each NMOS tube in the rest groups of NMOS tubes is connected with the output end of a rising edge time delay control submodule through the grid electrode of the NMOS tube, namely the grid electrode of the second NMOS tube NM2 is connected with a first rising edge time delay control submodule OSH1, the grid electrode of the third NMOS tube NM3 is connected with a second rising edge time delay control submodule OSH2, and the input ends of the first rising edge time delay control submodule OSH1 and the second rising edge time delay control submodule OSH2 are connected to the NMOS public node B1. After the signal PD1 of the NMOS input node B turns on the first NMOS transistor NM1, the signal PD1 drives the second NMOS transistor NM2 after passing through the first rising edge delay control submodule OSH1, the signal PD1 drives the third NMOS transistor NM3 after passing through the second rising edge delay control submodule OSH2, and after the NMOS input node B inputs the rising edge signal, each group of NMOS transistors is controlled to be turned on, where the on time width of the second NMOS transistor NM2 is defined by the first rising edge delay control submodule OSH1, and the on time width of the third PMOS transistor PM3 is defined by the second rising edge delay control submodule OSH 2.
Specifically, the number of driving NMOS transistors in the first set of NMOS transistors is minimized because the set of NMOS transistors is always on during the period when the data output terminal DO outputs a high level, i.e., the NMOS input node B is always on during the period when it is high level, and the NMOS input node B is first on when it is a rising edge signal, according to the ground bounce noise formulaDue toThe maximum value of the value is in direct proportion to the number of the NMOS tubes which are conducted first, so that the current change rate in the level conversion process of the NMOS input node B can be reduced by reducing the number of the NMOS tubes of the first group, and then the ground bounce noise of the output driving circuit in the low level stage of the data output end DO is reduced. When the NMOS common node B1 inputs a dynamic signal, the first rising edge delay control submodule OSH1 controls the on time width of the second NMOS transistor NM2, and the second rising edge delay control submodule OSH2 controls the on time width of the third NMOS transistor NM3, so as to control the output driving resistor of the NMOS driving module to reduce the rate of change of current, thereby reducing the ground bounce noise; when the NMOS common node B1 inputs a static signal, the first rising edge delay control submodule OSH1 turns off the second NMOS transistor NM2, and the second rising edge delay control submodule OSH2 turns off the third NMOS transistor NM3, so as to increase the output driving resistance of the NMOS driving module to enhance the effect of resisting high-ground-elasticity noise, so that the equivalent output driving resistance of the NMOS driving module under the static working condition is larger than the resistance of the NMOS driving circuit in the prior art when the NMOS driving circuit is simultaneously turned on, the influence of the high-ground-elasticity noise on the output signal of the output driving circuit is weakened, and the effect of resisting the high-ground-elasticity noise of the output driving circuit is enhanced.
The sources of the PMOS tubes divided into preset groups in the PMOS driving module are connected to a power supply voltage end VCC, and the drains of the PMOS tubes are connected to an output node OUT; the drains of the NMOS transistors divided into preset groups in the NMOS drive module are connected to an output node OUT, and the sources of the NMOS transistors are connected to a ground terminal VSS; each group of PMOS tubes is connected with a corresponding group of NMOS tubes to form a push-pull output structure so as to enhance IO output driving capability, and the numerical value of the preset group number is set to be 3 or more than 3.
As shown in fig. 3, the falling edge delay control submodule includes a first input logic unit s1, a low-level delay unit d1, a fourth inverter INV4 and a second OR gate OR2, and is triggered to operate by a falling edge signal at the PMOS input node a. The logic structure of the falling edge time-delay control sub-module comprises: the input end of the first input logic unit s1 is connected with the PMOS input node A1, the output end of the first input logic unit s1 is connected with the input end of the low-level time delay unit d1, the output end of the low-level time delay unit d1 is connected with the input end of the fourth inverter INV4, and the common node of the output end of the first input logic unit s1 and the input end of the low-level time delay unit d1 and the output end of the fourth inverter INV4 are connected to the two input ends of the second OR gate OR 2. Specifically, as shown in fig. 2, when the falling edge time delay control submodule is used as the first falling edge time delay control submodule OSL1, the output end of the second OR gate OR2 is connected with the gate of the second PMOS tube PM 2; when the falling edge time delay control submodule is used as a second falling edge time delay control submodule OSL2, the output end of the second OR gate OR2 is connected with the gate of the third PMOS tube PM 3. Wherein the first input logic unit s1 is a buffer or a delay unit; the low-level delay unit d1 directly determines the low-level pulse width generated by the falling edge delay control submodule, so as to influence the conduction time of the second PMOS transistor PM2 and the third PMOS transistor PM3, and the conduction time length can be set to be the same or different, which is determined by the load capacitance of the output driving circuit and the circuit working frequency.
As shown in fig. 4, the rising edge delay control submodule includes a second input logic unit s2, a high-level delay unit d2, a fifth inverter INV5, AND a second AND gate AND2, AND is triggered to operate by the rising edge signal of the NMOS input node B. The logic structure of the rising edge time-delay control sub-module comprises: the output end of the second input logic unit s2 is connected with the input end of the high-level delay unit d2, the output end of the high-level delay unit d2 is connected with the input end of the fifth inverter INV5, AND the common node of the output end of the second input logic unit s2 AND the input end of the high-level delay unit d2 AND the output end of the fifth inverter INV5 are connected to the two input ends of the second AND gate AND 2; specifically, as shown in fig. 2, when the rising edge delay control submodule is used as the first rising edge delay control submodule OSH1, the output end of the second AND gate AND2 is connected with the gate of the second NMOS transistor NM 2; when the rising edge time delay control submodule is used as a second rising edge time delay control submodule OSH2, the output end of the second AND gate AND2 is connected with the grid electrode of the third NMOS tube NM 3; wherein the second input logic unit s2 is a buffer or a delay unit; the high-level delay unit d2 directly determines the high-level pulse width generated by the rising edge delay control submodule, so as to influence the on-time of the second NMOS transistor NM2 and the third NMOS transistor NM3, and the on-time length can be set to be the same or different, which is determined according to the load capacitance of the output driving circuit and the circuit working frequency.
In fig. 6, an output circuit schematic diagram of a conventional single IO driving circuit including a package inductance between an output node OUT and a receiving end recevie in the prior art appears, where, for the conventional single IO driving circuit, r_mos in fig. 6 is an equivalent output driving resistance in a low level or high level state where the output node OUT outputs a static state, l_group is a package inductance on a ground line of the IO driving circuit, l_pkg is a package inductance on a power line of the IO driving circuit, c_load is a load capacitance of the IO driving circuit, and p_out is a load output signal. The ground spring noise generated by the IO driving circuit is
When the number N of the IO driving circuits is increased, that is, N outputs of the semiconductor circuits where the IO driving circuits are located are turned over at the same time, the current of the package inductance l_group on the ground line of the IO driving circuits becomes N times, and a larger voltage fluctuation is generated on the ground line, and similarly, a larger voltage fluctuation is also generated on the package inductance l_pkg on the power line of the IO driving circuits. As shown in fig. 6, if the output node OUT is at a static low level, the load output signal p_out should be at a low level, but because the ground line of the IO driving circuit is connected to the ground of a large number of other IO driving circuits generating inversion waveforms, the ground node VSS of the IO driving circuit will generate a ground bounce noise signal, which is transmitted through the pull-down conduction of the NMOS transistor, and has a magnitude equivalent to the original ground bounce noise signal on the ground node VSS, when the load output signal p_out is sent to the receiving end recevie, the receiving end recevie receives a high level pulse signal v_err, thereby causing a receiving error, causing erroneous judgment of other devices and generating a logic error.
As an embodiment of the present invention, an output circuit schematic diagram of fig. 7, in which a package inductor is included between an output node OUT of the output driving circuit and a receiving terminal recevie outside the integrated circuit where the output driving circuit is located, is different from the single IO driving circuit of fig. 6 in that the resistance value of the equivalent output driving resistor in the static working state in fig. 7 is greatly increased relative to that in fig. 6. R_big in FIG. 7 is the equivalent output driving resistance of the output driving circuit under the condition that the output node OUT outputs a static signal, L_group is the packaging inductance on the ground line of the output driving circuit, L_pkg is the packaging inductance on the power line of the output driving circuit, C_load is the load capacitance of the IO driving circuit, and p_out is the load output signal.
When the output node OUT of the output driving circuit is a static low-level signal, the ground wire of the output driving circuit is connected with the ground wires of a large number of other IO output driving circuits generating turnover waveforms in the same chip, so that the ground node VSS of the output driving circuit generates a ground bounce noise signal, and the ground bounce noise signal is transmitted OUT through the NMOS driving module. The voltage peak Vp corresponding to the load output signal p_out is related to the equivalent driving output resistor r_big as follows:
,
Therefore, when the resistance value of the equivalent output driving resistor r_big of the output driving circuit greatly exceeds the equivalent output driving resistor of the common IO driving circuit, and also exceeds the equivalent output driving resistor of most driving circuits adopting the low noise design technology, the voltage fluctuation amplitude corresponding to the load output signal p_out is weakened, so that the receiving signal of the receiving terminal recevie when the output node OUT is a static low level signal is ensured to be a low level signal v_no_err, and logic errors are avoided. The output driving circuit changes the output driving resistance by dynamically adjusting the conduction time of the driving PMOS tube and the driving NMOS tube, particularly, only the first group of PMOS tubes or the first group of NMOS tubes are conducted under the static working condition, and the other groups of MOS tubes are turned off under the control of the rising edge time-delay control sub-module or the falling edge time-delay control sub-module, so that the equivalent output driving resistance is increased, the peak voltage fluctuation amplitude on the load output signal p_out is reduced, and the effect of resisting high-altitude elastic noise is realized.
In the timing chart of the working signal of the output driving circuit provided by the embodiment of the invention, as shown in fig. 5, at time t0, the data output terminal DO sends a rising edge signal to the pre-driving module, the signal PU1 at the PMOS input node a is a falling edge signal, the first PMOS tube PM1 is turned on, the signal PD1 at the NMOS input node B is also a falling edge signal, and the first NMOS tube NM1 is turned off.
As shown in fig. 5, at time t1, the data output terminal DO maintains a high level state, the signal PU2 at the gate of the second PMOS transistor PM2 is a falling edge signal obtained by the signal PU1 through the logic action of the first falling edge delay control submodule OSL1, the second PMOS transistor PM2 is pulled up and turned on, and the signal PD2 at the gate of the second NMOS transistor NM2 is a low level signal obtained by the signal PD1 through the logic action of the first rising edge delay control submodule OSH1, and the second NMOS transistor NM2 is turned off; the signal PU1 at the time t1 keeps a low level, so that the first PMOS tube PM1 is kept on; the signal PD1 at time t1 keeps a low level, so that the first NMOS transistor NM1 keeps turned off.
As shown in fig. 5, at time t2, the data output terminal DO maintains a high level state, the signal PU3 at the gate of the third PMOS transistor PM3 is a falling edge signal obtained by the signal PU1 through the logic action of the second falling edge delay control sub-module OSL2, the third PMOS transistor PM3 is pulled up to be turned on, and the signal PD3 at the gate of the third NMOS transistor NM3 is a low level signal obtained by the signal PD1 through the logic action of the second rising edge delay control sub-module OSH2, and the third NMOS transistor NM3 is turned off; at this time, the pull-up driving output node OUT of the third PMOS transistor PM3 gradually changes from a low level signal to a high level signal. the signal PU1 at the time t2 keeps a low level, so that the first PMOS tube PM1 is kept on; the signal PU2 after the time t2 jumps to a high level, so that the second PMOS tube PM2 is turned off; the signal PD1 at the time t2 keeps a low level, so that the first NMOS tube NM1 keeps turned off; the signal PD2 at time t2 remains low, so that the second NMOS transistor NM2 remains turned off.
In the time period from t0 to t2, according to the change of the output signal of the data output terminal DO, the output driving resistance of the PMOS driving module changes along with the on and off of the PMOS transistors in each group, wherein the first group of PMOS transistors is always turned on, but the number of the PMOS transistors in the group is minimum, and the conduction of the other PMOS transistors in the group is used for assisting in adjusting the output driving resistance of the PMOS driving module, so that the change rate of the current is reduced, and the ground bounce noise is reduced.
As shown in fig. 5, at time t3, the data output terminal DO sends a falling edge signal to the pre-driving module, the signal PU1 at the PMOS input node a is a rising edge signal, the first PMOS transistor PM1 is turned off, the signal PD1 at the NMOS input node B is also a rising edge signal, and the first NMOS transistor NM1 is turned on.
As shown in fig. 5, at time t4, the data output terminal DO maintains a low level state, the signal PU2 at the gate of the second PMOS transistor PM2 is a high level signal obtained by the logic action of the first falling edge delay control submodule OSL1, the second PMOS transistor PM2 is turned off, the signal PD2 at the gate of the second NMOS transistor NM2 is a rising edge signal obtained by the logic action of the first rising edge delay control submodule OSH1, and the second NMOS transistor NM2 is pulled down and turned on; the signal PU1 at the time t4 keeps high level, so that the first PMOS tube PM1 is kept off; the signal PD1 at time t4 keeps high level, so that the first NMOS transistor NM1 keeps on.
As shown in fig. 5, at time t5, the data output terminal DO maintains a low level state, the signal PU3 at the gate of the third PMOS transistor PM3 is a high level signal obtained by the signal PU1 through the logic action of the second falling edge delay control submodule OSL2, the third PMOS transistor PM3 is turned off, and the signal PD3 at the gate of the third NMOS transistor NM3 is a rising edge signal obtained by the signal PD1 through the logic action of the second rising edge delay control submodule OSH2, and the third NMOS transistor NM3 is pulled down and turned on; at this time, the pull-up driving output node OUT of the third PMOS transistor PM3 gradually changes from a high level signal to a low level signal. The signal PU1 at the moment T5 keeps high level, so that the first PMOS tube PM1 is kept off; the signal PU2 at the time t5 is a high-level signal, so that the second PMOS tube PM2 is turned off; the signal PD1 at the time t5 keeps a high level, so that the first NMOS tube NM1 is kept on; the signal PD2 after the time t5 jumps to a low level, so that the second NMOS transistor NM2 is turned off.
In the time period from t3 to t5, according to the signal change output by the data output terminal DO, the output driving resistance of the NMOS driving module changes along with the on and off of each group of NMOS tubes, where the first group of NMOS tubes is always turned on but the number of the NMOS tubes is the smallest, and the conduction of the rest groups of NMOS tubes is used to assist in adjusting the output driving resistance of the NMOS driving module, so as to reduce the current change rate and reduce the ground bounce noise.
Specifically, only when the input signal of the PMOS common node A1 is a falling edge signal, the first falling edge delay control sub-module OSL1 and the second falling edge delay control sub-module OSL2 generate an effective low level pulse, and when other signals are input at the PMOS common node A1, the first falling edge delay control sub-module OSL1 and the second falling edge delay control sub-module OSL2 maintain high level output, so that the on time of driving the third PMOS pipe PM3 and the second PMOS pipe PM2 is limited, and the on start time of the third PMOS pipe PM3 and the second PMOS pipe PM2 is later than that of the first PMOS pipe PM1. The third PMOS pipe PM3 and the second PMOS pipe PM2 may be turned on at the same time, or may have a certain time delay, and the conduction time length of the second PMOS pipe PM2 is controlled by the first falling edge delay control submodule OSL1, and the conduction time length of the third PMOS pipe PM3 is controlled by the second falling edge delay control submodule OSL 2; the on-time lengths of the output driving circuits can be the same or different, and the on-time lengths are determined by the load capacitance and the working frequency of the output driving circuits under the condition of actually driving the output.
In order to reduce the ground bounce noise, the common conduction time of the second PMOS transistor PM2 and the third PMOS transistor PM3 may be controlled to be reduced by the first falling edge delay control sub-module OSL1 and the second falling edge delay control sub-module OSL2, or the common conduction time of the second NMOS transistor NM2 and the third NMOS transistor NM3 may be controlled to be reduced by the first rising edge delay control sub-module OSH1 and the second rising edge delay control sub-module OSH2, especially, in the case of inputting a static signal, the second PMOS transistor PM2, the third PMOS transistor PM3, the second NMOS transistor NM2 and the third NMOS transistor NM3 are substantially not conducted, so as to increase the equivalent driving output resistance of the output driving circuit, and avoid that the preset group of PMOS transistors or NMOS transistors charge the load capacitance through PMOS transistors or increase the ground bounce noise through NMOS transistors at the same time when the last stage driving of the output driving circuit.
The device embodiments described above are merely illustrative and can be understood and implemented by those of ordinary skill in the art without undue burden.

Claims (8)

1. The output driving circuit with low noise and high ground bounce noise resistance comprises a pre-driving module taking a data output end and an enabling output end as inputs, a PMOS input node, a PMOS common node connected with the PMOS input node, an NMOS common node connected with the NMOS input node, an output node, a grounding end and a power supply voltage end; the output driving circuit is characterized by further comprising a PMOS driving module and an NMOS driving module;
the PMOS driving module and the pre-driving module are connected to the PMOS input node, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the PMOS driving module when the PMOS input node inputs dynamic signals, and the effect of resisting the ground bounce noise is enhanced by improving the output driving resistance when the PMOS input node inputs static signals;
The NMOS driving module and the pre-driving module are connected to the NMOS input node, so that the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the NMOS driving module when the NMOS input node inputs a dynamic signal, and the effect of resisting the ground bounce noise is enhanced by improving the output driving resistance when the NMOS input node inputs a static signal;
wherein the PMOS driving module and the NMOS driving module are connected to the output node; the dynamic signal is a signal with level inversion, and the static signal is a signal without level inversion;
The PMOS driving module comprises a preset number of falling edge time-delay control submodules and PMOS tubes divided into preset groups; the pre-driving module comprises a first inverter with an output end connected with the PMOS input node and a second inverter with an output end connected with the NMOS input node; the grid electrodes of the first group of PMOS tubes are connected with the output end of the first inverter to be connected with the PMOS input node, the other groups of PMOS tubes are correspondingly connected with the output end of one falling edge time-delay control submodule through the grid electrodes of the first group of PMOS tubes, and the input ends of the preset number of falling edge time-delay control submodules are connected to the PMOS public node, so that when the PMOS public node inputs dynamic signals, the falling edge time-delay control submodule adjusts the output driving resistance of the PMOS driving module to reduce the change rate of current by controlling the conduction time of each group of PMOS tubes, and the ground bounce noise is reduced; when the PMOS public node inputs a static signal, the falling edge delay control submodule increases the output driving resistance of the PMOS driving module by turning off all groups of PMOS tubes so as to enhance the effect of resisting high-ground-bounce noise;
The NMOS driving module comprises a preset number of rising edge time-delay control submodules and NMOS tubes divided into preset groups; the grid electrodes of the first group of NMOS tubes and the output end of the second inverter are connected to the NMOS input node, the other groups of NMOS tubes are correspondingly connected with the output end of a rising edge time-delay control submodule through the grid electrodes of the first group of NMOS tubes, and the input ends of the preset number of rising edge time-delay control submodules are connected to the NMOS common node, so that when the NMOS common node inputs a dynamic signal, the falling edge time-delay control submodule adjusts the output driving resistance of the NMOS driving module to reduce the change rate of current by controlling the conduction time of each group of NMOS tubes, and the ground bounce noise is reduced; when the NMOS common node inputs a static signal, the falling edge delay control submodule increases the output driving resistance of the NMOS driving module by turning off all groups of NMOS tubes so as to enhance the effect of resisting high-ground-bounce noise;
Wherein the preset number is equal to the preset group number minus one; each of the other groups of PMOS tubes corresponds to one falling edge time delay control submodule; and each of the other NMOS tubes corresponds to one rising edge time delay control submodule.
2. The output driving circuit according to claim 1, wherein the PMOS driving module includes PMOS transistors divided into a predetermined number of groups, and the number of the PMOS transistors in the first group is smaller than that of the PMOS transistors in the remaining groups, so that the data output terminal is a ground bounce noise reduction in a high level stage;
the number of the first group of NMOS tubes is smaller than that of the rest groups of NMOS tubes, so that the ground bounce noise of the data output end in a low level stage is reduced.
3. The output driving circuit according to claim 2, wherein sources of the PMOS transistors divided into a predetermined number of groups in the PMOS driving module are all connected to the supply voltage terminal, and drains thereof are all connected to the output node;
And the drains of the NMOS transistors divided into preset groups in the NMOS driving module are connected to the output node, and the sources of the NMOS transistors are connected to the grounding terminal.
4. An output driving circuit according to any one of claims 1 to 3, wherein the value of the preset group number is set to 3 or more.
5. The output driving circuit according to claim 1, wherein the falling edge delay control submodule includes a first input logic unit, a low-level delay unit, a fourth inverter and a second or gate, wherein an input end of the first input logic unit is connected to the PMOS input node, an output end of the first input logic unit is connected to an input end of the low-level delay unit, an output end of the low-level delay unit is connected to an input end of the fourth inverter, a common node of the output end of the first input logic unit connected to the input end of the low-level delay unit and an output end of the fourth inverter are connected to two input ends of the second or gate, and an output end of the second or gate is connected to gates of a corresponding group of PMOS tubes in the remaining groups of PMOS tubes;
the first input logic unit is a buffer or a delay unit, and the low-level delay unit determines the output low-level pulse width.
6. The output driving circuit according to claim 1, wherein the rising edge delay control submodule includes a second input logic unit, a high-level delay unit, a fifth inverter and a second and gate, wherein an input end of the second input logic unit is connected to the NMOS input node, an output end of the second input logic unit is connected to an input end of the high-level delay unit, an output end of the high-level delay unit is connected to an input end of the fifth inverter, a common node of the output end of the second input logic unit connected to the input end of the high-level delay unit and an output end of the fifth inverter are connected to two input ends of the second and gate, and an output end of the second and gate is connected to gates of a corresponding group of NMOS transistors in the remaining groups of NMOS transistors;
The second input logic unit is a buffer or a delay unit, and the high-level delay unit determines the output high-level pulse width.
7. The output driving circuit according to claim 5 or claim 6, wherein the falling edge delay control submodule controls the conduction time length and the conduction start time of the other PMOS transistors; and the rising edge delay control submodule controls the conduction time length and the conduction starting time of the rest NMOS tubes.
8. A method of reducing ground bounce noise based on the output drive circuit of any one of claims 1 to 3, the method comprising:
When the data output end DO inputs a rising edge signal into the pre-driving module, the PMOS input node receives a falling edge signal, and the data output end DO turns on a first group of PMOS tubes in the PMOS driving module and triggers the falling edge delay control submodule to output a low-level pulse signal, and turns on the PMOS tubes corresponding to the other groups, so that the conduction time length and the conduction starting time of the PMOS tubes of the other groups are controlled, and the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the PMOS driving module;
When the data output end DO keeps a high-level state, the PMOS input node keeps a low-level signal, a first group of PMOS tubes in the PMOS driving module are continuously conducted, the falling edge delay control submodule outputs a high level, and other groups of PMOS tubes are turned off, so that the output driving resistance of the output driving circuit is increased, and the effect of resisting high-altitude elastic noise is enhanced;
when the data output end DO inputs a falling edge signal into the pre-driving module, the NMOS input node receives the rising edge signal, and the rising edge delay control submodule is triggered to output a high-level pulse signal to turn on the corresponding NMOS tubes of the other groups, so that the conduction time length and the conduction starting time of the NMOS tubes of the other groups are controlled, and the ground bounce noise is reduced by dynamically adjusting the output driving resistance of the NMOS driving module;
When the data output terminal DO keeps a low level state, the PMOS input node keeps a high level signal, a first group of NMOS tubes in the NMOS drive module are continuously conducted, the rising edge delay control submodule outputs a low level, and other groups of NMOS tubes are turned off, so that the output drive resistance of the output drive circuit is increased, and the effect of resisting high-altitude elastic noise is enhanced.
CN201810660099.6A 2018-06-25 2018-06-25 Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method Active CN108494394B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810660099.6A CN108494394B (en) 2018-06-25 2018-06-25 Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810660099.6A CN108494394B (en) 2018-06-25 2018-06-25 Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method

Publications (2)

Publication Number Publication Date
CN108494394A CN108494394A (en) 2018-09-04
CN108494394B true CN108494394B (en) 2024-07-09

Family

ID=63343083

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810660099.6A Active CN108494394B (en) 2018-06-25 2018-06-25 Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method

Country Status (1)

Country Link
CN (1) CN108494394B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109245756B (en) * 2018-11-07 2023-10-03 深圳讯达微电子科技有限公司 Method for reducing power domain switching noise and chip output interface circuit
CN110677021B (en) * 2019-09-23 2021-01-08 北京时代民芯科技有限公司 Output drive circuit of anti ground bounce noise
CN113346893B (en) * 2020-12-24 2022-03-18 澜起电子科技(昆山)有限公司 Drive output circuit, chip and drive output method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104079289A (en) * 2014-07-15 2014-10-01 湖南进芯电子科技有限公司 Output circuit with ground bounce resistance
CN208424337U (en) * 2018-06-25 2019-01-22 珠海市一微半导体有限公司 A kind of output driving circuit of low noise and anti-high ground bounce noise

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043231A (en) * 1998-12-28 2000-07-15 김영환 Data transmitter
KR100360550B1 (en) * 2000-12-21 2002-11-13 한국과학기술원 Low power small swing Bus driver using current feedback
CN101795132B (en) * 2010-04-02 2012-11-28 日银Imp微电子有限公司 Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104079289A (en) * 2014-07-15 2014-10-01 湖南进芯电子科技有限公司 Output circuit with ground bounce resistance
CN208424337U (en) * 2018-06-25 2019-01-22 珠海市一微半导体有限公司 A kind of output driving circuit of low noise and anti-high ground bounce noise

Also Published As

Publication number Publication date
CN108494394A (en) 2018-09-04

Similar Documents

Publication Publication Date Title
JP3014164B2 (en) Output buffer circuit
JP2572500B2 (en) Driver circuit, low noise driver circuit and low noise low voltage swing driver / receiver circuit
CN108494394B (en) Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method
US20020149392A1 (en) Level adjustment circuit and data output circuit thereof
JPH05259875A (en) Output buffer driver circuit
JPS63234622A (en) Data output circuit
JPH05243940A (en) Output buffer device
JP3410547B2 (en) Output circuit of semiconductor device
TWI394363B (en) Output driving circuit capable of reducing emi effect
JP3248103B2 (en) MOS transistor output circuit
CN107835011B (en) High-reliability tri-state output circuit
CN208424337U (en) A kind of output driving circuit of low noise and anti-high ground bounce noise
CN110677021B (en) Output drive circuit of anti ground bounce noise
US8860470B1 (en) Input/output line driver circuit
JPH04281294A (en) Driving circuit
US6864705B2 (en) Output buffer with low power/ground bounce noise and method for operating the same
CN112798854B (en) DC-DC zero crossing point detection circuit and control method
KR100410556B1 (en) Driving method of I/O driver for reducing noise
JP3299071B2 (en) Output buffer circuit
CN110289847B (en) Output driving circuit for reducing noise of power line and ground line
TWI695377B (en) Buffer output circuit and driving method thereof
CN109245756B (en) Method for reducing power domain switching noise and chip output interface circuit
CN118199565A (en) Schmidt trigger pulse control low-noise driving circuit
JP2017153095A (en) Semiconductor circuit and semiconductor device
CN114006612A (en) High-voltage side gate drive circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 519000 2706, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong

Applicant after: Zhuhai Yiwei Semiconductor Co.,Ltd.

Address before: Room 105-514, No.6 Baohua Road, Hengqin New District, Zhuhai City, Guangdong Province

Applicant before: AMICRO SEMICONDUCTOR Co.,Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant