CN107784981B - Device applied to display and related image display method - Google Patents
Device applied to display and related image display method Download PDFInfo
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- CN107784981B CN107784981B CN201610711956.1A CN201610711956A CN107784981B CN 107784981 B CN107784981 B CN 107784981B CN 201610711956 A CN201610711956 A CN 201610711956A CN 107784981 B CN107784981 B CN 107784981B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The invention relates to a device applied to a display, which comprises a receiving circuit, a detection circuit, an image processing circuit and a response time acceleration circuit, wherein the receiving circuit is used for receiving an input image signal; the detection circuit detects a frame update rate of image data of a frame in the input image signal; the image processing circuit performs image processing on the image data of the frame to generate target pixel values of a plurality of pixels of the frame; the response time acceleration circuit determines a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate and outputs the plurality of adjusted pixel values to a display panel; wherein, for a specific pixel, the adjusted pixel value of the specific pixel is different under different frame update rates.
Description
Technical Field
The present invention relates to a display, and more particularly, to a method for accelerating response time of a liquid crystal display.
Background
In the current lcd panel, a response time acceleration (response time acceleration) method is usually used to accelerate the response time of the liquid crystal, so as to avoid the afterimage and make the image displayed more clearly. For example, if the pixel value (gray-scale value) of the pixel needs to be changed from 10 to 200, the driving circuit of the display may set the pixel value of the pixel to 230 to accelerate the turning of the driving liquid crystal by using a higher voltage difference, and then switch to 200 to make the pixel display the correct pixel value. However, since the pixel value 230 is not the luminance that the pixel actually needs to display, there is a possibility that some side effects may be caused on the image display.
In addition, there are some techniques for dynamically changing frame update frequency (frame rate), which varies according to the content of the image data to make the image smooth, however, if the same response time acceleration intensity is applied at different frame update frequencies, the above-mentioned image display side effects may be more serious.
Disclosure of Invention
Therefore, it is an object of the present invention to provide a latency acceleration method, which can adopt different latencies at different frame update rates to solve the problems in the prior art.
In one embodiment of the present invention, an apparatus for a display includes a receiving circuit, a detecting circuit, an image processing circuit, and a response time accelerating circuit, wherein the receiving circuit is configured to receive an input image signal; the detection circuit detects a frame update rate of image data of a frame in the input image signal; the image processing circuit is coupled to the detection circuit and is used for performing image processing on the image data of the frame to generate a plurality of target pixel values of a plurality of pixels of the frame; the response time acceleration circuit is coupled to the detection circuit and used for determining a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate and outputting the plurality of adjusted pixel values to a display panel; wherein, for a specific pixel of the plurality of pixels, the adjusted pixel value of the specific pixel generated by the latency accelerator circuit is different at different frame update rates.
In another embodiment of the present invention, an image displaying method applied to a display includes: receiving an input image signal; detecting a frame update rate of image data of a frame in the input image signal; performing image processing on the image data of the frame to generate a plurality of target pixel values of a plurality of pixels of the frame; determining a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate, and outputting the plurality of adjusted pixel values to a display panel; wherein, for a specific pixel of the plurality of pixels, the adjusted pixel value of the specific pixel is different at different frame update rates.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a schematic diagram of an apparatus according to an embodiment of the invention.
FIG. 2 is a diagram illustrating an operation of a latency acceleration circuit according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of the operation of a response time acceleration circuit according to another embodiment of the present invention.
FIG. 4 is a schematic diagram of the operation of a response time acceleration circuit according to another embodiment of the present invention.
FIG. 5 is a flowchart illustrating an image displaying method applied to a display according to an embodiment of the present invention.
Elements in the figures are numbered as follows:
100 device
110 receiving circuit
120 decoder
122 detection circuit
130 image processing circuit
140 reaction time acceleration circuit
150 storage unit
152_1 to 152_ N lookup tables
160 output circuit
500 to 510 steps
Detailed Description
Please refer to fig. 1, which is a diagram illustrating an apparatus 100 according to an embodiment of the present invention. As shown in fig. 1, the apparatus 100 includes a receiving circuit 110, a decoder 120, an image processing circuit 130, a latency accelerator 140, a storage unit 150, and an output circuit 160, wherein the decoder 120 includes a detection circuit 122, and the storage unit 150 stores look-up tables (look-up tables) 152_1 to 152_ N. In the embodiment, the apparatus 100 is applied to a display, for example, a television with a liquid crystal panel, and is configured to receive and process an input video signal Din from an external device, such as a video player or a display card in a computer, and then generate an output video data Dout to a display panel of the television for displaying.
The apparatus 100 of the present embodiment is particularly applicable to a situation where the frame rate of the input video signal Din changes dynamically, i.e. the frame rate of the input video signal Din from the external apparatus changes differently according to the video content, for example, when the content of a plurality of consecutive frames in the input video signal Din changes less (e.g. approaches a still picture), the input video signal Din has a lower frame rate; conversely, when the content of a plurality of consecutive frames in the input video signal Din varies greatly, the input video signal Din has a higher frame update rate. In addition, the apparatus 100 in this embodiment may dynamically adjust the output pixel value according to the frame update rate of the input video signal Din, so that the liquid crystal corresponding to the pixels in the display panel may have different response time acceleration intensities. The specific operational details are as follows.
In the operation of the apparatus 100, first, the receiving circuit 110 receives the input video signal Din, the decoder 120 decodes the input video signal Din to obtain video data of a frame, and the detecting circuit 122 detects a frame update rate of the frame. Next, the image processing circuit 130 receives the image data of the frame from the decoder 120, and generates target pixel values of a plurality of pixels of the frame after performing the processes of enlargement/reduction, color, and brightness on the image data of the frame. Then, the latency accelerator 140 selects a specific lookup table from the lookup tables 152_1 to 152_ N in the storage unit 150 according to the frame update rate of the frame provided by the decoder 120/detection circuit 122, and determines adjusted pixel values of the pixels from the specific lookup table according to the target pixel values of the pixels of the frame and the pixel values of the pixels of the previous frame. Finally, the output circuit 160 outputs the adjusted pixel values to the display panel for display.
In the present embodiment, assuming that the frame update rate of the input video signal Din varies from 30Hz to 120Hz, the storage unit 150 may include 9 lookup tables 152_1 to 152_9, wherein the lookup table 152_1 corresponds to the frame update rate of 30Hz to 40Hz, the lookup table 152_2 corresponds to the frame update rate of 40Hz to 50Hz, the lookup table 152_3 corresponds to the frame update rate of 50Hz to 60Hz …, and so on. The latency accelerator 140 selects a corresponding look-up table according to the frame update rate of the frame provided by the decoder 120/detector 122, for example, the look-up table 152_1 is selected as the specific look-up table when the frame update rate of the frame is 30Hz, and the look-up table 152_4 is selected as the specific look-up table when the frame update rate of the frame is 60 Hz. In addition, in the embodiment, when the frame update rate of the frame is lower, the strength of the response time acceleration performed by the response time acceleration circuit 140 according to the specific lookup table is weaker, that is, the adjusted pixel value generated by the response time acceleration circuit 140 is closer to the pixel value that should be displayed (i.e., the target pixel value to be output by the image processing circuit 130). In another embodiment of the present invention, the storage unit 150 may not include a plurality of lookup tables, but only include one lookup table corresponding to a basic frame update rate, for example, the basic frame update rate is the aforementioned 60-70 Hz, the lookup table 152_4 is stored in the storage unit 150, if the frame update rate of the frame is lower than 60Hz, the response time acceleration circuit 140 multiplies the response time acceleration strength looked up by the lookup table 152_4 by a gain smaller than 1, if the frame update rate of the frame is lower, the gain value is lower, otherwise, if the frame update rate of the frame is higher than 60Hz, the response time acceleration circuit 140 multiplies the response time acceleration strength looked up by the lookup table 152_4 by a gain larger than 1, and if the frame update rate of the frame is higher, the gain value is higher.
For example, please refer to fig. 2, which is a schematic diagram illustrating an operation of the latency acceleration circuit 140 according to an embodiment of the present invention. In fig. 2, the frame update rate of the input video signal Din is 60Hz, and for a specific pixel, assuming that the pixel value of the specific pixel in the previous frame is "10" and the pixel values of the specific pixel in the current frame and the next frame are "200", in order to accelerate the response time of the liquid crystal, the response time acceleration circuit 140 determines an adjusted pixel value "230" according to the lookup table 152_4, and the output circuit 160 transmits the adjusted pixel value "230" to the display panel for displaying. Then, in the next frame, the pixel value of the specific pixel output by the output circuit 160 returns to "200".
The shaded portion shown in fig. 2 is not the luminance that the pixel actually needs to display, and therefore can be regarded as a reference index of a side effect on image display, and the side effect on image display increases as the area thereof increases.
Next, please refer to fig. 3, which is a schematic diagram illustrating an operation of the latency acceleration circuit 140 according to another embodiment of the present invention. In fig. 3, the frame update rate of the input video signal Din is 30Hz, and for a specific pixel, assuming that the pixel value of the specific pixel in the previous frame is "10" and the pixel values of the specific pixel in the current frame and the next frame are "200", in order to accelerate the response time of the liquid crystal, the response time acceleration circuit 140 determines an adjusted pixel value "210" according to the lookup table 152_1, and the output circuit 160 transmits the adjusted pixel value "210" to the display panel for displaying. Then, in the next frame, the pixel value of the specific pixel output by the output circuit 160 returns to "200".
In the example of fig. 3, since the frame update rate is low, if the adjusted pixel value is still set to "230" by using the lookup table 152_4, it is conceivable that the area of the diagonal line portion becomes larger, thereby causing a worse image display side effect; therefore, by using another lookup table 152_1 to determine the adjusted pixel value "210", the area of the diagonal line portion can be reduced, and the image display side effect will not increase due to the low frame update rate.
Fig. 4 is a schematic diagram illustrating the operation of the reaction time acceleration circuit 140 according to another embodiment of the present invention. As shown in fig. 4, the frame update rates of a plurality of consecutive frames are dynamically changing, and when the frame update rate is higher, the response time acceleration circuit 140 employs a stronger response time acceleration degree, i.e., the difference between the adjusted pixel value and the target pixel value (actual pixel value) is larger; when the frame rate is low, the latency acceleration circuit 140 uses a weaker latency acceleration, i.e., the difference between the adjusted pixel value and the target pixel value (actual pixel value) is smaller. Through the technical scheme of dynamically adjusting the acceleration degree of the response time according to the frame update rate, the quality of the displayed image can be kept under the condition that the response time is accelerated.
Please refer to fig. 5, which is a flowchart illustrating an image displaying method applied to a display according to an embodiment of the present invention. The process is described below with reference to FIGS. 1-4 and the disclosure of the specification.
Step 500: the process begins.
Step 502: an input image signal is received.
Step 504: the input video signal is decoded to obtain video data of a frame, and a frame update rate of the frame is detected.
Step 506: the image data of the frame is subjected to image processing to generate pixel values of a plurality of pixels of the frame.
Step 508: a plurality of adjusted pixel values of the plurality of pixels are determined according to the frame update rate, wherein different frame update rates generate different adjusted pixel values.
Step 510: the adjusted pixel values are transmitted to a display panel.
Briefly summarized, in the apparatus and method for displaying an image of the present invention, the response time acceleration level is changed according to the frame update rate, and the lower the frame update rate, the lower the response time acceleration level is, so as to avoid the side effect of displaying an image being amplified due to the lower frame update rate. The invention can make the display image maintain the image quality under the condition of accelerating the response time.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. An apparatus for use in a display, comprising:
a receiving circuit for receiving an input image signal;
a detection circuit, coupled to the receiving circuit, for detecting a frame update rate of a frame of image data in the input image signal;
an image processing circuit, coupled to the detection circuit, for performing image processing on the image data of the frame to generate a plurality of target pixel values of a plurality of pixels of the frame; and
a response time acceleration circuit, coupled to the detection circuit and the image processing circuit, for determining a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate and outputting the plurality of adjusted pixel values to a display panel; wherein, for a specific pixel in the plurality of pixels, the adjusted pixel value of the specific pixel generated by the response time accelerating circuit is different under different frame updating rates;
when the frame has a first frame updating rate, the response time acceleration circuit determines that the specific pixel has a first adjusted pixel value; and when the frame has a second frame update rate lower than the first frame update rate, the latency accelerator circuit determines that the specific pixel has a second adjusted pixel value, wherein a difference between the second adjusted pixel value and the target pixel value of the specific pixel is lower than a difference between the first adjusted pixel value and the target pixel value.
2. The apparatus of claim 1, wherein the adjusted pixel value of the specific pixel determined by the latency accelerator circuit is closer to the target pixel value of the specific pixel output by the image processing circuit when the frame rate is lower.
3. The apparatus of claim 1, further comprising:
a storage unit for storing a plurality of lookup tables, wherein the plurality of lookup tables respectively correspond to different frame update rates;
the response time acceleration circuit selects a corresponding look-up table from the plurality of look-up tables of the storage unit according to the frame update rate, and determines the adjusted pixel value of the specific pixel from the corresponding look-up table according to the target pixel value of the specific pixel.
4. The apparatus of claim 3, wherein the plurality of lookup tables correspond to different frame update rate intervals, respectively.
5. The apparatus of claim 3, wherein the latency accelerator circuit determines the adjusted pixel value of the particular pixel from the corresponding lookup table according to the target pixel value of the particular pixel of the frame and a pixel value of the particular pixel of a previous frame.
6. The apparatus of claim 1, wherein the apparatus is disposed in a television, and wherein the apparatus is disposed in a television
The frame update rate of the input video signal received by the receiving circuit is dynamically changed.
7. An image display method applied to a display comprises the following steps:
receiving an input image signal;
detecting a frame update rate of image data of a frame in the input image signal;
performing image processing on the image data of the frame to generate a plurality of target pixel values of a plurality of pixels of the frame; and
determining a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate, and outputting the plurality of adjusted pixel values to a display panel; wherein, aiming at a specific pixel in the plurality of pixels, the adjusted pixel value of the specific pixel is different under different frame updating rates;
determining a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate, and outputting the plurality of adjusted pixel values to the display panel includes:
determining that the specific pixel has a first adjusted pixel value when the frame has a first frame update rate; and
determining that the specific pixel has a second adjusted pixel value when the frame has a second frame update rate lower than the first frame update rate;
wherein a difference between the second adjusted pixel value and the target pixel value of the particular pixel is less than a difference between the first adjusted pixel value and the target pixel value.
8. The method of claim 7, wherein the step of determining the gain values of the pixels according to the frame update rate comprises:
the determined adjusted pixel value of the specific pixel is closer to the target pixel value of the specific pixel when the frame update rate is lower.
9. The image display method of claim 7, further comprising:
providing a plurality of lookup tables, wherein the plurality of lookup tables respectively correspond to different frame update rates; and
determining a plurality of adjusted pixel values of the plurality of pixels according to the frame update rate, and outputting the plurality of adjusted pixel values to the display panel includes:
selecting a corresponding look-up table from the plurality of look-up tables according to the frame update rate; and
the adjusted pixel value of the specific pixel is determined from the corresponding look-up table according to the target pixel value of the specific pixel.
10. The image displaying method of claim 9, wherein the plurality of lookup tables respectively correspond to different frame update rate intervals.
11. The method of claim 9, wherein the step of determining the adjusted pixel value of the specific pixel from the corresponding lookup table according to the target pixel value of the specific pixel comprises:
the adjusted pixel value of the specific pixel is determined from the corresponding look-up table according to the target pixel value of the specific pixel of the frame and a pixel value of the specific pixel of a previous frame.
12. The image display method of claim 7, wherein the image display method is applied to a television, and the frame update rate of the input image signal is dynamically changed.
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| CN201610711956.1A CN107784981B (en) | 2016-08-24 | 2016-08-24 | Device applied to display and related image display method |
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| US8179388B2 (en) * | 2006-12-15 | 2012-05-15 | Nvidia Corporation | System, method and computer program product for adjusting a refresh rate of a display for power savings |
| US8804048B2 (en) * | 2007-10-25 | 2014-08-12 | Marvell World Trade Ltd. | Motion-adaptive alternate gamma drive for LCD |
| CN101533611B (en) * | 2008-03-10 | 2014-03-12 | 群创光电股份有限公司 | Liquid crystal display panel, liquid crystal display device and control method thereof |
| CN101667401B (en) * | 2008-09-03 | 2013-01-09 | 奇美电子股份有限公司 | Liquid crystal panel driving method and liquid crystal display |
| US8345070B2 (en) * | 2009-06-10 | 2013-01-01 | Himax Media Solutions, Inc. | Apparatus and method for frame rate up conversion |
| CN102915710B (en) * | 2012-11-09 | 2015-02-04 | 福州华映视讯有限公司 | Sequential control circuit for reducing flickering of liquid crystal panel and relevant method of sequential control circuit |
| TW201419848A (en) * | 2012-11-12 | 2014-05-16 | Novatek Microelectronics Corp | Motion detection circuit and method for detecting motion images thereof |
| US9620064B2 (en) * | 2013-03-13 | 2017-04-11 | Apple Inc. | Compensation methods for display brightness change associated with reduced refresh rate |
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