CN107750392A - 半导体芯片以及使用了该半导体芯片的半导体模块 - Google Patents

半导体芯片以及使用了该半导体芯片的半导体模块 Download PDF

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CN107750392A
CN107750392A CN201680036701.8A CN201680036701A CN107750392A CN 107750392 A CN107750392 A CN 107750392A CN 201680036701 A CN201680036701 A CN 201680036701A CN 107750392 A CN107750392 A CN 107750392A
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semiconductor chip
control
terminal
pad
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CN107750392B (zh
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河野宪司
田边广光
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Denso Corp
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Denso Corp
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Abstract

提供一种半导体芯片。半导体芯片具备：开关元件(11a～16a)，具有栅极电极；第1控制焊盘(71)，与上述栅极电极电连接，被施加控制上述开关元件的接通、断开的电压；以及第2控制焊盘(72)，在上述开关元件接通时，在与上述第1控制焊盘之间构成供控制电流流过的电流路径，上述第1控制焊盘以及上述第2控制焊盘中的某一方的控制焊盘被配置成被另一方的控制焊盘夹着。

Description

半导体芯片以及使用了该半导体芯片的半导体模块
相关申请的交叉引用
本申请基于2015年6月24日提出的日本申请号2015－126785号，在此引用其记载内容。
技术领域
本公开涉及具有与控制端子连接的多个焊盘(Pad)的半导体芯片、以及使用了该半导体芯片的半导体模块。
背景技术
以往，例如在专利文献1中，作为构成逆变器的半导体模块，提出了所谓的2in1构造的半导体模块。即，在该半导体模块中，包括具有构成上臂的开关元件的半导体芯片、以及具有构成下臂的开关元件的半导体芯片，各半导体芯片的开关元件以串联的方式连接。此外，在该半导体模块中，各半导体芯片的构成被设为共同，并分别形成有IGBT元件。
而且，在形成有IGBT元件的半导体芯片的发射极侧分别配置上侧散热片，并且在集电极侧分别配置下侧散热片，上臂侧的上侧散热片与下臂侧的下侧散热片被连接，从而上臂的开关元件与下臂的开关元件被电连接。另外，上臂侧的下侧散热片与第1主端子(正极端子)连接，下臂侧的下侧散热片与第2主端子(输出端子)连接，下臂侧的上侧散热片与第3主端子(负极端子)连接。此外，从上侧散热片上观察时，第1～第3主端子相对于半导体芯片向相同方向延伸设置，若第1主端子与第3主端子的间隔变宽，则寄生电感变大，因此在第1主端子与第2主端子之间配置第3主端子。
另外，作为用于控制形成于各半导体芯片的IGBT元件的控制焊盘，各半导体芯片具有栅极焊盘以及开尔文发射极焊盘。而且，各控制焊盘与栅极端子以及开尔文发射极端子被电连接。
在这样的半导体模块中，通过交替地切换上臂以及下臂的开关元件的接通、断开，从而切换从第1主端子向第2主端子的主电流、以及从第2主端子向第3主端子的主电流。
现有技术文献
专利文献
专利文献1：JP2013－149684A
发明内容
然而，在上述那种半导体模块(半导体芯片)中，在对栅极焊盘施加规定的电压而使IGBT元件成为接通状态时，基于流经各主端子之间的主电流而感应产生磁通。而且，以阻碍感应产生的磁通的方式，在栅极端子与开尔文发射极端子之间产生控制电流(感应电流)，因此施加于栅极焊盘的电压变动。
另外，在上述半导体模块中，由于在第1主端子与第2主端子之间配置有第3主端子，因此主电流从第1主端子流向第2主端子的方向和主电流从第2主端子流向第3主端子的方向变得相反。换句话说，上臂的半导体芯片和下臂的半导体芯片中产生的控制电流成为逆向。
而且，在上述半导体模块中，由于上臂的半导体芯片与下臂的半导体芯片设为相同的构成，因此在一方的半导体芯片中，控制电流从开尔文发射极端子流向栅极端子侧，在另一方的半导体芯片中，控制电流从栅极端子流向开尔文发射极端子侧。在该情况下，若控制电流从栅极端子侧流向开尔文发射极端子侧，则施加于栅极焊盘的电压在使IGBT元件接通的一侧增加，成为误工作的原因。
本公开鉴于上述点，目的之一在于提供能够抑制开关元件误工作的半导体芯片以及使用了该半导体芯片的半导体模块。
本公开的一方面的半导体芯片具备多个焊盘和具有栅极电极的开关元件。多个焊盘具有：第1控制焊盘，与栅极电极电连接，被施加控制开关元件的接通、断开的电压；以及第2控制焊盘，在开关元件接通时，在与第1控制焊盘之间构成供控制电流流过的电流路径，第1控制焊盘以及第2控制焊盘中的某一方的控制焊盘被配置成被另一方的控制焊盘夹着。
据此，在第1控制焊盘以及第2控制焊盘连接控制端子时，能够适当地变更连接于第1控制焊盘以及第2控制焊盘的控制端子的排列。换句话说，能够以使控制电流从第2控制焊盘流向第1控制焊盘的方式，将控制端子连接于第1控制焊盘以及第2控制焊盘。因此，能够通过控制电流抑制开关元件误工作。
另外，本公开的一方面的半导体模块具备：构成上臂的第1半导体芯片，形成有具有栅极电极的开关元件，在表面形成有第1主焊盘，并且相邻地形成有多个控制焊盘，在背面形成有第2主焊盘；构成下臂的第2半导体芯片，形成有具有栅极电极的开关元件，并且被设为与第1半导体芯片相同的结构，与第1半导体芯片相邻地配置；正极端子，与第1半导体芯片的第2主焊盘电连接；负极端子，与第2半导体芯片的第1主焊盘电连接；输出端子，与第1半导体芯片的第1主焊盘以及第2半导体芯片的第2主焊盘电连接，从而成为上臂以及下臂的中间电位；以及多个控制端子，与多个控制焊盘连接。在从相对于第1半导体芯片以及第2半导体芯片的表面的法线方向观察时，正极端子、负极端子、输出端子相对于第1半导体芯片以及第2半导体芯片向相同方向延伸设置，并且在正极端子与输出端子之间配置有负极端子，多个控制焊盘具有：第1控制焊盘，与栅极电极电连接，被施加控制开关元件的接通、断开的电压；以及第2控制焊盘，在开关元件接通时，在与第1控制焊盘之间构成供控制电流流过的电流路径，第1控制焊盘以及第2控制焊盘中的某一方的焊盘被配置成被另一方的焊盘夹着，控制端子具有与第1控制焊盘连接的第1控制端子和与第2控制焊盘连接的第2控制端子，第1控制端子以及第2控制端子以使控制电流从第2控制端子流向第1控制端子的方式，与第1半导体芯片以及第2半导体芯片中的第1控制焊盘以及第2控制焊盘分别电连接。
据此，在第1半导体芯片以及第2半导体芯片中，第1控制端子以及第2控制端子分别以使控制电流从第2控制端子流向第1控制端子的方式与第1控制焊盘以及第2控制焊盘电连接。因此，在第1半导体芯片以及第2半导体芯片中，能够利用控制电流抑制第1控制焊盘的电位向使开关元件接通的一侧增加，从而能够抑制开关元件误工作。
附图说明
关于本公开的上述目的以及其他目的、特征及优点通过参照所附的附图来进行的下述详细的记述而变得更加明确。
图1是应用第1实施方式中的半导体模块而构成的逆变器的电路图。
图2是半导体模块的俯视示意图。
图3是相当于图2中的III－III剖面的剖面图。
图4是半导体芯片的俯视图。
图5是相当于图4中的V－V剖面的剖面图。
图6A是表示上臂中的控制电流的流动方向的图。
图6B是表示下臂中的控制电流的流动方向的图。
图7是第2实施方式中的半导体芯片的俯视图。
图8是第3实施方式中的半导体模块的俯视图。
具体实施方式
以下，基于图对实施方式进行说明。此外，以在下的各实施方式相互中，对相互相同或等效的部分附加相同的附图标记来进行说明。
(第1实施方式)
对第1实施方式进行说明。在本实施方式中，对将本公开的技术思想应用于构成三相马达驱动用的逆变器的半导体模块的例子进行说明。
首先，对逆变器的电路构成进行说明。逆变器用于基于直流电源对作为负荷的三相马达4进行交流驱动，具有包含升压电路的电源部1、逆变器输出电路2、以及在电源部1与逆变器输出电路2之间并联地配置的电容器3。此外，电容器3是平滑用电容器，为了抑制电源部(升压电路)1的噪声的影响而形成恒定的电源电压来配备。
逆变器输出电路2采用将串联连接的上下臂11～16以三相并联连接而成的构成，将上臂11、13、15与下臂12、14、16的中间电位向三相马达4的U相、V相、W相的各相依次切换着施加。上下臂11～16分别具备IGBT元件11a～16a以及FWD(续流二极管)元件11b～16b，通过对各相的上下臂11～16的IGBT元件11a～16a进行接通、断开控制，从而对三相马达4供给周期不同的三相的交流电流。
在本实施方式中，在将构成逆变器输出电路2中的U相、V相、W相的各层的上下臂11～16的一对半导体芯片(IGBT元件11a～16a以及FWD元件11b～16b)封装化成一个的2in1构造的半导体模块5中应用本公开的技术思想，使用3个半导体模块5构成了上述逆变器输出电路2。
接下来，参照图2以及图3说明本实施方式的半导体模块5的构成。此外，以下，列举构成上述逆变器输出电路2的U相的半导体模块5为例进行说明，但构成V相、W相的半导体模块5也被设为相同的构成。
半导体模块5如图2以及图3所示，设为2个半导体芯片21a、21b、主端子22～24、控制端子25a、25b～29a、29b、下侧散热片30a、30b、上侧散热片31a、31b等利用模制树脂32一体化而成的构造。此外，在图2中，为了容易理解模制树脂32内的构成，用虚线示出了模制树脂32。
半导体芯片21a形成有构成上臂11的元件，半导体芯片21b形成有构成下臂12的元件。以下，参照图4以及图5说明本实施方式的半导体芯片21a的具体的构成。此外，半导体芯片21b的构成与半导体芯片21a的构成共同，因此省略具体的说明。
半导体芯片21a如图4所示那样设为平面矩形状，具备单元区域41和包围单元区域41的周边区域42。
单元区域41在本实施方式中具有形成有IGBT元件11a的IGBT区域41a以及形成有FWD元件11b的FWD区域41b。换句话说，在本实施方式中，IGBT元件11a以及FWD元件11b形成于同一芯片内。此外，IGBT区域41a以及FWD区域41b在本实施方式中沿半导体基板50的一面50a的一方向(图4中纸面上下方向)延伸设置，并且在与延伸设置方向正交的方向上交替地形成。
如图5所示，单元区域41具有作为漂移层51发挥功能的N－型的共同的半导体基板50，在漂移层51上(半导体基板50的一面50a侧)形成有P型的基极层52。而且，以贯通基极层52到达漂移层51的方式形成有多个沟槽53，利用该沟槽53将基极层52分离为多个。
在本实施方式中，多个沟槽53分别形成于IGBT区域41a以及FWD区域41b，并沿半导体基板50的一面50a的面方向中的一方向(图5中纸面进深方向)以等间隔形成为条纹状。此外，多个沟槽53也可以使前端部引绕从而成为环状构造。另外，半导体基板50的一面50a也可以由基极层52中的与漂移层51相反的一侧的一面构成。
基极层52在IGBT区域41a中作为沟道区域发挥功能。而且，在作为沟道区域的基极层52(IGBT区域41a的基极层52)形成有N+型的发射极区域54、以及被发射极区域54夹住的P+型的主体区域55。
发射极区域54与漂移层51相比以高杂质浓度构成，在基极层52内终结，并且以与沟槽53的侧面接触的方式形成。另一方面，主体区域55与基极层52相比以高杂质浓度构成，与发射极区域54相同地以在基极层52内终结的方式形成。
更详细地讲，发射极区域54在沟槽53间的区域中沿着沟槽53的长度方向以与沟槽53的侧面接触的方式以棒状延伸设置，构成为比沟槽53的前端靠内侧终结的构造。另外，主体区域55被两个发射极区域54夹住并沿着沟槽53的长度方向(换句话说是发射极区域54)以棒状延伸设置。此外，本实施方式的主体区域55以半导体基板50的一面50a为基准比发射极区域54更深地形成。
另外，各沟槽53内通过以覆盖各沟槽53的壁面的方式形成的栅极绝缘膜56、及形成在该栅极绝缘膜56上的多晶硅等构成的栅极电极57被埋入。由此，构成了沟槽栅极构造。
在基极层52(半导体基板50的一面50a)上形成有由BPSG等构成的层间绝缘膜58。而且，在层间绝缘膜58上，在IGBT区域41a形成有使发射极区域54的一部分以及主体区域55露出的接触孔58a。另外，在FWD区域41b形成使基极层52露出的接触孔58b。
在层间绝缘膜58上形成有上部电极59。该上部电极59在IGBT区域41a经由接触孔58a而与发射极区域54以及主体区域55电连接，在FWD区域41b经由接触孔58b而与基极层52电连接。换句话说，上部电极59在IGBT区域41a中作为发射极电极发挥功能，在FWD区域41b中作为阳极电极发挥功能。此外，在本实施方式中，上部电极59相当于第1主焊盘。
另外，在漂移层51中的与基极层52侧相反的一侧(半导体基板50的另一面50b侧)形成有N型的场截止(Field stop)层(以下简称为FS层)60。该FS层60并不是必须的，但为了通过防止耗尽层的扩散来实现耐压与稳定损失的性能提高、并且控制从半导体基板50的另一面50b侧注入的空穴的注入量控制而配备。
而且，在IGBT区域41a中，夹着FS层60而在与漂移层51相反的一侧形成有P型的集电极层61，在FWD区域41b中，夹着FS层60而在与漂移层51相反的一侧形成有N型的阴极层62。换句话说，IGBT区域41a与FWD区域41b根据在半导体基板50的另一面50b侧形成的层是集电极层61还是阴极层62来被划分。即，在本实施方式中，半导体基板50中集电极层61上的部分设为构成IGBT元件11a的IGBT区域41a，阴极层62上的部分设为构成FWD元件11b的FWD区域41b。
在集电极层61以及阴极层62上(半导体基板50的另一面50b)形成有下部电极63。该下部电极63在IGBT区域41a中作为集电极电极发挥功能，在FWD区域41b中作为阴极电极发挥功能。此外，在本实施方式中，下部电极63相当于第2主焊盘。
而且，通过如上述那样构成，在FWD区域41b中构成将基极层52作为阳极，将漂移层51、FS层60、阴极层62作为阴极而成为PN结的FWD元件11b。
周边区域42虽然未特别图示，但为了能够实现耐压提高，在半导体基板50的表层部，以包围单元区域41的方式将环状的P型的势阱区域或多个P型的护环形成为多重环构造。
另外，在周边区域42，如图4所示，形成有栅极焊盘71、第1、第2开尔文发射极焊盘72a、72b、电流感测焊盘73、温度感测焊盘74、75。此外，在本实施方式中，栅极焊盘71相当于第1控制焊盘，第1、第2开尔文发射极焊盘72a、72b相当于第2控制焊盘。
栅极焊盘71是经由未图示的栅极布线与栅极电极57电连接的外部连接用的焊盘。第1、第2开尔文发射极焊盘72a、72b是经由未图示的开尔文发射极布线与发射极区域54电连接的外部连接用的焊盘。电流感测焊盘73是与发射极区域54电连接的外部连接用的焊盘。温度感测焊盘74、75是与形成于半导体基板50上的温度检测元件(省略图示)电连接的外部连接用的焊盘。
而且，这些各焊盘71～75沿构成半导体芯片21a的外形的一边(在图4中是纸面下侧的一边)相邻地排列配置。在本实施方式中，从图4中纸面左侧起依次配置有温度感测焊盘74、75、第1开尔文发射极焊盘72a、栅极焊盘71、电流感测焊盘73、第2开尔文发射极焊盘72b。换句话说，以夹着栅极焊盘71的方式配置有第1、第2开尔文发射极焊盘72a、72b。
以上是本实施方式中的半导体芯片21a的构成。此外，如上述那样，半导体芯片21b的构成也相同。
而且，如图2以及图3所示，上述半导体芯片21a、21b分别经由焊料32等安装于下侧散热片30a、30b。另外，在半导体芯片21a、21b上经由焊料33等安装金属块34，在金属块34上经由焊料35等安装有上侧散热片31a、31b。由此，半导体芯片21a、21b中下部电极63分别与下侧散热片30a、30b连接，上部电极59分别与上侧散热片31a、31b连接。
主端子22～24分别设为平板状，具有正极端子22、输出端子23、负极端子24。正极端子22构成与逆变器中的电源供给线6(参照图1)连接的端子。而且，通过与上臂11侧的下侧散热片30a一体地连接，从而与半导体芯片21a中的背面侧即半导体芯片21a中的下部电极63电连接。
输出端子23在上臂11与下臂12之间构成与三相马达4连接的端子。而且，通过与下臂12侧的下侧散热片30b一体地连接，从而与半导体芯片21b中的背面侧即半导体芯片21b中的下部电极63电连接。
负极端子24构成与逆变器中的接地线7(参照图1)连接的端子。而且，通过与下臂12的上侧散热片31b一体地连接，从而与半导体芯片21b中的表面侧即半导体芯片21b中的上部电极59电连接。
而且，上侧散热片31a与下侧散热片30b通过中间部件36连接。由此，输出端子23成为上臂11与下臂12之间的中间电位。
另外，在本实施方式中，上述正极端子22、输出端子23、负极端子24在从相对于半导体芯片21a、21b的平面方向的法线方向(相对于半导体基板50的一面50a的法线方向)观察时，以相对于半导体芯片21a、21b向相同方向突出的方式延伸设置。而且，将负极端子24配置为位于正极端子22与输出端子23之间。换句话说，将正极端子22与负极端子24接近地配置。由此，抑制了电源供给线6与接地线7之间的寄生电容增加。
控制端子25a、25b～29a、29b分别设为平板状，并具有栅极端子25a、25b、开尔文发射极端子26a、26b、电流感测端子27a、27b、温度感测端子28a、28b、29a、29b。而且，各控制端子25a、25b～29a、29b隔着半导体芯片21a、21b地配置于与主端子22～24相反的一侧。
栅极端子25a、25b构成向栅极电极57(栅极焊盘71)施加规定电压的端子，并经由焊线37a而分别与形成于半导体芯片21a、21b的栅极焊盘71电连接。此外，在本实施方式中，栅极端子25a、25b相当于第1控制端子。
开尔文发射极端子26a、26b构成作为流向栅极端子25a、25b的控制电流的反馈电路发挥功能的端子。即，开尔文发射极端子26a、26b是与栅极端子25a、25b一起构成向栅极端子25a、25b施加电压时流过控制电流的电流路径的端子。
在本实施方式中，在上臂11侧，开尔文发射极端子26a经由焊线37b与第2开尔文发射极焊盘72b连接。另一方面，在下臂12侧，开尔文发射极端子26b经由焊线37b与第1开尔文发射极焊盘72a连接。换句话说，上臂11与下臂12的开尔文发射极端子26a、26b在以各半导体芯片21a、21b的栅极焊盘71为基准时与相互位于相反位置的开尔文发射极焊盘72a、72b连接。换言之，与半导体芯片21a连接的栅极端子25a以及开尔文发射极端子26a的排列、和与半导体芯片21b连接的栅极端子25b以及开尔文发射极端子26b的排列设为相反。这样将开尔文发射极端子26a、26b与第1、第2开尔文发射极焊盘72a、72b连接的理由参见后述。此外，在本实施方式中，开尔文发射极端子26a、26b相当于第2控制端子。
电流感测端子27a、27b构成用于取出流经各半导体芯片21a、21b的主电流的一部分来测定的端子，经由焊线37c而与电流感测焊盘73电连接。温度感测端子28a、29a、28b、29b构成与温度感测焊盘74、75连接的端子，经由焊线37d、37e而与温度感测焊盘74、75适当地电连接。
而且，半导体芯片21a、21b、主端子22～24、控制端子25a、25b～29a、29b、下侧散热片30a、30b、上侧散热片31a、31b等被模制树脂32密封而一体化。具体而言，半导体芯片21a、21b、主端子22～24、控制端子25a、25b～29a、29b、下侧散热片30a、30b、上侧散热片31a、31b等以下侧散热片30a、30b以及上侧散热片31a、31b中的与半导体芯片21a、21b侧相反的一侧露出、并且主端子22～24以及控制端子25a、25b～29a、29b的一部分露出的方式，被模制树脂32密封而一体化。由此，在下侧散热片30a、30b以及上侧散热片31a、31b中的从模制树脂32露出的部分，释放出半导体芯片21a、21b所产生的热量，在主端子22～24以及控制端子25a、25b～29a、29b中的从模制树脂32露出的部分，实现与外部电路的连接。
如以上说明那样，构成了本实施方式中的2in1构造的半导体模块5。接下来，参照图6A以及图6B说明上述半导体模块5的工作。
这样的半导体模块5向构成上臂11的半导体芯片21a的栅极焊盘71和构成下臂12的半导体芯片21b的栅极焊盘71，交替地施加用于使形成于各半导体芯片21a、21b的IGBT元件11a成为接通状态的电压。
此时，若构成上臂11的半导体芯片21a的栅极焊盘71被施加用于使IGBT元件11a成为接通状态的电压，则如图6A所示，主电流Ic1从正极端子22流向输出端子23。然后，由于该主电流Ic1流动，基于右手螺旋法则，产生从半导体芯片21a的表面侧向背面侧(图6A中纸面进深方向)通过控制端子25a～29a的主磁通Bo。
然后，由于产生该主磁通Bo，因此产生从半导体芯片21a的背面侧向表面侧(图6A中纸面跟前方向)通过的控制磁通Bg。因此，基于控制磁通Bg的控制电流Ic2从开尔文发射极端子26a流向栅极端子25a。换句话说，由于控制电流Ic2，半导体芯片21a的栅极焊盘71(栅极端子25a)的电位从使IGBT元件11a接通的一侧减少。因此，能够抑制半导体芯片21a的栅极焊盘71的电位上升进而IGBT元件11a误工作。
另一方面，若构成下臂12的半导体芯片21b的栅极焊盘71被施加用于使IGBT元件12a成为接通状态的电压，则如图6B所示，主电流Ic1从输出端子23流向负极端子24。然后，由于该主电流Ic1流动，基于右手螺旋法则，产生从半导体芯片21b的背面侧向表面侧(图6B中纸面跟前方向)通过控制端子25b～29b的主磁通Bo。
然后，由于产生该主磁通Bo，因此产生从半导体芯片21b的表面侧向背面侧(图6B中纸面进深方向)通过的控制磁通Bg。因此，基于控制磁通Bg的控制电流Ic2从开尔文发射极端子26b流向栅极端子25b。换句话说，由于控制电流Ic2，半导体芯片21b的栅极焊盘71(栅极端子25b)的电位从使IGBT元件12a接通的一侧减少。因此，能够抑制半导体芯片21b的栅极焊盘71的电位上升进而IGBT元件12a误工作。
即，在本实施方式中，也可以说是开尔文发射极端子26a、26b以使控制电流Ic2从开尔文发射极端子26a、26b流向栅极端子25a、25b的方式与第1、第2开尔文发射极焊盘72a、72b中的某一方连接。
如以上说明那样，在本实施方式中，在半导体芯片21a、21b中以夹着栅极焊盘71的方式配备有第1、第2开尔文发射极焊盘72a、72b。因此，能够将开尔文发射极端子26a、26b与第1、第2开尔文发射极焊盘72a、72b中的某一方连接。即，如上述那样构成了半导体模块5的情况下，能够将开尔文发射极端子26a、26b与在上臂11与下臂12中不同的开尔文发射极焊盘72a、72b连接，以使在上臂11以及下臂12中产生的控制电流Ic2分别从开尔文发射极端子26a、26b流向栅极端子25a、25b。因此，在上臂11以及下臂12中，能够利用控制电流Ic2抑制栅极端子25a、25b(栅极焊盘71)的电位向使IGBT元件11a、12a接通的一侧增加，从而能够抑制IGBT元件11a、12a误工作。
(第2实施方式)
对第2实施方式进行说明。本实施方式相对于第1实施方式，在半导体芯片21a、21b配备一个开尔文发射极焊盘72，并且以夹着该开尔文发射极焊盘72的方式配备2个栅极焊盘71，关于其他与第1实施方式相同，因此这里省略说明。
在本实施方式中，如图7所示，半导体芯片21a仅配备有一个开尔文发射极焊盘72。而且，以夹着该开尔文发射极焊盘72的方式配备有第1、第2栅极焊盘71a、71b。此外，半导体芯片21b的构成与半导体芯片21a的构成相同。
作为这样的半导体芯片21a、21b，也是在构成上述第1实施方式的半导体模块5时，通过将栅极端子25a、25b与第1、第2栅极焊盘71a、71b中的某一方适当地连接，能够使控制电流Ic2从开尔文发射极端子26a、26b流向栅极端子25a、25b。因此，能够获得与上述第1实施方式相同的效果。
(第3实施方式)
对第3实施方式进行说明。本实施方式相对于第1实施方式，将IGBT元件11a、12a与FWD元件11b、12b形成于不同的芯片，关于其他与第1实施方式相同，因此这里省略说明。
在本实施方式中，如图8所示，在上臂11侧，IGBT元件11a形成于半导体芯片21a1，FWD元件11b形成于半导体芯片21a2。换句话说，IGBT元件11a与FWD元件11b形成于不同的半导体芯片。
同样，在下臂12侧，IGBT元件12a形成于半导体芯片21b1，FWD元件12b形成于半导体芯片21b2。此外，在半导体芯片21a1、21b1，分别与上述第1实施方式同样地形成有栅极焊盘71、第1、第2开尔文发射极焊盘72a、72b、电流感测焊盘73、温度感测焊盘74、75。
这样，即使采用将IGBT元件11a、12a与FWD元件11b、12b形成于不同芯片的半导体模块5，也能够获得与第1实施方式相同的效果。
(其他实施方式)
实施方式并不限定于上述实施方式。以下，例示出其他实施方式。
例如，在上述各实施方式中，说明了构成各相的上下臂11～16的一对半导体芯片21a、21b模块化成一个的2in1构造的半导体模块5。然而，半导体模块5的构成并不限定于此，例如，可以是构成各相的所有上下臂11～16的半导体芯片21a、21b利用模制树脂32一体化而成的6in1构造的半导体模块5，也可以是构成2个相的电桥电路的半导体芯片21a、21b利用模制树脂32一体化而成的4in1构造的半导体模块5。
另外，在上述各实施方式中，列举形成有IGBT元件11a～16a的半导体芯片21a、21b为例进行了说明，但也可以采用例如形成有不具有集电极层61的MOS元件的半导体芯片21a、21b。
并且，在上述第1、第3实施方式中，在第1、第2开尔文发射极焊盘72a、72b之间配备有栅极焊盘71以及电流感测焊盘73，但只要在第1、第2开尔文发射极焊盘72a、72b之间配备有栅极焊盘71，就可以适当地变更电流感测焊盘73、第1、第2温度感测焊盘74、75的配置位置。同样，在上述第2实施方式中，只要在第1、第2栅极焊盘71a、71b之间配备有开尔文发射极焊盘72，就可以适当地变更电流感测焊盘73、第1、第2温度感测焊盘74、75的配置位置。
另外，在上述第1、第2实施方式中，也可以采用不具备FWD元件11b～16b的构成。

Claims (3)

1.一种半导体芯片，具备：
多个焊盘(71、72)；以及
开关元件(11a～16a)，具有栅极电极(57)，
上述多个焊盘具有：
第1控制焊盘(71)，与上述栅极电极电连接，被施加控制上述开关元件的接通、断开的电压；以及
第2控制焊盘(72)，在上述开关元件接通时，在与上述第1控制焊盘之间构成供控制电流流过的电流路径，
上述第1控制焊盘以及上述第2控制焊盘中的某一方的控制焊盘被配置成被另一方的控制焊盘夹着。
2.一种半导体模块，具备：
构成上臂的第1半导体芯片(21a)，形成有具有栅极电极(57)的开关元件(11a、13a、15a)，在表面形成有第1主焊盘(59)，并且相邻地形成有多个控制焊盘(71、72)，在背面形成有第2主焊盘(63)；
构成下臂的第2半导体芯片(21b)，形成有具有栅极电极(57)的开关元件(12a、14a、16a)，并且被设为与上述第1半导体芯片相同的结构，与上述第1半导体芯片相邻地配置；
正极端子(22)，与上述第1半导体芯片的第2主焊盘电连接；
负极端子(24)，与上述第2半导体芯片的第1主焊盘电连接；
输出端子(23)，与上述第1半导体芯片的第1主焊盘以及上述第2半导体芯片的第2主焊盘电连接，从而成为上述上臂以及上述下臂的中间电位；以及
多个控制端子(25a、25b、26a、26b)，与上述多个控制焊盘连接，
在从相对于上述第1半导体芯片以及上述第2半导体芯片的表面的法线方向观察时，上述正极端子、上述负极端子、上述输出端子相对于上述第1半导体芯片以及第2半导体芯片向相同方向延伸设置，并且在上述正极端子与上述输出端子之间配置有上述负极端子，
上述多个控制焊盘具有：
第1控制焊盘(71)，与上述栅极电极电连接，被施加控制上述开关元件的接通、断开的电压；以及
第2控制焊盘(72)，在上述开关元件接通时，在与上述第1控制焊盘之间构成供控制电流流过的电流路径，
上述第1控制焊盘以及上述第2控制焊盘中的某一方的控制焊盘被配置成被另一方的控制焊盘夹着，
上述控制端子具有与上述第1控制焊盘连接的第1控制端子以及与上述第2控制焊盘连接的第2控制端子，
上述第1控制端子以及第2控制端子以使上述控制电流从上述第2控制端子流向上述第1控制端子的方式，与上述第1半导体芯片以及上述第2半导体芯片中的上述第1控制焊盘以及上述第2控制焊盘分别电连接。
3.如权利要求2所述的半导体模块，其中，
与上述第1半导体芯片连接的上述第1控制端子以及上述第2控制端子的排列，和与上述第2半导体芯片连接的上述第1控制端子以及上述第2控制端子的排列被设为相反。
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