CN107342283B - Transient Voltage Suppressor and preparation method thereof - Google Patents
Transient Voltage Suppressor and preparation method thereof Download PDFInfo
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- CN107342283B CN107342283B CN201710564682.2A CN201710564682A CN107342283B CN 107342283 B CN107342283 B CN 107342283B CN 201710564682 A CN201710564682 A CN 201710564682A CN 107342283 B CN107342283 B CN 107342283B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 58
- 238000002360 preparation method Methods 0.000 title abstract description 3
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000000926 separation method Methods 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 230000002457 bidirectional effect Effects 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 19
- 239000011229 interlayer Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of Transient Voltage Suppressor and preparation method thereof.The Transient Voltage Suppressor includes P type substrate, the p-type epitaxial layer being formed in the P type substrate, the p-type isolation well being formed in the p-type epitaxial layer, it is formed in the n-type doping region of the p-type epi-layer surface, and it is formed in the first P-doped zone domain and the second P-doped zone domain of the N-doped zone field surface, wherein first P-doped zone domain and second P-doped zone domain are located at the both ends in the n-type doping region, first P-doped zone domain and the n-type doping region form the first Zener diode, second P-doped zone domain and the n-type doping region form the second Zener diode.The Transient Voltage Suppressor has device area small, and technology difficulty is low, and manufacturing cost is low, protection feature and the higher advantage of reliability.
Description
Technical field
The present invention relates to semiconductor chip manufacturing technology fields, particularly, are related to a kind of Transient Voltage Suppressor and its system
Make method.
Background technique
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device, makes it from transient voltage surge
It destroys and specially designed solid-state semiconductor device, it has, and clamp coefficient is small, small in size, response is fast, leakage current is small and reliable
The advantages that property is high, thus be widely used on voltage transient and carrying out surge protection.Static discharge (ESD) and other one
The transient voltage that a little voltage surge forms occur at random, is typically found in various electronic devices.Increasingly with semiconductor devices
Tend to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to the influence of voltage surge, even results in fatal
Injury.Various voltage surges can induce transient current spikes from static discharge to lightning etc., and Transient Voltage Suppressor is usually used
To protect impact of the sensitive circuit by surge.Based on different applications, Transient Voltage Suppressor can be put by changing surge
Electric pathway and the clamping voltag of itself play the role of circuit protection.
Low capacitor transient stage voltage suppressor is suitable for the protection device of high-frequency circuit, because it can reduce parasitic capacitance pair
The interference of circuit reduces the decaying of high-frequency circuit signal.In order to improve the reverse characteristic of Transient Voltage Suppressor, improving device can
By property.Generally use protection ring structure and Metal field plate structure.But the additional capacitor that both structures introduce is big, and device
Area is big, reduces device and improves device manufacturing cost.
Summary of the invention
For the deficiency of existing method, a kind of low capacitor electrostatic protection Transient Voltage Suppressor is proposed, device is improved
Performance reduces device manufacturing cost.
A kind of Transient Voltage Suppressor comprising P type substrate, is formed the p-type epitaxial layer being formed in the P type substrate
P-type isolation well in the p-type epitaxial layer is formed in the n-type doping region of the p-type epi-layer surface and is formed in institute
State the first P-doped zone domain and the second P-doped zone domain of N-doped zone field surface, wherein first P-doped zone domain with
Second P-doped zone domain is located at the both ends in the n-type doping region, first P-doped zone domain and the n-type doping
Region forms the first Zener diode, and second P-doped zone domain and the n-type doping region form two pole of the second Zener
Pipe, first Zener diode and second Zener diode share the n-type doping region and make first Zener
Diode is docked with the second Zener diode cathode, and then there is the Transient Voltage Suppressor two-path bidirectional to protect function
Energy.
In one embodiment, the p-type isolation well and n-type doping region interval are arranged, the p-type isolation well
Through the p-type epitaxial layer and extends to the P type substrate and contacted with the P type substrate.
In one embodiment, the Transient Voltage Suppressor further includes being formed in the p-type epitaxial layer and the N-type
Inter-level dielectric on doped region, the first opening being formed through on the inter-level dielectric and the second opening, described first opens
First P-doped zone domain described in mouthful face, the second P-doped zone domain described in the second opening face.
In one embodiment, the third opening being formed through on the inter-level dielectric, the third opening face
The p-type isolation well.
In one embodiment, the Transient Voltage Suppressor further includes the first electricity being formed on the inter-level dielectric
Pole and second electrode, the first electrode and the second electrode are the Transient Voltage Suppressor for electric with external devices
The external electrode of connection, the first electrode is open respectively by described first and the third is open and mixes with first p-type
Miscellaneous region and p-type isolation well electrical connection, the second electrode pass through second opening and second P-doped zone domain
Electrical connection.
A kind of production method of Transient Voltage Suppressor comprising following steps:
P type substrate is provided, makes p-type epitaxial layer in the P type substrate, forms separation layer in the p-type epi-layer surface；
Using the first photoresist as exposure mask, the separation layer is etched using dry/wet and forms the first injection window, is gone
Except first photoresist；
P-type ion is carried out by the first injection window to inject to form p-type isolation well；
Using the second photoresist as exposure mask, the separation layer is etched using dry/wet and forms the second injection window, is gone
Except second photoresist, N-type ion is carried out in the p-type epi-layer surface by the second injection window and injects to form N
Type doped region；
Wet etching removes the separation layer, in the p-type isolation well, the p-type epitaxial layer and the n-type doping region
Surface forms inter-level dielectric；And
Using third photoresist as exposure mask, inter-level dielectric described in dry etching forms the first opening, the second opening, wherein
First opening, second opening corresponds to the n-type doping region, is open by described first and described second is open
P-type ion is carried out to the n-type doping region to inject to form the first P-doped zone domain and the second P-doped zone domain；
Wherein first P-doped zone domain and second P-doped zone domain are located at the two of the n-type doping region
End, first P-doped zone domain and the n-type doping region form the first Zener diode, second P-doped zone domain
The second Zener diode is formed with the n-type doping region, first Zener diode and second Zener diode are total
With the n-type doping region first Zener diode is docked with the second Zener diode cathode, and then described
Transient Voltage Suppressor has two-path bidirectional defencive function.
In one embodiment, the material of the separation layer is silica, and separation layer passes through to the p-type extension
The surface of layer carries out thermal oxide and is formed.
In one embodiment, the p-type isolation well through the p-type epitaxial layer and extends in the P type substrate
It is contacted with the P type substrate.
In one embodiment, described using third photoresist as exposure mask, inter-level dielectric described in dry etching is formed
In the step of first opening, the second opening, inter-level dielectric described in dry etching also forms third opening, and the third opening corresponds to
The p-type isolation well.
In one embodiment, the production method is further comprising the steps of:
Metal layer is formed on the inter-level dielectric, uses the 4th photoresist as exposure mask, metal layer described in dry etching
Form first electrode and second electrode, the first electrode and the second electrode be the Transient Voltage Suppressor for
External devices electrical connection external electrode, the first electrode respectively by described first be open and the third opening with it is described
First P-doped zone domain and p-type isolation well electrical connection, the second electrode pass through second opening and the 2nd P
The electrical connection of type doped region, removes the 4th photoresist.
Compared to the prior art, the invention proposes a kind of low capacitor electrostatic protection Transient Voltage Suppressor and its production sides
Method is integrated together two Zener diodes by process modification, device area on the basis of traditional Transient Voltage Suppressor
Small, technology difficulty is low, reduces device manufacturing cost.Improved Transient Voltage Suppressor is able to achieve two-path bidirectional protection function
Can, the protection feature and reliability of device are all improved.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure, in which:
Fig. 1 is the structural schematic diagram of Transient Voltage Suppressor of the present invention.
Fig. 2 is the schematic equivalent circuit of Transient Voltage Suppressor shown in Fig. 1.
Fig. 3 is the flow chart of the production method of Transient Voltage Suppressor shown in Fig. 1.
Fig. 4-Figure 10 is the structural schematic diagram of each step of production method shown in Fig. 3.
Main element symbol description:
Transient Voltage Suppressor 100；P type substrate 101；P-type epitaxial layer 102；P-type isolation well 103；N-type doping region
104；First P-doped zone domain 105；Second P-doped zone domain 106；N-type doping region 104；Inter-level dielectric 107；First electrode
108；Second electrode 109；First opening 107a；Second opening 107b；Third opening 107c；First Zener diode 100a；The
Two Zener diode 100b；Separation layer 111；First injection window 112；Second injection window 113.
Specific embodiment
The technical scheme in the embodiments of the invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
Big to solve prior art Transient Voltage Suppressor area, technology difficulty is high, and the technologies such as device manufacturing cost height are asked
Topic, the present invention provide a kind of improved Transient Voltage Suppressor, please refer to Fig. 1 and Fig. 2, and Fig. 1 is transient voltage suppression of the present invention
The structural schematic diagram of device 100 processed, Fig. 2 are the schematic equivalent circuits of Transient Voltage Suppressor 100 shown in Fig. 1.The transient state electricity
Pressure suppressor 100 includes P type substrate 101, the p-type epitaxial layer 102 being formed in the P type substrate 101, outside the p-type
Prolong layer 102 and extend to the p-type isolation well 103 of the P type substrate 101, be formed in 102 surface of p-type epitaxial layer and with institute
The first p-type stated the spaced n-type doping region 104 of p-type isolation well 103, be formed in 104 surface of n-type doping region
Doped region 105 and the second P-doped zone domain 106 are formed on the p-type epitaxial layer 102 and the n-type doping region 104
Inter-level dielectric 107 and the first electrode 108 that is formed on the inter-level dielectric 107 and second electrode 109.
The first opening 107a, the second opening 107b and third opening 107c being formed through on the inter-level dielectric 107,
It is described first opening 107a face described in the first P-doped zone domain 105, it is described second opening 107b face described in the second p-type mix
P-type isolation well 103 described in third opening 107c face is stated in miscellaneous region 106.The first electrode 108 and the second electrode 109
For the external electrode for being electrically connected with external devices of the Transient Voltage Suppressor 100, the first electrode 108 is led to respectively
Cross the first opening 107a and third opening 107c and first P-doped zone domain 105 and the p-type isolation well
103 electrical connections, the second electrode 109 are electrically connected by the second opening 107b with second P-doped zone domain 106.
Wherein, first P-doped zone domain 105 and second P-doped zone domain 106 are located at the N-doped zone
The both ends in domain 104, first P-doped zone domain 105 and the n-type doping region 104 form the first Zener diode 100a,
Second P-doped zone domain 106 and the n-type doping region 104 form the second Zener diode 100b, first Zener
Diode 100a and the second Zener diode 100b shares the n-type doping region 104 and makes two pole of the first Zener
Pipe 100a is docked with the second Zener diode 100b cathode, and then the Transient Voltage Suppressor 100 has two-path bidirectional
Defencive function.
Fig. 3-Figure 10 is please referred to, Fig. 3 is the flow chart of the production method of Transient Voltage Suppressor 100 shown in Fig. 1, Fig. 4-figure
10 be the structural schematic diagram of each step of production method shown in Fig. 3.The production method of the Transient Voltage Suppressor 100 include with
Lower step S1~S7.
Step S1 makes p-type epitaxial layer 102 referring to Fig. 4, providing P type substrate 101 in the P type substrate 101,
102 surface of p-type epitaxial layer forms separation layer 111.The P type substrate 101 is P-type wafer, in the P type substrate 101
It carries out being epitaxially-formed the p-type epitaxial layer 102.Further, the material of the separation layer 111 can be oxide layer, such as
Silica SiO2, specifically, in present embodiment, the separation layer 111 of the SiO2 can be by the p-type epitaxial layer
102 upper surface carries out thermal oxide and is formed.
Step S2, referring to Fig. 5, etching the separation layer using dry/wet using the first photoresist as exposure mask
111 form the first injection window 112, remove first photoresist.
Step S3, referring to Fig. 6, by it is described first injection window 112 carry out P-type ion inject to be formed the p-type every
From trap 103.Wherein the P-type ion is injected in the p-type epitaxial layer 102 and the P type substrate 101 by thermal diffusion to shape
At the p-type isolation well 103, it will be understood that the p-type isolation well 103 is through the p-type epitaxial layer 102 and extends to the P
It is contacted in type substrate 101 with the P type substrate 101.
Step S4, referring to Fig. 7, etching the separation layer using dry/wet using the second photoresist as exposure mask
111 form the second injection window 113, remove second photoresist, through the second injection window 113 outside the p-type
Prolong 102 surface of layer progress N-type ion to inject to form n-type doping region 104.
Step S5, referring to Fig. 8, wet etching removes the separation layer 111, in the p-type isolation well 103, the p-type
Epitaxial layer 102 and 104 surface of n-type doping region form inter-level dielectric 107.
Step S6, referring to Fig. 9, using third photoresist as exposure mask, inter-level dielectric 107 described in dry etching forms the
One opening 107a, the second opening 107b and third opening 107c, wherein the second opening 107b described in the first opening 107a is equal
The corresponding n-type doping region 104, the third opening 107c correspond to the p-type isolation well 103, are open by described first
107a and the second opening 107b carry out P-type ion to the n-type doping region 104 and inject to form the first P-doped zone domain
105 and the second P-doped zone domain 106.
Step S7 uses the 4th photoresist as covering referring to Fig. 10, form metal layer on the inter-level dielectric 107
Film, metal layer described in dry etching form first electrode 108 and second electrode 109, the first electrode 108 and second electricity
Pole 109 is the external electrode for being electrically connected with external devices of the Transient Voltage Suppressor 100, the first electrode 108
Respectively by the first opening 107a and the third be open 107c and first P-doped zone domain 105 and the p-type every
It is electrically connected from trap 103, the second electrode 109 is electrically connected by the second opening 107b with second P-doped zone domain 106
It connects, the 4th photoresist is removed, to complete the production of the Transient Voltage Suppressor 100.
Compared to the prior art, the invention proposes a kind of low capacitor electrostatic protection Transient Voltage Suppressor 100 and its systems
Make method, on the basis of traditional Transient Voltage Suppressor, is integrated into two Zener diodes 100a, 100b by process modification
Together, device area is small, and technology difficulty is low, reduces device manufacturing cost.Improved Transient Voltage Suppressor 100 is able to achieve
Two-path bidirectional defencive function, the protection feature and reliability of device are all improved.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to protection model of the invention
It encloses.
Claims (5)
1. a kind of production method of Transient Voltage Suppressor, it is characterised in that: the Transient Voltage Suppressor include P type substrate,
The p-type epitaxial layer that is formed in the P type substrate, is formed in the p-type at the p-type isolation well being formed in the p-type epitaxial layer
The n-type doping region of epi-layer surface and the first P-doped zone domain and the second p-type for being formed in the N-doped zone field surface
Doped region, wherein first P-doped zone domain and second P-doped zone domain are located at the two of the n-type doping region
End, first P-doped zone domain and the n-type doping region form the first Zener diode, second P-doped zone domain
The second Zener diode is formed with the n-type doping region, first Zener diode and second Zener diode are total
With the n-type doping region first Zener diode is docked with the second Zener diode cathode, and then described
Transient Voltage Suppressor has two-path bidirectional defencive function, and the p-type isolation well and n-type doping region interval are arranged, institute
P-type isolation well is stated through the p-type epitaxial layer and extends to the P type substrate and is contacted with the P type substrate, the transient voltage
Suppressor further includes the inter-level dielectric being formed on the p-type epitaxial layer and the n-type doping region, shape on the inter-level dielectric
At having perforative first opening and the second opening, the first P-doped zone domain described in the first opening face, described second is open
Second P-doped zone domain described in face, the third opening being formed through on the inter-level dielectric, the third are open face institute
P-type isolation well is stated, the Transient Voltage Suppressor further includes the first electrode and second electrode being formed on the inter-level dielectric,
The first electrode is the external electricity for being electrically connected with external devices of the Transient Voltage Suppressor with the second electrode
Pole, the first electrode is open respectively by described first and the third is open and first P-doped zone domain and the P
The electrical connection of type isolation well, the second electrode are electrically connected by second opening with second P-doped zone domain；
The production method of its Transient Voltage Suppressor, includes the following steps:
P type substrate is provided, makes p-type epitaxial layer in the P type substrate, forms separation layer in the p-type epi-layer surface；
Using the first photoresist as exposure mask, the separation layer is etched using dry/wet and forms the first injection window, removes institute
State the first photoresist；
P-type ion is carried out by the first injection window to inject to form p-type isolation well；
Using the second photoresist as exposure mask, the separation layer is etched using dry/wet and forms the second injection window, removes institute
The second photoresist is stated, carries out N-type ion and inject forming N-type and mixing in the p-type epi-layer surface by the second injection window
Miscellaneous region；
Wet etching removes the separation layer, in the p-type isolation well, the p-type epitaxial layer and the N-doped zone field surface
Form inter-level dielectric；And
Using third photoresist as exposure mask, inter-level dielectric described in dry etching forms the first opening, the second opening, wherein described
First opening, second opening corresponds to the n-type doping region, is open by described first and second opening is to institute
N-type doping region progress P-type ion is stated to inject to form the first P-doped zone domain and the second P-doped zone domain；
Wherein first P-doped zone domain and second P-doped zone domain are located at the both ends in the n-type doping region, institute
It states the first P-doped zone domain and the n-type doping region and forms the first Zener diode, second P-doped zone domain and institute
It states n-type doping region and forms the second Zener diode, first Zener diode and second Zener diode share institute
Stating n-type doping region docks first Zener diode with the second Zener diode cathode, and then the transient state
Voltage suppressor has two-path bidirectional defencive function.
2. the production method of Transient Voltage Suppressor as described in claim 1, it is characterised in that: the material of the separation layer is
Silica, and separation layer is formed and the surface to the p-type epitaxial layer carries out thermal oxide.
3. the production method of Transient Voltage Suppressor as described in claim 1, it is characterised in that: the p-type isolation well runs through
The p-type epitaxial layer and extending in the P type substrate is contacted with the P type substrate.
4. the production method of Transient Voltage Suppressor as described in claim 1, it is characterised in that: described to utilize third photoresist
As exposure mask, in the step of inter-level dielectric described in dry etching forms the first opening, the second opening, interlayer described in dry etching is situated between
Matter also forms third opening, the corresponding p-type isolation well of third opening.
5. the production method of Transient Voltage Suppressor as claimed in claim 4, it is characterised in that: the production method further includes
Following steps:
Metal layer is formed on the inter-level dielectric, uses the 4th photoresist as exposure mask, metal layer described in dry etching is formed
First electrode and second electrode, the first electrode and the second electrode are being used for and outside for the Transient Voltage Suppressor
The external electrode of device electrical connection, the first electrode is open respectively by described first and the third is open and described first
P-doped zone domain and p-type isolation well electrical connection, the second electrode are mixed by second opening with second p-type
Miscellaneous region electrical connection, removes the 4th photoresist.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147853A (en) * | 1997-09-29 | 2000-11-14 | Stmicroelectronics S.A. | Protection circuit that can be associated with a filter |
| CN1976028A (en) * | 2005-11-28 | 2007-06-06 | 株式会社东芝 | ESD protection element |
| CN104241274A (en) * | 2014-08-30 | 2014-12-24 | 电子科技大学 | Both-way ESD protection device based on transverse PNP structure |
| CN105261616A (en) * | 2015-09-22 | 2016-01-20 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method thereof |
| CN105551989A (en) * | 2014-10-24 | 2016-05-04 | 格罗方德半导体公司 | Integrated circuits with test structures including bi-directional protection diodes |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206680B (en) * | 2014-06-24 | 2018-09-11 | 比亚迪股份有限公司 | Bilateral transient voltage suppression diode and its manufacturing method |
-
2017
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147853A (en) * | 1997-09-29 | 2000-11-14 | Stmicroelectronics S.A. | Protection circuit that can be associated with a filter |
| CN1976028A (en) * | 2005-11-28 | 2007-06-06 | 株式会社东芝 | ESD protection element |
| CN104241274A (en) * | 2014-08-30 | 2014-12-24 | 电子科技大学 | Both-way ESD protection device based on transverse PNP structure |
| CN105551989A (en) * | 2014-10-24 | 2016-05-04 | 格罗方德半导体公司 | Integrated circuits with test structures including bi-directional protection diodes |
| CN105261616A (en) * | 2015-09-22 | 2016-01-20 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method thereof |
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