CN107256826B - 为多层多晶硅制作层间绝缘层的方法 - Google Patents

为多层多晶硅制作层间绝缘层的方法 Download PDF

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CN107256826B
CN107256826B CN201710570320.4A CN201710570320A CN107256826B CN 107256826 B CN107256826 B CN 107256826B CN 201710570320 A CN201710570320 A CN 201710570320A CN 107256826 B CN107256826 B CN 107256826B
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向鹏飞
雷仁方
杨修伟
曲鹏程
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Abstract

本发明公开了一种为多层多晶硅制作层间绝缘层的方法，具体步骤为：1）在多晶硅表面形成多晶硅氧化层；2）在氮化硅衬底上侧面上淀积修复层，所述修复层将多晶硅氧化层和氮化硅衬底上侧面的裸露区域全部覆盖；3）进行初次刻蚀，对修复层进行刻蚀，刻蚀后，所述裸露区域表面仍保留有一定厚度的修复层；4）进行二次刻蚀，将所述裸露区域表面的修复层刻蚀掉，刻蚀后，多晶硅根部残留有修复层；所述多晶硅氧化层和残留在多晶硅根部的修复层即形成层间绝缘层；本发明的有益技术效果是：提出了一种为多层多晶硅制作层间绝缘层的方法，该方法能够对多晶硅氧化层的生长缺陷进行修复，从而得到质量符合要求的层间绝缘层。

Description

为多层多晶硅制作层间绝缘层的方法
技术领域
本发明涉及一种CCD制作工艺，尤其涉及一种为多层多晶硅制作层间绝缘层的方法。
背景技术
现有技术在制作CCD时，通常采用多层多晶硅布线结构，多层多晶硅之间用多晶硅氧化层作为层间绝缘层(也叫层间绝缘介质层)；不同层次多晶硅之间需要满足一定的击穿电压强度要求，击穿电压大小由层间绝缘层的质量决定，具体来说，层间绝缘层的厚度直接决定了击穿电压大小，层间绝缘层越厚，击穿电压就越高，但层间绝缘层也不能太厚，如果太厚又会影响到电荷信号的转移效率；根据现有理论可知，层间绝缘层的厚度一般以100nm～250nm为宜。
现有技术在制作层间绝缘层时，一般先制作出相应的多晶硅，然后采用热氧化工艺对器件进行处理，使多晶硅表面生长出多晶硅氧化层，多晶硅氧化层即形成层间绝缘层；存在的问题是：发明人将前述工艺用于氮化硅衬底的多层多晶硅布线结构制作时，制作出的器件的层间击穿电压仅有12V～18V(行业标准一般要求层间击穿电压要大于40V)；发明人就前述问题进行了大量研究，在研究过程中发现，造成器件层间击穿电压过低的原因是：由于氮化硅表面无法进行热氧化生长，在多晶硅根部(也即多晶硅下部与氮化硅的连接部位)，多晶硅的氧化速率很低，当生长在多晶硅上部和侧壁的多晶硅氧化层的厚度已达到设计要求时，生长在多晶硅根部的多晶硅氧化层的厚度却还无法满足要求，于是就导致了器件的层间击穿电压过低。
发明内容
针对背景技术中的问题，本发明提出了一种为多层多晶硅制作层间绝缘层的方法，包括氮化硅衬底和层叠在氮化硅衬底上侧面上的多层多晶硅，在层叠方向上相邻的两层多晶硅之间设置有层间绝缘层；其创新在于：按如下方法制作层间绝缘层：1)采用热氧化工艺，在多晶硅表面形成多晶硅氧化层；2)采用化学气相沉积工艺，在氮化硅衬底上侧面上淀积修复层，所述修复层将多晶硅氧化层和氮化硅衬底上侧面的裸露区域全部覆盖；3)采用干法刻蚀工艺，对修复层进行刻蚀，刻蚀后，所述裸露区域表面仍保留有一定厚度的修复层；4)采用湿法刻蚀工艺，将所述裸露区域表面的修复层刻蚀掉，刻蚀后，多晶硅根部残留有修复层；所述多晶硅氧化层和残留在多晶硅根部的修复层即形成层间绝缘层；所述修复层的材质为未掺杂的硅酸盐玻璃(未掺杂的硅酸盐玻璃的英文为Undoped SilicateGlass，其缩写为USG，这种材料是本领域中的一种常见材料，也常用于制作绝缘层，但未见作“修复”用途的应用)。
本发明的原理是：多晶硅在氮化硅衬底上的热氧化生长特点是无法改变的，并且当多晶硅上部和侧壁的多晶硅氧化层的厚度达到设计要求后，考虑到其他制约条件，不可能再让多晶硅氧化层继续生长，于是发明人考虑对多晶硅根部的多晶硅氧化层进行修复(这也是本发明将相应结构定义为修复层的原因)，以使多晶硅根部的层间绝缘层厚度满足设计要求；为达到修复目的，本发明先采用化学气相沉积工艺淀积修复层，然后再用刻蚀工艺对修复层进行刻蚀；基于现有理论可知，化学气相沉积工艺具有填充能力强的特点，这就使得修复层能够将多晶硅根部位置处的多晶硅氧化层与氮化硅衬底之间的缝隙全部填充，不留空隙；基于现有技术可知，采用现有刻蚀工艺进行刻蚀操作时，只要不是过度刻蚀，在结构体的转角位置，总会有一定的残留，这是现有刻蚀工艺的缺点，但这也恰恰是本发明得以实现的关键：修复层被刻蚀后，多晶硅根部位置处的修复层无法被刻蚀干净，残留在多晶硅根部的修复层就对多晶硅根部较薄的多晶硅氧化层起到了修复效果，使多晶硅根部能够形成厚度满足要求的层间绝缘层；具体刻蚀时，本发明采用了两种刻蚀工艺分步进行刻蚀，其原因是：为提高操作效率，先采用刻蚀速度较快的干法刻蚀来使修复层被快速减薄，但由于干法刻蚀的速度较快，刻蚀进度可控性较差，为避免损伤氮化硅衬底，因此在干法刻蚀时，并未将氮化硅衬底裸露区域表面的修复层完全刻蚀掉，之后再采用可控性较好的湿法刻蚀工艺来将氮化硅衬底裸露区域表面剩余的修复层完全刻蚀掉；采用本发明方案后，可以为形成在氮化硅衬底上的多层多晶硅制作出质量较好的层间绝缘层，保证器件的层间击穿电压满足要求；本发明所涉及的工艺均为CCD制作中常见的工艺，将他们用来制作层间绝缘层，工艺兼容性很好，技术难度较低；关于具体的工艺参数，本文虽未作详细介绍，但发明人认为，考虑到本发明已经清楚地揭示了相关工作原理，以及考虑到各种工艺的常规性，具备本专业基本技能的本领域技术人员，在面对具体的器件时，应该是能够根据具体的器件参数，调试出相应的工艺参数的。
优选地，步骤3)中，保留在所述裸露区域表面的修复层厚度大于或等于50nm。
本发明的有益技术效果是：提出了一种为多层多晶硅制作层间绝缘层的方法，该方法能够对多晶硅氧化层的生长缺陷进行修复，从而得到质量符合要求的层间绝缘层。
附图说明
图1、采用热氧化工艺生长多晶硅氧化层时，多晶硅氧化层缺陷示意图(图中箭头所指部位，即为多晶硅氧化层厚度较薄位置)；
图2、淀积了修复层后，器件表面结构示意图；
图3、干法刻蚀后，器件表面结构示意图；
图4、湿法刻蚀后，器件表面结构示意图；
图中各个标记所对应的名称分别为：氮化硅衬底1、多晶硅2、多晶硅氧化层3、修复层4。
具体实施方式
一种为多层多晶硅制作层间绝缘层的方法，包括氮化硅衬底和层叠在氮化硅衬底上侧面上的多层多晶硅，在层叠方向上相邻的两层多晶硅之间设置有层间绝缘层；其创新在于：按如下方法制作层间绝缘层：1)采用热氧化工艺，在多晶硅表面形成多晶硅氧化层；2)采用化学气相沉积工艺，在氮化硅衬底上侧面上淀积修复层，所述修复层将多晶硅氧化层和氮化硅衬底上侧面的裸露区域全部覆盖；3)采用干法刻蚀工艺，对修复层进行刻蚀，刻蚀后，所述裸露区域表面仍保留有一定厚度的修复层；4)采用湿法刻蚀工艺，将所述裸露区域表面的修复层刻蚀掉，刻蚀后，多晶硅根部残留有修复层；所述多晶硅氧化层和残留在多晶硅根部的修复层即形成层间绝缘层；所述修复层的材质为未掺杂的硅酸盐玻璃。
进一步地，步骤3)中，保留在所述裸露区域表面的修复层厚度大于或等于50nm。
经实验验证，采用本发明方案后，多晶硅根部位置处的修复层和多晶硅氧化层的总厚度大约在150nm～200nm，完全可以满足要求。

Claims (2)

1.一种为多层多晶硅制作层间绝缘层的方法，包括氮化硅衬底和层叠在氮化硅衬底上侧面上的多层多晶硅，在层叠方向上相邻的两层多晶硅之间设置有层间绝缘层；其特征在于：按如下方法制作层间绝缘层：1）采用热氧化工艺，在多晶硅表面形成多晶硅氧化层；2）采用化学气相沉积工艺，在氮化硅衬底上侧面上淀积修复层，所述修复层将多晶硅氧化层和氮化硅衬底上侧面的裸露区域全部覆盖；3）采用干法刻蚀工艺，对修复层进行刻蚀，刻蚀后，所述裸露区域表面仍保留有一定厚度的修复层；4）采用湿法刻蚀工艺，将所述裸露区域表面的修复层刻蚀掉，刻蚀后，多晶硅氧化层根部残留有修复层；所述多晶硅氧化层和残留在多晶硅氧化层根部的修复层即形成层间绝缘层；所述修复层的材质为未掺杂的硅酸盐玻璃。
2.根据权利要求1所述的为多层多晶硅制作层间绝缘层的方法，其特征在于：步骤3）中，保留在所述裸露区域表面的修复层厚度大于或等于50nm。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044497A (zh) * 2009-10-13 2011-05-04 中芯国际集成电路制造(上海)有限公司 分立栅存储器件的形成方法
CN102082124A (zh) * 2009-12-01 2011-06-01 无锡华润上华半导体有限公司 多种器件集成工艺中栅极间隙壁的制造方法

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* Cited by examiner, † Cited by third party
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JP3788387B2 (ja) * 2002-05-10 2006-06-21 セイコーエプソン株式会社 電気光学装置および電気光学装置の製造方法
CN102087959B (zh) * 2009-12-04 2013-07-17 中芯国际集成电路制造(上海)有限公司 动态随机存取存储器及其电容器的制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044497A (zh) * 2009-10-13 2011-05-04 中芯国际集成电路制造(上海)有限公司 分立栅存储器件的形成方法
CN102082124A (zh) * 2009-12-01 2011-06-01 无锡华润上华半导体有限公司 多种器件集成工艺中栅极间隙壁的制造方法

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