CN106775869B - Loading method and terminal equipment - Google Patents
Loading method and terminal equipment Download PDFInfo
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- CN106775869B CN106775869B CN201611170822.XA CN201611170822A CN106775869B CN 106775869 B CN106775869 B CN 106775869B CN 201611170822 A CN201611170822 A CN 201611170822A CN 106775869 B CN106775869 B CN 106775869B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
- G06F9/4451—User profiles; Roaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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Abstract
The embodiment of the invention provides a loading method and terminal equipment, which are used for solving the technical problems of long time and low efficiency for loading an FPGA (field programmable gate array). The method comprises the following steps: determining that the terminal equipment is in a power-on state, and acquiring and loading a first configuration file related to an FPGA module in the terminal equipment in a first storage area; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area; determining that the first configuration file is successfully loaded, and receiving a second configuration file sent by a control device connected with the terminal device, wherein the second configuration file comprises at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a local reconstruction area; and determining that the second configuration file is loaded successfully, and starting the terminal equipment to enter a working state.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a loading method and a terminal device.
Background
Currently, the dynamic reconstruction technology of a Field-Programmable Gate Array (FPGA) is divided into a global reconstruction technology and a local reconstruction technology.
The FPGA global reconfiguration technology is to program the FPGA configuration pins through a configuration processing unit outside the FPGA to realize the switching of the whole FPGA content, and the method is widely applied at present. The FPGA local reconstruction technology realizes the switching of partial modules in the FPGA by time division multiplexing of partial resources in the FPGA through a configuration processing unit in or outside the FPGA.
At present, for military unmanned aerial vehicles, in order to prevent the unmanned aerial vehicle from being captured by an enemy and causing the leakage of an encryption algorithm and parameters, a power failure disappearance mode must be adopted. The conventional solution is to adopt an online loading method, which needs to write a complete FPGA configuration file into a configuration port through a serial port or a network port, and in this process, a bit stream file of the entire FPGA needs to be configured, resulting in a slow configuration speed, and after the configuration is completed, the entire FPGA is in an initial state, and the interface needs to be initialized again and corresponding operating parameters are configured, and meanwhile, since the global configuration hardly saves an intermediate result of the FPGA operation, if the unmanned aerial vehicle is externally connected with storage units such as DDR SDRAM, data confusion may also be caused by the reset of the interface.
In summary, in the prior art, the time required for configuring the FPGA online is long, and the efficiency is low.
Disclosure of Invention
The embodiment of the invention provides a loading method and terminal equipment, which are used for solving the technical problems of long time and low efficiency for loading an FPGA (field programmable gate array).
A loading method is applied to a terminal device and comprises the following steps:
determining that the terminal equipment is in a power-on state, and acquiring and loading a first configuration file related to a Field Programmable Gate Array (FPGA) module in the terminal equipment in a first storage area; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area;
determining that the first configuration file is successfully loaded, and receiving a second configuration file sent by a control device connected to the terminal device, where the second configuration file includes at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a local reconfiguration area;
and determining that the second configuration file is loaded successfully, and starting the terminal equipment to enter a working state.
Optionally, after determining that the first configuration file is successfully loaded, before receiving a second configuration file sent by a control device connected to the terminal device, the method further includes:
determining platform identification information corresponding to control equipment connected with the terminal equipment, and acquiring a platform interface configuration file corresponding to the platform identification information in the first storage area;
and configuring a third configuration area of the at least two configuration areas based on the platform interface configuration file, wherein the third configuration area is used for configuring a functional interface between the terminal device and the control device.
Optionally, after configuring a third configuration area of the at least two configuration areas based on the platform interface configuration file, the method further includes:
determining that the third configuration file is successfully loaded, and generating a feedback message;
sending the feedback message to the control device to receive the second configuration file fed back by the control device based on the feedback message.
Optionally, the method further includes:
receiving update information for the second profile and/or the third profile;
updating the third file in the terminal device and/or updating the second configuration file in the control device based on the updating information.
Optionally, before determining that the terminal device is in the power-on state, the method further includes:
determining a complete configuration file corresponding to a complete configuration area of an FPGA module of the control equipment;
dividing the complete configuration area into at least two configuration areas based on at least one preset condition; the at least one preset condition comprises that a configuration file of the configuration area is lost in power failure and/or the configuration file of the configuration area corresponds to the platform.
In another aspect, an embodiment of the present invention provides a terminal device, including:
the memory is used for storing a first configuration file related to an FPGA module in the terminal equipment; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area;
the processor is used for determining that the terminal equipment is in a power-on state, acquiring and loading a first configuration file related to a Field Programmable Gate Array (FPGA) module in the terminal equipment in a first storage area, receiving a second configuration file sent by control equipment connected with the terminal equipment if the first configuration file is determined to be loaded successfully, determining that the second configuration file is loaded successfully, and starting the terminal equipment to enter a working state; the second configuration file comprises at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a local reconstruction area.
Optionally, the processor is further configured to:
after the first configuration file is successfully loaded and before a second configuration file sent by control equipment connected with the terminal equipment is received, platform identification information corresponding to the control equipment connected with the terminal equipment is determined, and a platform interface configuration file corresponding to the platform identification information in the first storage area is obtained;
and configuring a third configuration area of the at least two configuration areas based on the platform interface configuration file, wherein the third configuration area is used for configuring a functional interface between the terminal device and the control device.
Optionally, the processor is further configured to:
after a third configuration area in the at least two configuration areas is configured based on the platform interface configuration file, determining that the third configuration file is loaded successfully, and generating a feedback message;
sending the feedback message to the control device to receive the second configuration file fed back by the control device based on the feedback message.
Optionally, the processor is further configured to:
receiving update information for the second profile and/or the third profile;
updating the third file in the terminal device and/or updating the second configuration file in the control device based on the updating information.
Optionally, the processor is further configured to:
before the terminal equipment is determined to be in a power-on state, determining a complete configuration file corresponding to a complete configuration area of an FPGA module of the control equipment;
dividing the complete configuration area into at least two configuration areas based on at least one preset condition; the at least one preset condition comprises that a configuration file of the configuration area is lost in power failure and/or the configuration file of the configuration area corresponds to the platform.
In the embodiment of the present invention, when it is determined that the terminal device is in the power-on state, the terminal device may obtain and load a first configuration file related to the FPGA module in a first storage area, where the first configuration file may configure a first configuration area of at least two configuration areas included in the FPGA module, where the first configuration area is a completely reconstructed area, and further determine that the first configuration file is successfully loaded, and may receive a second configuration file sent by a control device connected to the terminal device, where the second configuration file includes at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a locally reconstructed area in the FPGA module, and further after it is determined that the second configuration file is successfully loaded, the terminal device may be started to enter the working state, so that by partitioning the FPGA module in the terminal device and performing corresponding loading manners on different areas, the method and the device realize the loading in a mode of only loading the configuration file of the encrypted data needing to be protected on line, greatly reduce the size of the file compared with the size of the complete FPGA configuration file, and can effectively shorten the transmission time of the configuration file, thereby shortening the time from starting to normal work and improving the loading efficiency of the FPGA.
Drawings
Fig. 1 is a schematic structural diagram of a system in which a terminal device is located in an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a loading method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an FPGA loading process in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a terminal device in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First, some terms in the embodiments of the present invention are explained so as to be easily understood by those skilled in the art.
1) The terminal device refers to a device that needs to disappear after power failure of the protection code, such as a military unmanned aerial vehicle, a reconnaissance plane, and the like, and the embodiment of the present invention is not particularly limited thereto.
2) The control device is configured to configure and control the terminal device at the user side, for example, the control device may be a terminal, or the control device may also be a networking remote control unit, and may perform remote communication on the terminal device.
The network architecture to which the embodiments of the present invention are applied will be described with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a system structure applied to a loading method in an embodiment of the present invention, where an entity corresponding to the system may include a terminal device and a control device, where the terminal device mainly includes an FPGA module, a storage module, and a Digital Signal Processing (DSP) module, and all the modules are connected to each other; the control device may be a Personal Computer (PC), and the terminal device and the control device may be connected through a corresponding interface, for example, the DSP module may be connected to the control device through a network or a serial port, and the FPGA module may be connected to the control device through a Joint Test Action Group (JTAG) interface.
In the system architecture, an FPGA region is divided into three parts, namely a static logic region, a partial dynamic reconstruction region 1 and a partial dynamic reconstruction region 2. Wherein the static logic area may be used to store hardware logic that does not require protection and does not change from platform to platform; part of the dynamic reconfiguration area 1 can be used for storing encryption hardware logic needing to be protected; the partial dynamic reconfiguration region 2 may be used to store interface hardware logic that does not require protection but requires corresponding adjustments for different platforms.
In practical application, the FPGA portion may adopt a partial reconfiguration design based on modularization, in which the encryption module and the interface module are respectively configured as reconfigurable modules. For example, the bitstream to be configured may be classified by using a local reconstruction implementation tool and a Plan Ahead tool, and a static full bitstream file (e.g., static. bit in fig. 1), an encryption module partial bitstream file (e.g., dep. bit in fig. 1), and an interface partial bitstream file (e.g., IFS _1.bit to IFS _ n. bit in fig. 1) for different platforms are generated, respectively.
The technical solutions provided by the embodiments of the present invention are further described in detail below with reference to the drawings of the specification. The following description takes the system architecture shown in fig. 1 as an example.
As shown in fig. 2, an embodiment of the present invention discloses a loading method, which is applied to a terminal device and can be described as follows.
S11: determining that the terminal equipment is in a power-on state, and acquiring and loading a first configuration file related to an FPGA module in the terminal equipment in a first storage area; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area;
s12: determining that the first configuration file is successfully loaded, and receiving a second configuration file sent by a control device connected with the terminal device, wherein the second configuration file comprises at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a local reconstruction area;
s13: and determining that the second configuration file is loaded successfully, and starting the terminal equipment to enter a working state.
In the embodiment of the present invention, the terminal device may be an unmanned aerial vehicle product, and before the unmanned aerial vehicle is put into normal operation, the user usually performs online loading on the FPGA through the control device before the unmanned aerial vehicle is released, so as to better execute a corresponding task, and the control device may include a terminal computer or a handheld injector device at a terminal, and the like, which is not particularly limited in the example of the present invention.
Optionally, the terminal device may at least include the functional modules shown in fig. 1, such as a DSP module, a memory and an FPGA module, where the DSP module may be used to process data in the terminal device, and the first memory in the terminal device may be a Flash memory, for example, a Flash memory. In the unmanned aerial vehicle product, the Flash memory can be used for storing the bit stream file which does not need to disappear after power failure, and can also keep data for a long time under the condition of no current supply.
The terminal device can set the working state of the FPGA module by a program stored in a Random Access Memory (RAM), so that the RAM in the terminal device needs to be programmed when the terminal device is working, and a user can adopt different programming modes according to different configuration modes. Generally speaking, when a terminal device is powered on, an FPGA chip reads data in an Erasable Programmable Read Only Memory (EPROM) into an on-chip programming RAM, and after configuration is completed, the FPGA enters a working state; after power failure, the FPGA is recovered to be a white chip, and the internal logic relation disappears, so that the FPGA can be repeatedly used.
Optionally, when it is determined that the terminal device is in the power-on state, a first configuration file related to a first configuration area in the FPGA module may be obtained and loaded, where the first configuration area may be a static logic area divided for the FPGA module as in fig. 1, and the first configuration file may include static complete data configuring the first configuration area, that is, a static complete bitstream file (static.
In practical application, when the terminal device is powered on, the terminal device can read a static logic bit stream file (static. bit) from the Flash through the DSP, and completely configure the FPGA. Generally speaking, after loading a static complete bitstream file into a first configuration area of an FPGA, a communication interface between the FPGA and a control device in a terminal device is enabled.
In the embodiment of the present invention, the FPGA module of the terminal device may include at least two configuration areas, and the process of determining the at least two configuration areas may be determining a complete configuration file corresponding to the complete configuration area of the FPGA module of the control device, and further dividing the complete configuration area into the at least two configuration areas based on at least one preset condition, where the at least one preset condition includes power failure loss of the configuration file of the configuration area and/or correspondence between the configuration file of the configuration area and a platform. That is, when dividing the complete configuration area of the FPGA, the dividing standard mainly considers two points: firstly, whether the area requires power failure disappearance or not; secondly, whether the region code will be inconsistent due to different platforms.
In the dividing process, if it is determined that a certain area in the FPGA requires power failure disappearance, the certain area can be divided into a second configuration area, namely, the second configuration area is used for storing encryption hardware logic needing to be protected; if the area does not require power failure disappearance, the area can be determined to be a static logic area corresponding to static complete data, and further, whether the configuration file of the area is inconsistent due to different unmanned aerial vehicle platforms can be judged, and the area is divided into a third configuration area, namely a partial dynamic reconstruction area 2 for storing interface hardware logic which does not need protection but needs corresponding adjustment for different platforms.
In the embodiment of the invention, the terminal equipment is partitioned, the area for storing part of the bit stream file of the encryption module can be independently loaded online, and a large amount of static complete data can be loaded through static configuration, so that the time required by online configuration is reduced.
Optionally, after it is determined that the first configuration file is successfully loaded, S12 may be performed, the terminal device may obtain a second configuration file, where the second configuration file is a partial bit stream file (dep.bit) of the encryption module stored in the control end, and the second configuration area corresponds to the partial dynamic reconstruction area 1 in fig. 1, where the second configuration area is used to store secret data requiring power failure disappearance.
Optionally, before S12, platform identification information corresponding to the control device connected to the terminal device may be further determined, a platform interface configuration file corresponding to the platform identification information in the first storage area is acquired, and a third configuration area of the at least two configuration areas is configured based on the platform interface configuration file, where the third configuration area is used to configure a functional interface between the terminal device and the control device.
The third configuration area may correspond to the partial dynamic reconfiguration area 2 in fig. 1, and the platform identification information may be information capable of indicating a platform interface in the control device, and generally speaking, when the control device of a different platform is used to configure the terminal device, the FPGA of the terminal device needs to be configured according to the difference of the platforms.
In practical application, the platform parameter information corresponding to the device can be written into Flash of the control device through the control device, and after the control device is powered on, the platform parameter information can be read from Flash by the control device, that is, the bit stream file of the interface part of the corresponding platform can be selectively loaded, for example, the bit stream file is determined according to the platform identification information of the control device
In the embodiment of the present invention, when a user inputs an operation for configuring an FPGA of a terminal device in a control device, the control device may send platform identification information of the control device to a DSP of the terminal device, and the DSP may read a corresponding platform interface bitstream, that is, a third configuration file, in Flash based on the platform identification information, where the third configuration file may be one of IFS _1.bit to IFS _ n.bit stored in Flash shown in fig. 1, corresponding to a platform identification information, for example, IFS _1.bit or IFS _1.bit, and the like.
Optionally, the first configuration region divided by the FPGA module in the terminal device may be a complete reconfiguration region, and the second configuration region and the third configuration region may be local reconfiguration regions, or partial reconfiguration regions.
In practical application, if the control device corresponding to the terminal device is relatively fixed, the configuration platform corresponding to the FPGA is also relatively fixed, and then, when the terminal device is powered on, the platform interface may be loaded while the first configuration file in the first configuration area in the FPGA is loaded. For example, if the platform interface configuration file corresponding to the platform identification information of the control device is determined to be the IFS _3.bit, the IFS _3.bit in Flash can also be extracted to configure the partial dynamic reconfiguration area 2 when the static logic area of the FPGA is configured, so that the loading efficiency is improved.
In the embodiment of the invention, because the configuration files corresponding to the first configuration area and the second configuration area are both stored in the memory (namely Flash) connected with the FPGA in the terminal equipment, when the control equipment is powered on, the static complete bit stream file and the interface part bit stream file in the Flash can be read by the DSP, and the corresponding configuration areas are respectively configured.
Optionally, after configuring the corresponding platform interface bitstream file for the third configuration area, the terminal device may generate and send a feedback message to the control device, where the feedback message may be used to indicate that the terminal device has completed loading the platform interface configuration file and is currently in a state of waiting for receiving a partial bitstream file (dep.bit) of the encryption module.
In practical application, the feedback message may be regarded as a reply operation of the terminal device to the control device in the FPGA configuration process, and the reply operation may adopt a mode that the FPGA actively sends a ready instruction to the control device after loading the interface part bitstream file of the corresponding platform, and starts to receive and online load the encryption module part bitstream file acquired from the control device after the handshake is successful.
Therefore, after receiving the feedback message, the control device may determine that the terminal device is ready, and at this time, start to issue a second configuration file, that is, a partial bit stream file (dep) of the encryption module, the terminal device receives the second configuration file through the DSP, and performs online configuration on a partial dynamic reconfiguration region 1 in the FPGA module based on the second configuration file, and after all the configurations are completed, the terminal device may enter a normal operating mode. Fig. 3 shows a complete process of configuring an FPGA according to an embodiment of the present invention.
Optionally, update information sent from the control device is received, where the update information is used for updating information for the first configuration file and/or the third configuration file in the first storage area, and further, the control device may update the corresponding configuration file based on the update information. For example, the update information may be information for updating an interface partial bit stream file (IFS _ n.bit) in Flash of the control device, and the control device may write a corresponding sector of Flash through the user terminal based on the update information to update the partial file.
In addition, the second configuration file, namely the encryption module part bit stream file (dep.bit) from the control device can be upgraded independently, and since the encryption module part bit stream file (dep.bit) is stored in the control device, the user can perform upgrading operation at the control device.
In practical application, because the complete reconfiguration needs to configure the bit stream file of the whole FPGA, and the partial dynamic reconfigurable technology only needs to configure the logic content of the corresponding module, the sizes of the files are very different, and the configuration speed of the partial dynamic reconfigurable technology is one-tenth or one-tenth of the complete configuration under the same configuration clock frequency, the configuration speed is provided only by carrying out online loading on the second configuration area which needs to carry out power-down disappearance on data in the embodiment of the invention.
Meanwhile, after the complete reconfiguration is completed, the whole FPGA is in an initial state, and the interface needs to be initialized again and the operation parameters need to be configured. And partial dynamic reconfigurable technology does not need global reset, and parameter assignment only needs to be carried out aiming at the reconfigurable module, so that the process of resetting and parameter assignment after complete configuration is omitted.
In addition, the intermediate result of the FPGA operation is difficult to store through complete reconfiguration, if a DDR SDRAM and other storage units are externally connected, data confusion can also be caused due to the reset of the interface, and the intermediate result and the data of the FPGA operation can be stored through partial dynamic reconfigurable technology.
As shown in fig. 4, based on the same inventive concept, an embodiment of the present invention further provides a terminal device, which includes a memory 10 and a processor 20.
The memory 10 may be configured to store a first configuration file related to the FPGA module in the terminal device; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area.
The processor 20 may be configured to determine that the terminal device is in a powered-on state, obtain and load a first configuration file in a first storage area, where the first configuration file is related to a field programmable gate array FPGA module in the terminal device, receive a second configuration file sent by a control device connected to the terminal device if it is determined that the first configuration file is successfully loaded, determine that the second configuration file is successfully loaded, and start the terminal device to enter a working state; the second configuration file comprises at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a local reconstruction area.
In practical applications, the first memory may be a Flash memory in the terminal device, such as a Flash memory, and the processor 20 may be a DSP module with data processing capability in the terminal device, which may be used to configure an FPGA module in the terminal device, where an internal structure of the terminal device is also please refer to fig. 1 and corresponding description, which are not described herein again.
Optionally, the processor 20 may be further configured to determine, after it is determined that the first configuration file is successfully loaded and before receiving a second configuration file sent by a control device connected to the terminal device, platform identification information corresponding to the control device connected to the terminal device, and acquire a platform interface configuration file corresponding to the platform identification information in the first storage area;
and configuring a third configuration area of the at least two configuration areas based on the platform interface configuration file, wherein the third configuration area is used for configuring a functional interface between the terminal device and the control device.
Optionally, the processor 20 is further configured to:
after a third configuration area in the at least two configuration areas is configured based on the platform interface configuration file, determining that the third configuration file is loaded successfully, and generating a feedback message;
sending the feedback message to the control device to receive the second configuration file fed back by the control device based on the feedback message.
Optionally, the processor 20 is further configured to:
receiving update information for the second profile and/or the third profile;
updating the third file in the terminal device and/or updating the second configuration file in the control device based on the updating information.
Optionally, the processor 20 is further configured to:
before the terminal equipment is determined to be in a power-on state, determining a complete configuration file corresponding to a complete configuration area of an FPGA module of the control equipment;
dividing the complete configuration area into at least two configuration areas based on at least one preset condition; the at least one preset condition comprises that a configuration file of the configuration area is lost in power failure and/or the configuration file of the configuration area corresponds to the platform.
In the embodiment of the present invention, when it is determined that the terminal device is in the power-on state, the terminal device may obtain and load a first configuration file related to the FPGA module in a first storage area, where the first configuration file may configure a first configuration area of at least two configuration areas included in the FPGA module, where the first configuration area is a completely reconstructed area, and further determine that the first configuration file is successfully loaded, and may receive a second configuration file sent by a control device connected to the terminal device, where the second configuration file includes at least one secret data for configuring a second configuration area of the at least two configuration areas, and the second configuration area is a locally reconstructed area in the FPGA module, and further after it is determined that the second configuration file is successfully loaded, the terminal device may be started to enter the working state, so that by partitioning the FPGA module in the terminal device and performing corresponding loading manners on different areas, the method and the device realize the loading in a mode of only loading the configuration file of the encrypted data needing to be protected on line, greatly reduce the size of the file compared with the size of the complete FPGA configuration file, and can effectively shorten the transmission time of the configuration file, thereby shortening the time from starting to normal work and improving the loading efficiency of the FPGA.
The foregoing specific examples of the loading method in the embodiments of fig. 1 to fig. 3 are also applicable to the terminal device in this embodiment, and a person skilled in the art can clearly know the implementation method of the terminal device in this embodiment through the foregoing detailed description of the loading method, so that details are not described here for brevity of the description.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A loading method is applied to a terminal device, and is characterized by comprising the following steps:
determining that the terminal equipment is in a power-on state, and acquiring and loading a first configuration file related to a Field Programmable Gate Array (FPGA) module in the terminal equipment in a first storage area; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area;
determining that the first configuration file is successfully loaded, and receiving a second configuration file sent by a control device connected to the terminal device, where the second configuration file includes at least one secret data for configuring a second configuration area of the at least two configuration areas, where a loading manner of the secret data is online loading, and the second configuration area is a local reconfiguration area;
and determining that the second configuration file is loaded successfully, and starting the terminal equipment to enter a working state.
2. The method of claim 1, wherein after determining that the first configuration file is successfully loaded, and before receiving a second configuration file sent by a control device connected to the terminal device, the method further comprises:
determining platform identification information corresponding to control equipment connected with the terminal equipment, and acquiring a platform interface configuration file corresponding to the platform identification information in the first storage area;
and configuring a third configuration area of the at least two configuration areas based on the platform interface configuration file, wherein the third configuration area is used for configuring a functional interface between the terminal device and the control device.
3. The method of claim 2, after configuring a third configuration region of the at least two configuration regions based on the platform interface configuration file, further comprising:
determining that the third configuration file is successfully loaded, and generating a feedback message;
sending the feedback message to the control device to receive the second configuration file fed back by the control device based on the feedback message.
4. The method of claim 3, wherein the method further comprises:
receiving update information for the second profile and/or the third profile;
updating the third configuration file in the terminal device and/or updating the second configuration file in the control device based on the updating information.
5. The method of claim 1, wherein prior to determining that the terminal device is in a powered-on state, the method further comprises:
determining a complete configuration file corresponding to a complete configuration area of an FPGA module of the control equipment;
dividing the complete configuration area into at least two configuration areas based on at least one preset condition; the at least one preset condition comprises that a configuration file of the configuration area is lost in power failure and/or the configuration file of the configuration area corresponds to the platform.
6. A terminal device, comprising:
the memory is used for storing a first configuration file related to an FPGA module in the terminal equipment; the FPGA module comprises at least two configuration areas, the first configuration file comprises static complete data used for configuring a first configuration area of the at least two configuration areas, and the first configuration area is a complete reconstruction area;
the processor is used for determining that the terminal equipment is in a power-on state, acquiring and loading a first configuration file related to a Field Programmable Gate Array (FPGA) module in the terminal equipment in a first storage area, receiving a second configuration file sent by control equipment connected with the terminal equipment if the first configuration file is determined to be loaded successfully, determining that the second configuration file is loaded successfully, and starting the terminal equipment to enter a working state; the second configuration file comprises at least one secret data for configuring a second configuration area of the at least two configuration areas, the secret data is loaded online, and the second configuration area is a local reconstruction area.
7. The terminal device of claim 6, wherein the processor is further configured to:
after the first configuration file is successfully loaded and before a second configuration file sent by control equipment connected with the terminal equipment is received, platform identification information corresponding to the control equipment connected with the terminal equipment is determined, and a platform interface configuration file corresponding to the platform identification information in the first storage area is obtained;
and configuring a third configuration area of the at least two configuration areas based on the platform interface configuration file, wherein the third configuration area is used for configuring a functional interface between the terminal device and the control device.
8. The terminal device of claim 7, wherein the processor is further configured to:
after a third configuration area in the at least two configuration areas is configured based on the platform interface configuration file, determining that the third configuration file is loaded successfully, and generating a feedback message;
sending the feedback message to the control device to receive the second configuration file fed back by the control device based on the feedback message.
9. The terminal device of claim 8, wherein the processor is further configured to:
receiving update information for the second profile and/or the third profile;
updating the third configuration file in the terminal device and/or updating the second configuration file in the control device based on the updating information.
10. The terminal device of claim 6, wherein the processor is further configured to:
before the terminal equipment is determined to be in a power-on state, determining a complete configuration file corresponding to a complete configuration area of an FPGA module of the control equipment;
dividing the complete configuration area into at least two configuration areas based on at least one preset condition; the at least one preset condition comprises that a configuration file of the configuration area is lost in power failure and/or the configuration file of the configuration area corresponds to the platform.
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| US20190228666A1 (en) * | 2018-01-19 | 2019-07-25 | Ge Aviation Systems Llc | System and Method for Reconfiguring a System-On-Module for an Unmanned Vehicle |
| CN110196729B (en) * | 2018-11-30 | 2022-02-08 | 腾讯科技（深圳）有限公司 | Application program updating method, device and apparatus and storage medium |
| CN112291237A (en) * | 2020-10-28 | 2021-01-29 | 山东超越数控电子股份有限公司 | Reconfigurable symmetric encryption method for realizing software definition based on domestic FPGA |
| CN112597096B (en) * | 2020-12-15 | 2023-11-21 | 中国科学院计算技术研究所 | Low-power consumption FPGA part reconfigurable method and device |
| CN112347035B (en) * | 2021-01-11 | 2021-06-25 | 北京中超伟业信息安全技术股份有限公司 | Remote FPGA equipment-oriented dynamic part reconfigurable configuration device and method |
| CN113740851B (en) * | 2021-09-07 | 2023-06-13 | 电子科技大学 | SAR imaging data processing system of time-sharing multiplexing single DDR |
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