CN106771981A - A kind of test control circuit, chip and test control method - Google Patents
A kind of test control circuit, chip and test control method Download PDFInfo
- Publication number
- CN106771981A CN106771981A CN201710037683.1A CN201710037683A CN106771981A CN 106771981 A CN106771981 A CN 106771981A CN 201710037683 A CN201710037683 A CN 201710037683A CN 106771981 A CN106771981 A CN 106771981A
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- test
- signal
- unit
- control circuit
- scribe line
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of test control circuit, chip and test control method, including test enabling unit, for producing test to enable signal, and the test that will be produced enables signal output to power control unit, authentication unit and test and excitation unit；Power control unit, enables signal, it is determined whether power to authentication unit according to the test for receiving；Authentication unit, under power supply state, when the test for receiving enable signal it is effective when, whether by scribing, if scribe line is not by scribing, generation allows the signal of test to test and excitation unit to checking scribe line；Test and excitation unit, for when the test enable signal for receiving is effective with the signal for allowing to test, producing the test and excitation signal for testing circuit-under-test.The present invention can effectively reduce quiescent dissipation of the test control circuit under non-test, mode.
Description
Technical field
The present invention relates to electronic technology field, more particularly to a kind of test control circuit, chip and test control method.
Background technology
In order to improve the reliability of product, chip needs to carry out the test of system before dispatching from the factory.It is generally integrated in chip internal
Test circuit, is directly tested chip to improve testing efficiency by test circuit.Due in test mode, tester
All operationss authority is possessed to the memory in chip, is the safety of protection storage user data in chip, in chip testing
After the completion of to exit test pattern.
In Publication No. " CN104678284A ", a kind of entitled " novel test control for improving chip robustness
In the application of circuit and method ", it is noted that enable clock signal and reset signal that signal controls test circuit by testing,
After test enables invalidating signal, test control circuit clock signal is closed, while test control circuit reset signal keeps low
Level so that test control circuit cannot start, so as to substantially reduce the probability that chip enters test pattern extremely, while also dropping
The low dynamic power consumption of test control circuit.But, under non-test, mode, in reset state and without clock signal
Test control circuit, however it remains quiescent dissipation, and this quiescent dissipation is more highlighted under small size technique.Now, test
Control circuit generates unnecessary quiescent dissipation, reduces the performance of chip.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of test control circuit, chip and test control method,
Quiescent dissipation of the test control circuit under non-test, mode can effectively be reduced.
In order to reach the object of the invention, what the technical scheme of the embodiment of the present invention was realized in：
A kind of test control circuit is the embodiment of the invention provides, including：Test enabling unit, power control unit, test
Card unit and test and excitation unit, wherein,
The test enabling unit, for producing test to enable signal, and the test that will be produced enables signal output to electricity
Source control unit, authentication unit and test and excitation unit；
The power control unit, determines whether that authentication unit is powered for enabling signal according to the test for receiving；
The authentication unit, under power supply state, when the test enable signal for receiving is effective, checking scribe line to be
It is no by scribing；If scribe line is not by scribing, generation allows the signal of test to test and excitation unit；
The test and excitation unit, for when the test enable signal for receiving is effective with the signal for allowing to test, producing
The raw test and excitation signal for testing circuit-under-test.
Further, the power control unit specifically for：
When the test enable signal is effective, the power supply signal of high level is produced, think that the authentication unit is powered；
When the test enables invalidating signal, high-impedance state or low level power supply signal are produced, to turn off the checking
The power supply of unit.
Further, the power control unit is buffer or triple gate.
Further, the authentication unit includes random signal source module, Second processing module, the judgement in chip
Module and the first processing module in the scribe line, wherein,
The random signal source module, for producing random signal, and exports to the first processing module and described sentences
Disconnected module；
The first processing module, for being encrypted to the random signal for receiving using default AES,
And by the signal output after encryption to the Second processing module；
The Second processing module, place is decrypted for the signal after the encryption using default decipherment algorithm to reception
Reason, and by the signal output after decryption to the judge module；
The judge module, for the signal after the random signal of reception and decryption to be contrasted, if identical, output
The signal of test is allowed to the test and excitation unit.
Further, the power control unit respectively with the first processing module, the Second processing module and institute
Judge module is stated to be connected.
Further, the power control unit is also connected with the test and excitation unit, for when the test for receiving
When enabling invalidating signal, the power supply of the test and excitation unit is turned off.
The embodiment of the present invention additionally provides a kind of chip, including the test control circuit described in any of the above.
The embodiment of the present invention additionally provides a kind of test control method, including：
Test is produced to enable signal；
Judge whether test enables signal effective；
When the test enable signal is effective, whether checking scribe line is by scribing；If scribe line is produced not by scribing
Test and excitation signal, tests circuit-under-test；
When the test enables invalidating signal, the power supply of test control circuit is turned off.
Further, whether the checking scribe line specifically includes by scribing：
Chip produces random signal, and exports to the scribe line；
The scribe line is encrypted using default AES to the random signal, and generation is outputed signal to
The chip；
The chip is decrypted treatment to the output signal of the scribe line using default decipherment algorithm, and by itself and
The random signal is contrasted, if identical, the scribe line is not by scribing.
Further, when the test enables invalidating signal, high-impedance state or low electricity are exported by buffer or triple gate
Flat power supply signal, and then turn off the power supply of the test control circuit.
In the technical scheme that the present invention is provided, on the one hand, enable the power supply that signal controls test control circuit according to test
Signal, when test enables invalidating signal, test control circuit does not have power supply to power, with regard to no any power consumption penalty, effectively yet
Reduce quiescent dissipation of the test control circuit under non-test, mode；On the other hand, the present invention is without the reset for increasing complexity
Control circuit and clock control circuit, have just reached the effect of reduction power consumption more more preferable than prior art.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this hair
Bright schematic description and description does not constitute inappropriate limitation of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is a kind of structural representation of the test control circuit of the embodiment of the present invention；
Fig. 2 is another structural representation of the test control circuit of the embodiment of the present invention；
Fig. 3 is the schematic flow sheet of the test control method of the embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case where not conflicting, in the embodiment and embodiment in the application
Feature can mutually be combined.
As shown in figure 1, the test control circuit of the embodiment of the present invention, including test enabling unit, power control unit, test
Card unit and test and excitation unit, wherein,
Test enabling unit, for producing test to enable signal, and the test that will be produced enables signal output to power supply control
Unit processed, authentication unit and test and excitation unit；
Power control unit, determines whether that authentication unit is powered for enabling signal according to the test for receiving；
Authentication unit, under power supply state, when the test for receiving enable signal it is effective when, checking scribe line whether by
Scribing；If scribe line is not by scribing, generation allows the signal of test to test and excitation unit；
Test and excitation unit, for when the test enable signal for receiving is effective with the signal for allowing to test, producing use
In the test and excitation signal of test circuit-under-test.
There are the thousands of chips of marshalling on usual silicon chip (wafer), left between every two adjacent chips
The space of fixed width carries out wafer cuttings as scribe line for saw blade.It is provided with scribe line for adjacent two
The chip fuse and circuit communicated between chip.After chip completes test assignment, scribe line is destroyed by scribing
In chip fuse and circuit, cause chip to cannot get correct data input, it is impossible to enter back into test pattern.
Further, whether the checking scribe line specifically includes by scribing：Judge whether is chip fuse in scribe line
In physical connection state, if chip fuse is not at physical connection state, scribe line is by scribing.
Alternatively, described test is enabled signal and is input into by chip exterior or chip internal generation.
Further, the power control unit specifically for：
When the test enable signal is effective, the power supply signal of high level is produced, think that authentication unit is powered；
When the test enables invalidating signal, high-impedance state or low level power supply signal are produced, to turn off authentication unit
Power supply.
Power control unit in the present invention can select different controlling parties according to the scale of test control circuit
Formula.In embodiments of the present invention, when test control circuit scale is smaller, power control unit is controlled using buffer buffer
System, the input connecting test of buffer enables signal, and the output end of buffer is exported by the power supply signal of control circuit.Work as survey
When the test enable signal of examination enabling unit output is effective, power control unit output high level, i.e. subsequent conditioning circuit have power supply；
When it is invalid that the test for testing enabling unit output enables signal, buffer is output as 0, and power control unit exports low electricity
Put down, i.e. subsequent conditioning circuit power ground, stop being powered to subsequent conditioning circuit.
Alternatively, the present invention can also use triple gate as power control unit, the input connecting test of triple gate
Signal is enabled, the output end of triple gate is exported by the power supply signal of control circuit.When the test of test enabling unit output is enabled
When signal is effective, power control unit output high level, i.e. subsequent conditioning circuit have power supply；It is when test enables module output signal
When invalid, the output end output high-impedance state of triple gate stops being powered to subsequent conditioning circuit.
Further, as shown in Fig. 2 the authentication unit is including the random signal source module in chip, at second
Reason module and judge module and the first processing module in scribe line, wherein,
The random signal source module, for producing random signal, and exports to first processing module and judge module；
The first processing module, for being encrypted to the random signal for receiving using default AES,
And by the signal output after encryption to Second processing module；
The Second processing module, place is decrypted for the signal after the encryption using default decipherment algorithm to reception
Reason, and by the signal output after decryption to judge module；
The judge module, for the signal after the random signal of reception and decryption to be contrasted, if identical, output
The signal of test is allowed to test and excitation unit.
Alternatively, the power control unit is connected with first processing module, Second processing module and judge module respectively
Connect, for when the test for receiving enables invalidating signal, turning off the electricity of first processing module, Second processing module and judge module
Source.
The random signal that the random signal source module is produced is the random number of many bits.What deserves to be explained is, due to
The random signal that machine signal source module is produced in each starting up is easy to be attacked by attacker, power supply list of the invention
Power supply of the unit not used for control random signal source module.
Alternatively, the power control unit is also connected with test and excitation unit, for enabling letter when the test for receiving
When number invalid, the power supply of test and excitation unit is turned off.
Test control circuit of the invention, power control unit is increased by original circuit base, is made according to test
Energy signal produces power supply signal, and the power supply of the part or all of circuit in test control circuit is controlled by power supply signal.Surveying
When examination enables invalidating signal, test control circuit does not have power supply to power, just without any power consumption penalty, so as to effectively reduce survey yet
Quiescent dissipation of the examination control circuit under non-test, mode；On the other hand, the present invention need not increase the reset control electricity of complexity
Road and clock control circuit, it becomes possible to reach the effect of reduction power consumption more more preferable than prior art.
The embodiment of the invention also discloses a kind of chip, including the test control circuit described in any of the above.
As shown in figure 3, the embodiment of the invention also discloses a kind of test control method, including：
Test is produced to enable signal；
Judge whether test enables signal effective；
When test enable signal is effective, whether checking scribe line is by scribing；If scribe line produces test not by scribing
Pumping signal, tests circuit-under-test；
When test enables invalidating signal, the power supply of test control circuit is turned off.
Alternatively, described test is enabled signal and is input into by chip exterior or chip internal generation.
Further, whether the checking scribe line specifically includes by scribing：Judge whether is chip fuse in scribe line
In physical connection state, if chip fuse is not at physical connection state, scribe line is by scribing.
Further, whether the chip fuse judged in scribe line is in physical connection state, specifically includes：
Chip produces random signal, and exports to scribe line；
Scribe line is encrypted using default AES to random signal, and generation outputs signal to chip；
Chip is decrypted treatment to the output signal of scribe line using default decipherment algorithm, and by itself and random signal
Contrasted, if identical, the chip fuse in scribe line is in physical connection state.
Alternatively, when the test enables invalidating signal, high-impedance state or low level are exported by buffer or triple gate
Power supply signal, and then turn off test control circuit power supply.When test enable signal is effective, by buffer or triple gate
Output high level, is that test control circuit is powered.
Test control method of the invention, the power supply signal that signal controls test control circuit is enabled according to test, is being surveyed
When examination enables invalidating signal, test control circuit does not have power supply to power, just without any power consumption penalty, so as to effectively reduce survey yet
Quiescent dissipation of the examination control circuit under non-test, mode；On the other hand, the present invention need not increase the reset control electricity of complexity
Road and clock control circuit, it becomes possible to reach the effect of reduction power consumption more more preferable than prior art.
Although disclosed herein implementation method as above, described content be only readily appreciate the present invention and use
Implementation method, is not limited to the present invention.Technical staff in any art of the present invention, is taken off the present invention is not departed from
On the premise of the spirit and scope of dew, any modification and change, but the present invention can be carried out in the form and details implemented
Scope of patent protection, must be still defined by the scope of which is defined in the appended claims.
Claims (10)
1. a kind of test control circuit, it is characterised in that including：Test enabling unit, power control unit, authentication unit and survey
Examination exciting unit, wherein,
The test enabling unit, for producing test to enable signal, and the test that will be produced enables signal output to power supply control
Unit processed, authentication unit and test and excitation unit；
The power control unit, determines whether that authentication unit is powered for enabling signal according to the test for receiving；
The authentication unit, under power supply state, when the test for receiving enable signal it is effective when, checking scribe line whether by
Scribing；If scribe line is not by scribing, generation allows the signal of test to test and excitation unit；
The test and excitation unit, for when the test enable signal for receiving is effective with the signal for allowing to test, producing use
In the test and excitation signal of test circuit-under-test.
2. test control circuit according to claim 1, it is characterised in that the power control unit specifically for：
When the test enable signal is effective, the power supply signal of high level is produced, think that the authentication unit is powered；
When the test enables invalidating signal, high-impedance state or low level power supply signal are produced, to turn off the authentication unit
Power supply.
3. test control circuit according to claim 2, it is characterised in that the power control unit is buffer or three
State door.
4. test control circuit according to claim 1, it is characterised in that the authentication unit includes being located in chip
Random signal source module, Second processing module, judge module and the first processing module in the scribe line, wherein,
The random signal source module, for producing random signal, and exports to the first processing module and the judgement mould
Block；
The first processing module, for being encrypted to the random signal for receiving using default AES, and will
Signal output after encryption is to the Second processing module；
The Second processing module, treatment is decrypted for the signal after the encryption using default decipherment algorithm to reception,
And by the signal output after decryption to the judge module；
The judge module, for the signal after the random signal of reception and decryption to be contrasted, if identical, output is allowed
The signal of test is to the test and excitation unit.
5. test control circuit according to claim 4, it is characterised in that the power control unit is respectively with described
One processing module, the Second processing module are connected with the judge module.
6. test control circuit according to claim 5, it is characterised in that the power control unit also with the test
Exciting unit is connected, for when the test for receiving enables invalidating signal, turning off the power supply of the test and excitation unit.
7. a kind of chip, it is characterised in that including the test control circuit described in claim any one of 1~claim 6.
8. a kind of test control method, it is characterised in that including：
Test is produced to enable signal；
Judge whether test enables signal effective；
When the test enable signal is effective, whether checking scribe line is by scribing；If scribe line produces test not by scribing
Pumping signal, tests circuit-under-test；
When the test enables invalidating signal, the power supply of test control circuit is turned off.
9. test control method according to claim 8, it is characterised in that whether the checking scribe line is by scribing, tool
Body includes：
Chip produces random signal, and exports to the scribe line；
The scribe line is encrypted using default AES to the random signal, and generation outputs signal to described
Chip；
The chip is decrypted treatment to the output signal of the scribe line using default decipherment algorithm, and by itself and it is described
Random signal is contrasted, if identical, the scribe line is not by scribing.
10. test control method according to claim 8, it is characterised in that when the test enables invalidating signal, lead to
Buffer or triple gate output high-impedance state or low level power supply signal are crossed, and then turns off the power supply of the test control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710037683.1A CN106771981A (en) | 2017-01-18 | 2017-01-18 | A kind of test control circuit, chip and test control method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710037683.1A CN106771981A (en) | 2017-01-18 | 2017-01-18 | A kind of test control circuit, chip and test control method |
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Cited By (5)
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| CN109765500A (en) * | 2017-11-08 | 2019-05-17 | 中兴通讯股份有限公司 | A kind of power supply analog machine and power supply analogy method |
| CN109782153A (en) * | 2019-01-14 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of method, apparatus of chip testing, chip and computer storage medium |
| CN110457172A (en) * | 2019-08-12 | 2019-11-15 | 兆讯恒达微电子技术(北京)有限公司 | A kind of detection method for during flow |
| WO2023093357A1 (en) * | 2021-11-26 | 2023-06-01 | 深圳飞骧科技股份有限公司 | Devm test platform and test method for wifi 6 chip |
| WO2024031817A1 (en) * | 2022-08-12 | 2024-02-15 | 长鑫存储技术有限公司 | Temperature measurement control circuit and storage device |
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| CN109782153A (en) * | 2019-01-14 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of method, apparatus of chip testing, chip and computer storage medium |
| CN110457172A (en) * | 2019-08-12 | 2019-11-15 | 兆讯恒达微电子技术(北京)有限公司 | A kind of detection method for during flow |
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| WO2023093357A1 (en) * | 2021-11-26 | 2023-06-01 | 深圳飞骧科技股份有限公司 | Devm test platform and test method for wifi 6 chip |
| WO2024031817A1 (en) * | 2022-08-12 | 2024-02-15 | 长鑫存储技术有限公司 | Temperature measurement control circuit and storage device |
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Application publication date: 20170531 |