CN1067325A - Semiconductor memory - Google Patents
Semiconductor memory Download PDFInfo
- Publication number
- CN1067325A CN1067325A CN92100194A CN92100194A CN1067325A CN 1067325 A CN1067325 A CN 1067325A CN 92100194 A CN92100194 A CN 92100194A CN 92100194 A CN92100194 A CN 92100194A CN 1067325 A CN1067325 A CN 1067325A
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- China
- Prior art keywords
- aforementioned
- bit line
- electric crystal
- writing
- require
- Prior art date
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- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000013078 crystal Substances 0.000 claims abstract description 67
- 230000015654 memory Effects 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 3
- 230000005055 memory storage Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
The present invention system provides a kind of semiconductor memory, system by: mnemon, text line, a pair of bit line, and free charging facility constituted, wherein more comprise leakage current compensating circuit, in order to leakage current that compensates the bit line that is connected with mnemon and the CMOS long period electric current that prevents to flow into mnemon, the combination of used CMOS electric crystal intersection is constituted.
Description
Present invention is directed to semiconductor memory (storage) device, particularly relevant in the static random memory (hereinafter to be referred as SRAM) of high power capacity, the improvement semiconductor memory that possesses the bit line is arranged (Bit Line) leakage current compensating circuit, this bit linear system can prevent that data from reading/misoperation during write activity.
In the accompanying drawing, shown in the 3rd figure and the 4th figure be with the present invention in as the relevant circuit of mnemon of the SRAM of prior art object, this is described as follows:
Essential structure 1 with memory storage is shown in the 3rd figure and the 4th figure, and memory storage includes: mnemon (memory cell) 311, be can keep to electric property " 0 " or " 1 " data latch structure; Text line (Word Line) WL is to be connected with the grid of MOS electric crystal 2,3, and these MOS electric crystal systems are connected to the suitching type electric crystal at these mnemon 311 two ends; And bit line BLi, BLi are to be connected on the signal wire of these suitching type electric crystals; More comprise freely (Free Change) the electric crystal T that charges
31, T
32, be to be connected between bit line and the power supply, make this to the bit line respectively before reading and writing, charge comparably with predetermined current potential; Comprise MOS electric crystal T again
35, be to be connected between the bit line, for the equalization of data line, can accept not decide pulse φ BQi by being shown in giving that equalizer circuit among the figure supplied with.
The pulse signal of mark φ BLi in these electric crystal acceptance patterns that freely charge, this just means that this SRAM is needn't be by the asynchronous type SRAM of outside service time pulse.Asynchronous type SRAM has ATD(Address Transistion Detector) memory storage, ATD changes according to detecting address signal, produce clock pulse by inside, and carries out action; Aforementioned φ BLi signal is to be supplied with by ATD.
Remove outside the general SRAM of its peripheral circuit part, among the figure, the bit leakage current compensation device possesses each bit line in parallel with the electric crystal that freely charges.The 3rd figure is the example that P type MOS clamp (Clamping) electric crystal is used in expression; The 4th figure is the example that N type MOS clamp electric crystal is used in expression.
Use the background of this device to be, because of the integrated level of semiconductor device increases, but not in narrow and small area, possess a lot of element can not, therefore on the dimension of manufacturing engineering, require the miniaturization engineering, this project easily produces the electric property short circuit of each interlayer of the element that constitutes electrical specification.Main cause on engineering, lift the one example, connecting portion in the MOS electric crystal and the distance between grid very near the time, between grid and connecting portion, can produce the dimension shot (Shot) of microcosmic, between the source electrode of electric crystal and grid or between drain electrode and the grid, form the leakage current passage, this leakage current is on the bit line, because of the accurate step-down in electric signal position of bit line, and produce the situation of misoperation.In the specific implementation of the high power capacity memory storage of 1M bit, the compensation system of this electric leakage of misgivings must be arranged, the bit line leakage current compensating circuit 31 that the 3rd figure and the 4th figure adopt in order to prevent so misoperation with regard to expression is to 34(41 to 44).
In the 3rd figure, when selecting text line WL
1The time, mnemon 311,312 is promptly selected, see through the electric crystal of storing in the mnemon that " 0 " data is for example arranged (not being shown among the figure), by the formed clamp circuit of P type MOS electric crystal, charging charge will compensate charge leakage, and form very little DC channel.This is the main cause that produces the electric current that flows to mnemon, and acts on.And, the memory storage of miniaturization and high power capacity, because of with text line WL
1The number of the mnemon that connects is a lot of, so CMOS long period (Long Cycle) electric current that is consumed by mnemon increases therewith in direct ratioly.
Under the situation of the 4th figure, same shortcoming is also arranged.
Above-mentioned known technology is relevant with the CMOS SRAM with access time 25ns, capacity 1M bit, and it is seen to be published in the 7330740th page the document of IEEE Journal of Solid-State Circuit Vol.SC-22 No.5 in October, 1987.
Therefore, the objective of the invention is for solving aforesaid shortcoming, and a kind of semiconductor memory be provided, this semiconductor memory have at a high speed, the bit line leakage current current compensation of highly integrated memory storage, more Gai Liang circuit.
Another object of the present invention provides a kind of semiconductor device, not only can reduce to consume CMOS long period electric current, and owing to the mnemon with majority is connected with single text line, can dwindles square (Block) number, and make wafer occupied area minimization.
For reaching aforementioned purpose of the present invention, a kind of semiconductor memory is provided now, it has: mnemon, text line, and bit line, and more in the high power capacity SRAM of the free charging facility with bit line, have: the 1st switches electric crystal and the 2nd switches electric crystal; The 1st switches the signal that the acceptance of electric crystal system is transported to by the free charging facility of the 1st bit line side, and as control signal, its source electrode is connected in power supply, and its drain electrode is connected in the 2nd bit line side, with the compensation leakage current; The 2nd switches the signal that electric crystal system accepts the free charging facility of the 2nd bit line side, and as control signal, its source electrode is connected in power supply, and its drain electrode is connected in the 1st bit line side, with the compensation leakage current.
Feature of the present invention provides a kind of semiconductor memory, and it has: mnemon, text line, and bit line, and more in the high power capacity SRAM of the free charging facility with bit line, have: the 1st switches electric crystal; The 2nd switches electric crystal; Reach the 2nd and switch electric crystal; The 1st switches the free charging facility signal that electric crystal is acceptance the 1st a bit line side, and its drain electrode is connected in the 2nd bit line, with blocking leakage current or OFF electric current; The 2nd switches the free charging facility signal that electric crystal system accepts the 2nd bit line side, and its drain electrode is connected in the 1st bit line side, with blocking leakage current or OFF electric current; The 3rd switching crystal is the common source electrode that is connected in the 1st, the 2nd switching electric crystal, and supply power.
Below, circuit of the present invention constitutes and action effect should be with reference to accompanying drawing, and the embodiment technology that foundation is following will be more clear.
Possess the embodiment that has corresponding to the semiconductor memory of the bit line leakage current compensation device of purpose of the present invention, be shown among the 1st figure and the 2nd figure.
Because of the essential structure of the memory storage in the 3rd figure and the 4th figure, suitable equally in the 1st figure and the 2nd figure, so give same reference numeral, continue known example and describe in more detail for identical constitutive requirements.
Circuit of the present invention has shown in the 1st figure: mnemon; Text line; And, bit line BL
1, BL
1, it is characterized in that: in the high power capacity SRAM of free charging facility, have more and have the 1st and switch electric crystal Q with bit line
12Reach the 2nd and switch electric crystal Q
11; The 1st switches electric crystal Q
12Be to accept by the 1st bit line BL
1The signal that the free charging facility of side is transported to, as control signal, its source electrode is connected in power Vcc, and its drain electrode is connected in the 2nd bit line BL
1Side is with the compensation leakage current; The 2nd switches electric crystal Q
11Be to accept the 2nd bit line BL
1The signal of the free charging facility of side, as control signal, its source electrode is connected in power Vcc, and its drain electrode is connected in the 1st bit line BL
1Side is with the compensation leakage current.And the electric crystal patterns system in the compensating circuit 11,12 is set at, and is same types as the employed electric crystal of free charging facility; And with the switching electric crystal of text line be different types.Following NMOS is defined as the 1st pattern, and PMOS is defined as the 2nd pattern.The present invention's circuit operation relevant with said shortcoming below is described.
For the convenience that illustrates, suppose in the mnemon of the 1st figure, at the 1st bit line BL
1Store, keep the data of high levels; At the 2nd bit line BL
1Then store, keep the data of low level, be illustrated.
According to by selected text line ML
1The signal of transporting to flows into, and selects text line WL
1, becoming ON by the switching electric crystal that connects mnemon and text line, mnemon can be connected with the electric property of data line ground.The aforementioned hypothesis voltage level of mnemon is with the prosperous body Q of P type MOS electricity of the bit line leakage current compensating circuit of circuit of the present invention
11And Q
12, become ON and OFF state respectively.Electric crystal Q
11The ON state, be in order to compensate the leakage current action of bit line; Become the electric crystal Q of OFF
12Mnemon is not supplied with any electric signal yet, therefore can not form as the known and connected current path of CMOS long period.
This circuit can be kept the data of bit line fully, can prevent that leakage current from flowing into mnemon simultaneously.More, for the high levels data of the 1st bit line, the compensation of leakage current can be kept current supply, but for the low level data of the 2nd bit line, but breaking current is supplied with.
And, the accurate P type MOS electric crystal T that is stranded of the free charge position of bit line
11-T
14Relation, to supply with the identical position of the accurate Vcc in position accurate with power supply and become.At the grid of the electric crystal that is used for this action of freely charging, input is by atd circuit (not being shown among the figure) signal supplied φ BLi, φ BLi.
Among the figure, be connected with mnemon 111 and mnemon 112 in succession, relevant with the operating state of having said, when the data of the bit line BLn of mnemon 112 side is " low level ", and the data of bit line BLn side is when being " high levels ", as saying, if select text line WL
1, electric crystal Q then
13Promptly become the OFF state, and electric crystal Q
14Promptly become the ON state, therefore, by the electric crystal Q of ON state
14, can keep the high levels data of bit line BLn side; Opposite, for the low level data of bit line BLn side, promptly breaking current is supplied with.This kind action all is suitable for all mnemon groups (Memory Cell Array).
In addition, though object of the present invention is the 3rd figure and the relevant device configuration example of the 4th figure with known circuit, in being suitable for principle of the present invention, be not data average means among the 1st figure of must being contained in or ATD etc.Just, the present invention is applicable to various memory storages.
Secondly, describe the 2nd embodiment of the present invention in detail with reference to the 2nd figure.The 2nd figure is the variation of the circuit of the present invention of expression the 1st figure, gives same reference symbol for identical constitutive requirements.But with the difference of the 1st figure circuit be, shown in the 2nd figure, the power supply that is supplied to leakage current compensating circuit 21,22 is the 1st type, just, supplies with for the MOS electric crystal via the N type here.
In the circuit of the 2nd embodiment, the accurate accurate V in critical voltage position that is had with the MOS electric crystal that comprises the 1st type of body effect (Body effect) in power supply position
TN 'Poor, borrow the MOS electric crystal T of the 1st type
21-T
24Supply with free charge position standard.
The MOS electric crystal is during by constructivity, have: grid, drain electrode, source electrode, and the heap utmost point, but in order to make the MOS electric crystal become the ON state, know as many institutes wealth, the voltage that is supplied to grid should be littler than the voltage that is supplied to source electrode, but than certain critical voltage Vth height.Yet, this critical voltage Vth position standard, because of the accurate voltage difference with source voltage position standard in heap pole tension position changes, if source voltage is piled pole tension when high, the Vth value promptly increases.In above stated specification, free charge position standard is not Vcc, but supplies with Vcc-V
TN ', its reason promptly is this.
Aforementioned content is relevant with the circuit operation of the 2nd embodiment.Just, the 1st type electric crystal Q is used in prompting
25Reason.Though the action of summary is identical with the 1st embodiment, for bit line BL
1Or BL
1High-level voltage be set at Vcc-V
TN 'So, in voltage vcc and the 2nd type PMOS electric crystal Q
21, Q
22Between, insert the NMOS electric crystal Q of the 1st type
25
In previous constructions, as the bit line BL that is connected on the mnemon node that stores the high levels data
1, or BL
1The place when leakage current takes place, relies on by electric crystal Q
21, Q
22ON, OFF the action, also can carry out identical: the misoperation that the blocking data is read with first embodiment; Blocking flows into the electric current of mnemon.
In addition, with the 1st embodiment further difference be employed electric crystal type.As the power supply supply mean of leakage current compensating circuit, and the MOS electric crystal that uses is considered body effect, therefore with the MOS electric crystal same-type that is used for free charging facility; And the MOS electric crystal in the connected leakage current compensating circuit is to select dissimilar electric crystal mutually.
Among the 1st embodiment and the 2nd embodiment, it is IGFET(Insulated Gate Field Effect Transistor that preferable element is selected).Its tie up to gate metal or and the electrode of its equal class, and between the semiconductor layer, the element of the insulation course of being separated by; Insulation course is for example: SiO
2, also available in addition Si
3N
4, Al
2O
3It is the part that is specially adapted to memory cell.
Circuit of the present invention is the memory storage that can be particularly suitable for highly integrated high power capacity.Relevant therewith, though the mnemon of majority can be connected in text line structure, this structure should be considered the wastage in bulk or weight magnitude of current in the mnemon.For example, when on a text line, connecting 128 mnemon circuit,, will be the product of each mnemon institute's current sinking and 128 in the total current that these mnemons consume, this determines the attachable memory of each text line square unit.
Graphic brief description:
The 1st figure is the circuit diagram of memory square that comprises the semiconductor memory of circuit of the present invention;
The 2nd figure is the 2nd embodiment circuit diagram relevant with the 1st figure;
Fig. 3 figure and the 4th figure are known memory square pie graphs.
11,12 ... compensating circuit
21,22 ... leakage current compensating circuit
111,112 ... mnemon
WL
1Text line
BL
1, BL
1The the 1st and the 2nd bit line
Claims (13)
1, a kind of semiconductor memory, possessing has: the text line of plural number is right with the bit line of plural number; Most mnemon, cording has the structure that latchs that is connected with each intersection point of aforementioned text line and bit line respectively; Free charging facility is to be connected between aforementioned paired the bit line and power supply, before reading or writing, with certain potentials, charges to the bit line idiostatic; And, leakage current compensating circuit, the leakage current in order to the compensation aforementioned memory cell is characterized in that: aforementioned leakage current compensating circuit system insert power supply and bit line between; And, be connected in the other side's drain terminal by each gate terminal of a pair of switching electric crystal, constituted.
2, require 1 semiconductor memory of being put down in writing as patent, wherein, the electric prosperous body same types of the pattern of this a pair of switching electric crystal system and the usefulness of freely charging; And, and the electric crystal that is connected between text line and mnemon is a different types.
3, require 1 semiconductor memory of being put down in writing as patent,, comprise the average means in wireless of an aforementioned contraposition.
4, require 1 semiconductor memory of being put down in writing as patent, the control signal system that is supplied to aforementioned free charging facility is by ATD(Address Transistion Detector) the circuit supply, this ATD system produces pulse according to detecting that address signal changes by inside, and the execution action.
5, require 1 semiconductor memory of being put down in writing as patent, aforementioned a pair of switching electric crystal is IGFET(Insulated Gate Field Effect Transistor).
6, require 1 semiconductor memory of being put down in writing as patent, the memory square system that comprises aforementioned memory cell is configured to, and majority connects on single text line.
7, a kind of semiconductor memory, possessing has: the text line of plural number is right with the bit line of plural number; Most mnemon, cording has the structure that latchs that is connected with each intersection point of aforementioned text line and bit line respectively; Free charging facility is to be connected between aforementioned paired the bit line and power supply, before reading or writing, with certain potentials, charges to the bit line idiostatic; And, leakage current compensating circuit, the leakage current in order to the compensation aforementioned memory cell is characterized in that: aforementioned leakage current compensating circuit system insert power supply and bit line between; And, be connected in the other side's drain terminal by each gate terminal of a pair of switching electric crystal, and another switches electric crystal, be that it leads to and is connected to the aforementioned a pair of source electrode of cutting electric crystal, and supply power is constituted.
8, require 7 semiconductor memories of being put down in writing as patent, wherein, the pattern of the electric prosperous body of the pattern of this a pair of switching electric crystal system and the usefulness of freely charging and this another switching electric crystal is different each other, is constituted.
9, require 7 semiconductor memories of being put down in writing as patent, more comprise the data average means that are formed between the aforementioned a pair of bit line.
10, require 7 semiconductor memories of being put down in writing as patent, the control signal system that is supplied to aforementioned free charging facility is by ATD(Address Transistion Detector) the circuit supply, this ATD system produces pulse according to detecting that address signal changes by inside, and the execution action.
11, require 7 semiconductor memories of being put down in writing as patent, aforementioned a pair of switching electric crystal and this another switching electric crystal are IGFET(Lnsulated Gate Field Effect Transistor).
12, require 7 semiconductor memories of being put down in writing as patent, close the voltage level of stating free charging facility and be critical voltage poor of supply voltage and used electric crystal.
13, require 7 semiconductor memories of being put down in writing as patent, the memory square system that comprises aforementioned memory cell is configured to, and majority connects on single text line.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910008735A KR920022301A (en) | 1991-05-28 | 1991-05-28 | Semiconductor memory |
| KR91-8735 | 1991-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1067325A true CN1067325A (en) | 1992-12-23 |
Family
ID=19315060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN92100194A Pending CN1067325A (en) | 1991-05-28 | 1992-01-10 | Semiconductor memory |
Country Status (7)
| Country | Link |
|---|---|
| KR (1) | KR920022301A (en) |
| CN (1) | CN1067325A (en) |
| DE (1) | DE4135686A1 (en) |
| FR (1) | FR2677162A1 (en) |
| GB (1) | GB2256297A (en) |
| IT (1) | IT1251623B (en) |
| NL (1) | NL9101772A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100347786C (en) * | 2002-04-04 | 2007-11-07 | 三菱电机株式会社 | Semiconductor memory device having memory cells requiring no refresh operations |
| CN100350507C (en) * | 2002-09-25 | 2007-11-21 | 松下电器产业株式会社 | Semiconductor stroage device |
| CN100397279C (en) * | 2002-10-31 | 2008-06-25 | 松下电器产业株式会社 | Current leakage compensator and its compensating method |
| CN100419914C (en) * | 2001-03-30 | 2008-09-17 | 英特尔公司 | Apparatus and method for a memory storage cell leakage cancellation scheme |
| CN106558329A (en) * | 2015-09-30 | 2017-04-05 | 展讯通信（上海）有限公司 | A kind of difference reading circuit of single-ended memory and method |
| WO2018152952A1 (en) * | 2017-02-21 | 2018-08-30 | 中国科学院上海微***与信息技术研究所 | Readout circuit and readout method for three-dimensional memory |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828610A (en) * | 1997-03-31 | 1998-10-27 | Seiko Epson Corporation | Low power memory including selective precharge circuit |
| JP3544933B2 (en) * | 2000-10-05 | 2004-07-21 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor integrated circuit |
| KR100732390B1 (en) * | 2001-12-29 | 2007-06-27 | 매그나칩 반도체 유한회사 | current mirror type circuit for compensating leakage current |
| DE10255102B3 (en) * | 2002-11-26 | 2004-04-29 | Infineon Technologies Ag | Semiconducting memory cell, especially SRAM cell, has arrangement for adapting leakage current that causes total leakage current independent of memory state, especially in the non-selected state |
| US6967875B2 (en) * | 2003-04-21 | 2005-11-22 | United Microelectronics Corp. | Static random access memory system with compensating-circuit for bitline leakage |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0073726B1 (en) * | 1981-09-01 | 1987-11-25 | Fujitsu Limited | Semi-conductor memory circuit |
| US4467451A (en) * | 1981-12-07 | 1984-08-21 | Hughes Aircraft Company | Nonvolatile random access memory cell |
| US4494221A (en) * | 1982-03-03 | 1985-01-15 | Inmos Corporation | Bit line precharging and equilibrating circuit |
| JPS61239493A (en) * | 1985-04-05 | 1986-10-24 | Fujitsu Ltd | Semiconductor memory device |
| JPS63131396A (en) * | 1986-11-20 | 1988-06-03 | Ricoh Co Ltd | Sense circuit for semiconductor memory device |
| JPS63166090A (en) * | 1986-12-26 | 1988-07-09 | Toshiba Corp | Static memory |
| JPH0760600B2 (en) * | 1987-08-19 | 1995-06-28 | 三菱電機株式会社 | Synchronous storage device |
| JP2542022B2 (en) * | 1987-12-18 | 1996-10-09 | 沖電気工業株式会社 | Field effect transistor load circuit |
| US4975879A (en) * | 1989-07-17 | 1990-12-04 | Advanced Micro Devices, Inc. | Biasing scheme for FIFO memories |
-
1991
- 1991-05-28 KR KR1019910008735A patent/KR920022301A/en not_active Application Discontinuation
- 1991-10-14 GB GB9121767A patent/GB2256297A/en not_active Withdrawn
- 1991-10-23 IT ITMI912808A patent/IT1251623B/en active IP Right Grant
- 1991-10-23 NL NL9101772A patent/NL9101772A/en not_active Application Discontinuation
- 1991-10-25 DE DE4135686A patent/DE4135686A1/en not_active Withdrawn
- 1991-10-25 FR FR9113207A patent/FR2677162A1/en active Pending
-
1992
- 1992-01-10 CN CN92100194A patent/CN1067325A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100419914C (en) * | 2001-03-30 | 2008-09-17 | 英特尔公司 | Apparatus and method for a memory storage cell leakage cancellation scheme |
| CN100347786C (en) * | 2002-04-04 | 2007-11-07 | 三菱电机株式会社 | Semiconductor memory device having memory cells requiring no refresh operations |
| CN100350507C (en) * | 2002-09-25 | 2007-11-21 | 松下电器产业株式会社 | Semiconductor stroage device |
| CN100397279C (en) * | 2002-10-31 | 2008-06-25 | 松下电器产业株式会社 | Current leakage compensator and its compensating method |
| CN106558329A (en) * | 2015-09-30 | 2017-04-05 | 展讯通信（上海）有限公司 | A kind of difference reading circuit of single-ended memory and method |
| WO2018152952A1 (en) * | 2017-02-21 | 2018-08-30 | 中国科学院上海微***与信息技术研究所 | Readout circuit and readout method for three-dimensional memory |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2677162A1 (en) | 1992-12-04 |
| DE4135686A1 (en) | 1992-12-03 |
| KR920022301A (en) | 1992-12-19 |
| GB2256297A (en) | 1992-12-02 |
| ITMI912808A0 (en) | 1991-10-23 |
| GB9121767D0 (en) | 1991-11-27 |
| ITMI912808A1 (en) | 1993-04-23 |
| NL9101772A (en) | 1992-12-16 |
| IT1251623B (en) | 1995-05-17 |
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