CN105811937A - Waveform output method and device - Google Patents
Waveform output method and device Download PDFInfo
- Publication number
- CN105811937A CN105811937A CN201610145936.2A CN201610145936A CN105811937A CN 105811937 A CN105811937 A CN 105811937A CN 201610145936 A CN201610145936 A CN 201610145936A CN 105811937 A CN105811937 A CN 105811937A
- Authority
- CN
- China
- Prior art keywords
- value
- count
- pwm waveform
- waveform
- count mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 76
- 230000000295 complement effect Effects 0.000 abstract description 29
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000003780 insertion Methods 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 238000004064 recycling Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Inverter Devices (AREA)
Abstract
The application provides a waveform output method and a device, comprising the following steps: in the process of counting the machine period according to the counting mode, when the judgment counting value reaches a first numerical value, controlling a first PWM waveform to carry out level inversion; otherwise, controlling the level of the first PWM waveform to keep unchanged; in the process of counting the machine period according to the counting mode, when the judgment counting value reaches a second numerical value, controlling a second PWM waveform to carry out level inversion; otherwise, the level of the second PWM waveform is controlled to remain unchanged. The polarity of the initial level of the first PWM waveform is opposite to that of the initial level of the second PWM waveform, the first value and the second value are not equal and are both smaller than the counting peak value, and the product of the absolute value of the difference value of the first value and the second value and the machine period is preset dead time. According to the method and the device, the dead time is inserted while the complementary PWM waveform is output, so that the complexity of the waveform generator can be reduced, and the generation efficiency can be improved.
Description
Technical field
The application relates to integrated circuit and automation application technical field, particularly relates to a kind of Waveform output method and device.
Background technology
At present, technical field is controlled at some, it is necessary to use PWM (PulseWidthModulation, the pulse width modulation) waveform that two-way is complementary.When two-way complementation PWM waveform is specially a road PWM waveform output high level, an other road PWM waveform output low level, i.e. the level of a road PWM waveform always complementary relation.
Such as, in electric machines control technology process, it will usually use two-way complementation PWM waveform to control H bridge.As it is shown in figure 1, be a kind of circuit diagram of H bridge.H bridge has two brachium pontis as can be seen from Figure 1;One of them brachium pontis is made up of gate-controlled switch S1 and gate-controlled switch S2, and another brachium pontis is made up of gate-controlled switch S3 and gate-controlled switch S4.Each brachium pontis forms by upper half-bridge and lower half-bridge, for instance, gate-controlled switch S1, S3 are upper half-bridge, and gate-controlled switch S2, S4 are lower half-bridge.Owing to the brachium pontis of H bridge is between power supply and ground, therefore, when using H bridge, it is necessary to assure the upper half-bridge of brachium pontis and what lower half-bridge can not simultaneously turn on, because simultaneously turning on, can cause that H bridge burns.Such as, gate-controlled switch S1 (upper half-bridge) and lower half-bridge (gate-controlled switch S2) can not simultaneously turn on.
For this, employing two-way complementation PWM (PulseWidthModulation, pulse width modulation) waveform controls the brachium pontis of H bridge under normal circumstances, and one of them PWM waveform controls upper half-bridge, and another PWM waveform controls lower half-bridge.Referring to Fig. 2, for the schematic diagram of ideally two-way complementation PWM waveform.Figure it is seen that the low and high level of two-way PWM waveform (PWM1 and PWM2) is always contrary, namely when PWM1 exports high level, PWM2 output low level;When PWM1 output low level, PWM2 exports high level.
It is all the conducting of same level due to gate-controlled switch, is namely both high level conducting or is both low level conducting;Therefore, therefore in the ideal case, the two-way complementation PWM waveform shown in Fig. 2 is adopted, it is ensured that upper half-bridge turns on half-bridge at present and is off, and it is in the conduction state that upper half-bridge disconnects half-bridge at present;That is, upper half-bridge and lower half-bridge can not simultaneously turn on.
But in practical situations both, certain time-delay is had when closed due to controlled member, this can cause when the low and high level of two-way complementation PWM switches, and occurs in and closes upper half-bridge (lower half-bridge) when being not turned off, situation that lower half-bridge (upper half-bridge) has already turned on.This can cause the situation that upper half-bridge and lower half-bridge are opened simultaneously occur.
In order to avoid this situation occurs, current solution is at the two-way previously inserted Dead Time of PWM waveform high level.Referring to Fig. 3, for two-way complementation PWM waveform (PWM11 and PWM22) after insertion Dead Time t.Purpose at the previously inserted Dead Time of PWM waveform high level is, set aside some time close gate-controlled switch for upper half-bridge (lower half-bridge), to guarantee that upper half-bridge (lower half-bridge) opens lower half-bridge (upper half-bridge) again after having been switched off, thus avoid the occurrence of half-bridge and situation that lower half-bridge is opened simultaneously.
Summary of the invention
Applicant finds in research process: Waveform generator can be utilized to generate the complementary PWM waveform with Dead Time.Referring to Fig. 4, the schematic diagram in control process in Waveform generator.Wherein, transverse axis is clock, the longitudinal axis is count value;The original levels value of PWM1 is low level L, PWM2 original levels value is high level H;The counts peaks of period register is P, and the numerical value of duty cycle register is P1;The initial pattern of count mode depositor is incremental count.
Process count value machine cycle counted at counting module starts to be incremented by from 0, and count value and dutyfactor value, in counting module counting process, are contrasted by comparison module;In T1 moment count value equal to dutyfactor value P1, then control PWM1 and PWM2 trigging signal.Counting module continues to machine is counted, and when T2 moment count value reaches counts peaks P, this hour counter upwards overflows, and then changes the counting direction of counting module, starts countdown.
In countdown process, count value starts to successively decrease from counts peaks, and count value and dutyfactor value, in counting module counting process, are contrasted by comparison module;In T3 moment count value equal to dutyfactor value P1, then control PWM1 and PWM2 trigging signal.Counting module continues to counting, and when T4 moment count value reaches 0, this hour counter overflows downwards, then changes the counting direction of counting module, begins incrementally counting up.Waveform generator can repeat said process, thus producing two complementary waveforms of periodic PWM1 and PWM2.
Referring to Fig. 5, after producing complementary PWM waveform, start Waveform generator and utilize dead band insertion module to insert Dead Time in PWM1 and PWM2 respectively, thus generating the final required complementary PWM waveform with Dead Time.
Be can be seen that by foregoing, above-mentioned generation needs the complementary PWM waveform of first generation to be then inserted into Dead Time with the process of the complementary PWM waveform of Dead Time, just can generating the complementary PWM waveform with Dead Time, this makes generation complex with the step of the complementary PWM waveform of Dead Time.And it is further desired that be separately provided dead band in Waveform generator to insert module, increase the complexity of Waveform generator.
Given this, it is now desired to a kind of simple method generates the complementary PWM waveform with Dead Time, in order to reduce the complexity of Waveform generator and improve formation efficiency.
To achieve these goals, this application provides techniques below means:
A kind of Waveform output method, including:
In the process machine cycle counted by count mode, when judging that count value reaches the first numerical value, control the first PWM waveform and carry out level upset;Otherwise, the level controlling described first PWM waveform remains unchanged;
In the process machine cycle counted by described count mode, when judging that described count value reaches second value, control the second PWM waveform and carry out level upset;Otherwise, the level controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
Preferably, also include:
When described count mode is incremental count pattern, when described count value reaches counts peaks set in advance by zero, described count mode is changed to countdown pattern;
When described count mode is countdown pattern, when described count value reaches zero by counts peaks set in advance, described count mode is changed to incremental count pattern.
Preferably, before carrying out, by count mode, the process counted, also include:
Set the first original levels polarity of described first PWM waveform and the second original levels polarity of described second PWM waveform.
Preferably, before carrying out, by count mode, the process counted, also include:
Set described count mode as incremental count pattern or countdown pattern.
Preferably, before carrying out, by count mode, the process counted, also include:
Presetting described counts peaks, described counts peaks is for representing the maximum of described count value.
Preferably, before carrying out, by count mode, the process counted, also include:
Preset described first numerical value;Described first numerical value is for representing the dutyfactor value of described first PWM waveform;
Preset described second value;Described second value is for representing the dutyfactor value of described second PWM waveform.
A kind of Waveform output device, including:
First processing unit, in the process machine cycle counted by count mode, when judging that count value reaches the first numerical value, controls the first PWM waveform and carries out level upset;Otherwise, the level controlling described first PWM waveform remains unchanged;
Second processing unit, in the process machine cycle counted by described count mode, when judging that described count value reaches second value, controls the second PWM waveform and carries out level upset;Otherwise, the level controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
Preferably, also include:
First changing unit, for when described count mode is incremental count pattern, when described count value reaches counts peaks set in advance by zero, being changed to countdown pattern by described count mode;
Second changing unit, for when described count mode is countdown pattern, when described count value reaches zero by counts peaks set in advance, being changed to incremental count pattern by described count mode.
A kind of Waveform output device, including:
Period register, for the counts peaks of stored count module;
First depositor, is used for storing the first numerical value;
Second depositor, is used for storing second value;Wherein, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of machine cycle;
First initial polarity depositor, for storing the first original levels polarity of the first PWM waveform;
Second initial polarity depositor, for storing the second original levels polarity of the second PWM waveform;
Count mode depositor, for the count mode of stored count module;
Counting module, for counting the machine cycle according to the count mode set in described count mode depositor;
Comparison module, for the count value of described counting module being contrasted with storage the first numerical value in described first depositor, and contrasts the count value of described counting module with the storage second value in described second depositor;
Waveform controls module, and for when described comparison module judges that count value reaches the first numerical value, controlling the first PWM waveform and carry out level upset, the level otherwise controlling described first PWM waveform remains unchanged;When described comparison module judges that count value reaches second value, controlling the second PWM waveform and carry out level upset, the level otherwise controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
Preferably, described comparison module, being additionally operable to when the described count mode of described counting module is incremental count pattern, when described count value reaches counts peaks set in advance by zero, the count mode controlling described count mode depositor is changed to countdown pattern;And, when the described count mode of described counting module is countdown pattern, when described count value reaches zero by counts peaks set in advance, the count mode controlling described count mode depositor is changed to incremental count pattern.
The Waveform output method that the application provides provides two numerical value, is the first PWM waveform and the first numerical value is set, be that the second PWM waveform arranges second value.Further, the first numerical value and second value are unequal, and both absolute difference and the product of machine cycle are equal to Dead Time set in advance.Dead Time is taken into account by the first numerical value and second value owing to setting, so, the first PWM waveform and the second PWM waveform that utilize the first numerical value and second value output have had Dead Time, therefore, it is not necessary to module is inserted in recycling dead band is inserted into Dead Time.
Therefore, the application just inserts Dead Time while the complementary PWM waveform of output, dead band insertion module need not be recycled and be inserted separately into Dead Time, so need not insert in module, Waveform generator and also need not add dead band and insert module in individually designed dead band again, therefore can reduce the complexity of Waveform generator and improve formation efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the application, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of circuit diagram of H bridge;
Fig. 2 is the schematic diagram of ideally complementary PWM waveform;
Fig. 3 is the schematic diagram of the complementary PWM waveform with dead band;
Fig. 4 is the schematic diagram generating complementary PWM waveform disclosed in prior art;
Fig. 5 is the waveform diagram inserting Dead Time disclosed in prior art;
Fig. 6 is the flow chart of a kind of Waveform output method disclosed in the embodiment of the present application;
Fig. 7 is the oscillogram of a kind of Waveform output method disclosed in the embodiment of the present application;
Fig. 8 is the structural representation of a kind of Waveform output device disclosed in the embodiment of the present application.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.Based on the embodiment in the application, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of the application protection.
Applicant finds after the process generating PWM waveform that research summary of the invention provides:
Prior art only sets a numerical value, for controlling the dutycycle of significant level in the second PWM waveform of the first PWM waveform., namely the numerical value of the first PWM waveform and the numerical value of the second PWM waveform are equal, and this is that the complementary PWM waveform causing prior art to export is not with the basic reason of Dead Time.
Therefore, the application arranges two numerical value, is that the first PWM waveform arranges the first numerical value, and is that the second PWM waveform arranges second value, as long as so arranging the first numerical value and second value being unequal, just can control in the first PWM waveform and the second PWM waveform with Dead Time.The specific descriptions of detailed process embodiment as described below.
The application needs output two-way complementation PWM waveform, in order to convenient narration adopts the first PWM waveform and the second PWM waveform to represent, all adopts the first PWM waveform and the second PWM waveform to describe in process described below.Before performing the waveform controlling method that the application provides, first the process needing to first carry out in advance is described:
First, set the original levels polarity of the first PWM waveform and the second PWM waveform.
Set the original levels polarity of described first PWM waveform as the first original levels polarity, and set described second PWM waveform original levels polarity as the second original levels polarity.Owing to the application needs output two-way complementation PWM waveform, therefore, the first original levels polarity and the second original levels polarity are complementary, namely contrary.Such as, when the first original levels polarity is high level, the second original levels polarity is low level;When the first original levels polarity is low level, the second original levels polarity is high level.
Second, set count mode.
Presetting count mode, count mode is incremental count pattern or countdown pattern.
3rd, set counts peaks.
Presetting described counts peaks, described counts peaks is for representing the maximum of described count value.Namely, when count mode is incremental count pattern, count value can be started from scratch and is gradually increased until counts peaks;When count mode is countdown pattern, count value can start to successively decrease until zero from counts peaks.
4th, set the first numerical value and second value.
Presetting the first numerical value, the first numerical value is for representing the waveform upset moment of the first PWM waveform, and the first numerical value is less than counts peaks.Preset described second value;In the present embodiment, second value is for representing the waveform upset moment of the second PWM waveform, and, second value is less than counts peaks.
So that when the complementary PWM waveform of output, just the complementary PWM waveform with Dead Time is exported, therefore, when setting the first numerical value and second value, need to take into account Dead Time so that the absolute difference between the first numerical value and second value is equal to Dead Time.Such as, counts peaks is 100, and the first numerical value is 45, and second value is 35, then Dead Time is equal to 10* machine time.Because enumerator is used for the machine cycle is counted, so, enumerator adds 1 every time, then it represents that through a machine cycle.
First carry out after process is finished in advance above-mentioned, it is possible to perform the Waveform output method that the application provides.As shown in Figure 6, this application provides a kind of Waveform output method, be applied to waveform generator, specifically include following steps:
Step S601: in the process machine cycle counted by count mode, when judging that count value reaches the first numerical value, controls the first PWM waveform and carries out level upset;Otherwise, the level controlling described first PWM waveform remains unchanged.
In waveform generator so that the machine cycle is counted, when count mode is incremental count pattern, often through a count cycle, count value adds one;When count mode is countdown pattern, often through a count cycle, count value subtracts one.
Undertaken in the process counted at waveform generator by count mode set in advance, count value and the first numerical value are contrasted, it is judged that whether count value is equal to the first numerical value.If so, then controlling the first PWM waveform and carry out level upset, otherwise, the level controlling the first PWM waveform remains unchanged.
Step S602: in the process machine cycle counted by count mode set in advance, when judging that described count value reaches second value, controls the second PWM waveform and carries out level upset;Otherwise, the level controlling described second PWM waveform remains unchanged.Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
Undertaken in the process counted at waveform generator by count mode set in advance, count value and second value are contrasted, it is judged that whether count value is equal to second value.If so, then controlling the second PWM waveform and carry out level upset, otherwise, the level controlling the second PWM waveform remains unchanged.
By counting means above, it is possible to find that the application has the advantages that
The Waveform output method that the application provides provides two numerical value, is the first PWM waveform and the first numerical value is set, be that the second PWM waveform arranges second value.Further, the first numerical value and second value are unequal, and both absolute difference are equal to Dead Time.Owing to Dead Time is taken into account by the first numerical value and second value, so, the first PWM waveform and the second PWM waveform that utilize the first numerical value and second value output have had Dead Time, namely while the complementary PWM waveform of output, Dead Time is just inserted, therefore, it is not necessary to module is inserted in recycling dead band is inserted into Dead Time.
Therefore, the application need not recycle dead band insertion module and be inserted separately into Dead Time, therefore, it is not necessary to individually designed dead band is inserted in module, Waveform generator and also need not be added dead band and insert module again, therefore can reduce the complexity of Waveform generator and improve formation efficiency.
Provided herein Waveform output method is described in detail below with specific embodiment.Referring to Fig. 7, export control process for waveform.Wherein, transverse axis is clock, the longitudinal axis is count value;First PWM waveform adopts PWM1 to represent, the second PWM waveform adopts PWM2 to represent.Assume that the original levels value of PWM1 be low level L, PWM2 original levels value is high level H;Counts peaks is P, and the first numerical value is P1, second value is P2;The initial pattern of count mode is incremental count pattern.
Referring to Fig. 7, owing to initial count mode is incremental count pattern, then count value starts to be gradually increased from 0.In the process of count, count value is constantly contrasted with the first numerical value P1 and second value P2.
In comparison process, before the T1 moment, count value is all inconsistent with the first numerical value P1 and second value P2, and therefore, before the T1 moment, PWM1 and PWM2 all remains unchanged.Being continuously increased along with count value, judge that count value is consistent with second value P2 in the T1 moment, therefore, control PWM2 and carry out level upset, PWM2 is converted to low level by high level.
During T1-T2, count value is all inconsistent with the first numerical value P1 and second value P2, and therefore, in during T1-T2, PWM1 and PWM2 all remains unchanged.Being continuously increased along with count value, judge that count value is consistent with the first numerical value P1 in the T2 moment, therefore, control PWM1 and carry out level upset, PWM1 is high level by low transition.
During T2-T3, count value is all inconsistent with the first numerical value P1 and second value P2, and therefore, in during T1-T2, PWM1 and PWM2 all remains unchanged.It is continuously increased along with count value, increases to counts peaks P in T3 moment count value, now control count mode and be changed to countdown pattern.
During T3-T4, count value is all inconsistent with the first numerical value P1 and second value P2, and therefore, in during T3-T4, PWM1 and PWM2 all remains unchanged.Constantly reducing along with count value, judge that count value is consistent with the first numerical value P1 in the T4 moment, therefore, control PWM1 and carry out level upset, PWM1 is converted to low level by high level.
During T4-T5, count value is all inconsistent with the first numerical value P1 and second value P2, and therefore, in during T4-T5, PWM1 and PWM2 all remains unchanged.Constantly reducing along with count value, judge that count value is consistent with second value P2 in the T5 moment, therefore, control PWM2 and carry out level upset, PWM2 is high level by low transition.
In the figure 7, the interval that dotted line represents is Dead Time, and the Waveform output method provided by the application can be inserted simultaneously into Dead Time at the complementary PWM waveform of output.Said process being a circulation, it is to be understood that waveform generator can continuously carry out said process, producing complementary PWM waveform thus circulating.
Fig. 7 complementation PWM waveform is analyzed, the wave period of PWM1 and PWM2 is the twice of counts peaks in period register, impact due to Dead Time, the dutycycle of the effective polarity of PWM1 (high level) is the twice that period register value deducts the first numerical value, the twice that dutycycle is second value of the effective polarity of PWM2 (high level).
The Waveform output method that the present embodiment provides can be inserted simultaneously into Dead Time at the complementary PWM waveform of output, insert module thus avoiding being separately provided dead band and in complementary PWM waveform, insert the situation of Dead Time, it is thus possible to improve with the formation efficiency of complementary PWM waveform of Dead Time and reduce Waveform generator complexity.
This application provides a kind of Waveform output device, including:
First processing unit, in the process machine cycle counted by count mode, when judging that count value reaches the first numerical value, controls the first PWM waveform and carries out level upset;Otherwise, the level controlling described first PWM waveform remains unchanged;
Second processing unit, in the process machine cycle counted by described count mode, when judging that described count value reaches second value, controls the second PWM waveform and carries out level upset;Otherwise, the level controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
Waveform generator internal software modules is described in detail below, referring to Fig. 8, this application provides a kind of Waveform output device, specifically include with lower module:
Period register the 61, first depositor the 62, second depositor the 63, first initial polarity depositor the 64, second initial polarity depositor 65, count mode depositor 66, counting module 67, comparison module 68, waveform control module 69.
Wherein, period register 61, for stored count peak value, counts peaks is for representing the maximum of counting module 67 count value.Counts peaks can be set by technical staff, and concrete numerical value is relevant with concrete condition, does not repeat them here.
First depositor 62, is used for storing the first numerical value.In the present embodiment, the first numerical value is for representing the waveform upset moment of the first PWM waveform.First numerical value can be set by technical staff, and the first numerical value is less than counts peaks.
Second depositor 63, is used for storing second value.In the present embodiment, second value is for representing the waveform upset moment of the second PWM waveform.Second value can by counting personnel setting, and second value is less than counts peaks.Further, counting personnel are when setting the first numerical value and second value, it is necessary to taken into account by Dead Time so that the product of the absolute difference between the first numerical value and second value and machine cycle is equal to Dead Time.
First initial polarity depositor 64, for storing the first original levels polarity of the first PWM waveform.The original levels polarity of the first PWM waveform can be high level or low level.
Second initial polarity depositor 65, for storing the second original levels polarity of the second PWM waveform.The original levels polarity of the second PWM waveform can be high level or low level.In order to ensure that the first PWM waveform and the second PWM waveform form complementary waveform, the first original levels polarity and the second original levels polarity are contrary, namely ensure that namely both initial times are complementary.
Count mode depositor 66, for the count mode of stored count module;Count mode can be incremented by count mode or countdown pattern.
Counting module 67, for counting the machine cycle according to the count mode set in described count mode depositor;The maximum of counting module 67 count value is the counts peaks set in period register 61.When the described count mode of described counting module 67 is incremental count pattern, when described count value reaches counts peaks set in advance by zero, the count mode controlling described count mode depositor is changed to countdown pattern;And, when the described count mode of described counting module is countdown pattern, when described count value reaches zero by counts peaks set in advance, the count mode controlling described count mode depositor is changed to incremental count pattern.
Comparison module 68, for the count value of described counting module being contrasted with storage the first numerical value in described first depositor, and contrasts the count value in described counting module 67 with the storage second value in described second depositor.
Waveform controls module 69, and for when described comparison module 68 judges that count value reaches the first numerical value, controlling the first PWM waveform and carry out level upset, the level otherwise controlling described first PWM waveform remains unchanged;When described comparison module 68 judges that count value reaches second value, controlling the second PWM waveform and carry out level upset, the level otherwise controlling described second PWM waveform remains unchanged.
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
By counting means above, it is possible to find that the application has the advantages that
The Waveform output method that the application provides provides two dutyfactor values, is the first PWM waveform and the first numerical value is set, be that the second PWM waveform arranges second value.Further, the first numerical value and second value are unequal, and both absolute difference are equal to Dead Time.Owing to Dead Time is taken into account by the first numerical value and second value, so, the first PWM waveform and the second PWM waveform that utilize the first numerical value and second value output have had Dead Time, namely while the complementary PWM waveform of output, Dead Time is just inserted, therefore, it is not necessary to module is inserted in recycling dead band is inserted into Dead Time.
Therefore, the application need not recycle dead band insertion module and be inserted separately into Dead Time, therefore, it is not necessary to individually designed dead band is inserted in module, Waveform generator and also need not be added dead band and insert module again, therefore can reduce the complexity of Waveform generator and improve formation efficiency.
If the function described in the present embodiment method is using the form realization of SFU software functional unit and as independent production marketing or use, it is possible to be stored in a computing equipment read/write memory medium.Based on such understanding, part or the part of this technical scheme that prior art is contributed by the embodiment of the present application can embody with the form of software product, this software product is stored in a storage medium, including some instructions with so that a computing equipment (can be personal computer, server, mobile computing device or the network equipment etc.) perform all or part of step of method described in each embodiment of the application.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (ROM, Read-OnlyMemory), the various media that can store program code such as random access memory (RAM, RandomAccessMemory), magnetic disc or CD.
Finally, it can further be stated that, in this article, the relational terms of such as first and second or the like is used merely to separate an entity or operation with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " includes ", " comprising " or its any other variant are intended to comprising of nonexcludability, so that include the process of a series of key element, method, article or equipment not only include those key elements, but also include other key elements being not expressly set out, or also include the key element intrinsic for this process, method, article or equipment.When there is no more restriction, statement " including ... " key element limited, it is not excluded that there is also other identical element in including the process of described key element, method, article or equipment.
In this specification, each embodiment adopts the mode gone forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment same or similar part mutually referring to.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the application.The multiple amendment of these embodiments be will be apparent from for those skilled in the art, and generic principles defined herein when without departing from spirit herein or scope, can realize in other embodiments.Therefore, the application is not intended to be limited to the embodiments shown herein, and is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (10)
1. a Waveform output method, it is characterised in that including:
In the process machine cycle counted by count mode, when judging that count value reaches the first numerical value, control the first PWM waveform and carry out level upset;Otherwise, the level controlling described first PWM waveform remains unchanged;
In the process machine cycle counted by described count mode, when judging that described count value reaches second value, control the second PWM waveform and carry out level upset;Otherwise, the level controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
2. the method for claim 1, it is characterised in that also include:
When described count mode is incremental count pattern, when described count value reaches counts peaks set in advance by zero, described count mode is changed to countdown pattern;
When described count mode is countdown pattern, when described count value reaches zero by counts peaks set in advance, described count mode is changed to incremental count pattern.
3. the method for claim 1, it is characterised in that before carrying out, by count mode, the process counted, also include:
Set the first original levels polarity of described first PWM waveform and the second original levels polarity of described second PWM waveform.
4. the method for claim 1, it is characterised in that before carrying out, by count mode, the process counted, also include:
Set described count mode as incremental count pattern or countdown pattern.
5. the method for claim 1, it is characterised in that before carrying out, by count mode, the process counted, also include:
Presetting described counts peaks, described counts peaks is for representing the maximum of described count value.
6. the method for claim 1, it is characterised in that before carrying out, by count mode, the process counted, also include:
Preset described first numerical value;Described first numerical value is for representing the dutyfactor value of described first PWM waveform;
Preset described second value;Described second value is for representing the dutyfactor value of described second PWM waveform.
7. a Waveform output device, it is characterised in that including:
First processing unit, in the process machine cycle counted by count mode, when judging that count value reaches the first numerical value, controls the first PWM waveform and carries out level upset;Otherwise, the level controlling described first PWM waveform remains unchanged;
Second processing unit, in the process machine cycle counted by described count mode, when judging that described count value reaches second value, controls the second PWM waveform and carries out level upset;Otherwise, the level controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
8. device as claimed in claim 7, it is characterised in that also include:
First changing unit, for when described count mode is incremental count pattern, when described count value reaches counts peaks set in advance by zero, being changed to countdown pattern by described count mode;
Second changing unit, for when described count mode is countdown pattern, when described count value reaches zero by counts peaks set in advance, being changed to incremental count pattern by described count mode.
9. a Waveform output device, it is characterised in that including:
Period register, for the counts peaks of stored count module;
First depositor, is used for storing the first numerical value;
Second depositor, is used for storing second value;Wherein, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of machine cycle;
First initial polarity depositor, for storing the first original levels polarity of the first PWM waveform;
Second initial polarity depositor, for storing the second original levels polarity of the second PWM waveform;
Count mode depositor, for the count mode of stored count module;
Counting module, for counting the machine cycle according to the count mode set in described count mode depositor;
Comparison module, for the count value of described counting module being contrasted with storage the first numerical value in described first depositor, and contrasts the count value of described counting module with the storage second value in described second depositor;
Waveform controls module, and for when described comparison module judges that count value reaches the first numerical value, controlling the first PWM waveform and carry out level upset, the level otherwise controlling described first PWM waveform remains unchanged;When described comparison module judges that count value reaches second value, controlling the second PWM waveform and carry out level upset, the level otherwise controlling described second PWM waveform remains unchanged;
Wherein, first original levels polarity of described first PWM waveform and the second original levels opposite polarity of described second PWM waveform, described first numerical value and described second value are unequal and be respectively less than counts peaks, further, described first numerical value and the absolute value of described second value difference are Dead Time set in advance with the product of described machine cycle.
10. device as claimed in claim 9, it is characterised in that
Described comparison module, it is additionally operable to when the described count mode of described counting module is incremental count pattern, when described count value reaches counts peaks set in advance by zero, the count mode controlling described count mode depositor is changed to countdown pattern;And, when the described count mode of described counting module is countdown pattern, when described count value reaches zero by counts peaks set in advance, the count mode controlling described count mode depositor is changed to incremental count pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610145936.2A CN105811937A (en) | 2016-03-15 | 2016-03-15 | Waveform output method and device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610145936.2A CN105811937A (en) | 2016-03-15 | 2016-03-15 | Waveform output method and device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105811937A true CN105811937A (en) | 2016-07-27 |
Family
ID=56467463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610145936.2A Pending CN105811937A (en) | 2016-03-15 | 2016-03-15 | Waveform output method and device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105811937A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107517049A (en) * | 2017-09-05 | 2017-12-26 | 郑州云海信息技术有限公司 | A kind of control method, system and the FPGA of multichannel PWM outputs |
CN111988021A (en) * | 2019-05-24 | 2020-11-24 | 北京车和家信息技术有限公司 | PWM generation method and device, motor controller and vehicle |
CN112688672A (en) * | 2019-10-17 | 2021-04-20 | 珠海零边界集成电路有限公司 | Apparatus and method for generating PWM wave |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1280418A (en) * | 1999-07-09 | 2001-01-17 | Lg产电株式会社 | Pulse width modulation control system |
US20120106217A1 (en) * | 2006-08-30 | 2012-05-03 | Daikin Industries, Ltd. | Current controlled power converter |
CN102904419A (en) * | 2012-09-25 | 2013-01-30 | 上海交通大学 | Three-phase PWM (Pulse-Width Modulation) wave FPGA (Field Programmable Gate Array) generating device |
-
2016
- 2016-03-15 CN CN201610145936.2A patent/CN105811937A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1280418A (en) * | 1999-07-09 | 2001-01-17 | Lg产电株式会社 | Pulse width modulation control system |
US20120106217A1 (en) * | 2006-08-30 | 2012-05-03 | Daikin Industries, Ltd. | Current controlled power converter |
CN102904419A (en) * | 2012-09-25 | 2013-01-30 | 上海交通大学 | Three-phase PWM (Pulse-Width Modulation) wave FPGA (Field Programmable Gate Array) generating device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107517049A (en) * | 2017-09-05 | 2017-12-26 | 郑州云海信息技术有限公司 | A kind of control method, system and the FPGA of multichannel PWM outputs |
CN111988021A (en) * | 2019-05-24 | 2020-11-24 | 北京车和家信息技术有限公司 | PWM generation method and device, motor controller and vehicle |
CN111988021B (en) * | 2019-05-24 | 2024-05-03 | 北京车和家信息技术有限公司 | PWM generation method and device, motor controller and vehicle |
CN112688672A (en) * | 2019-10-17 | 2021-04-20 | 珠海零边界集成电路有限公司 | Apparatus and method for generating PWM wave |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105811937A (en) | Waveform output method and device | |
CN101188384B (en) | Synchronization rectification and soft switch control circuit for power converter, and method thereof | |
CN104270007B (en) | Switching power supply circuit and method | |
US5506520A (en) | Energy conserving clock pulse generating circuits | |
CN105764204B (en) | A kind of PWM light-dimming methods and PWM light modulating devices | |
CN102969921A (en) | SVPWM (Space Vector Pulse Width Modulation) control method for Z-source inverter | |
CN105790738A (en) | Pulse Width Modulation Signal Generating Circuit and Method | |
CN102467889B (en) | Pwm signal generation circuit and method and LED drive circuit thereof | |
CN101860251B (en) | PWM (Pulse-Width Modulation) complementary output method of inserting variable dead zone time | |
CN104158420A (en) | Control method and system of three-phase three-level converter | |
CN103574706B (en) | Bull electromagnetic stove and method for heating and controlling thereof | |
CN106341106A (en) | Double sampling state retention flip-flop | |
CN104767431B (en) | A kind of control method, the device and system of the modulation of DC brushless motor pulse width | |
CN111934655B (en) | Pulse clock generation circuit, integrated circuit and related method | |
CN102810974B (en) | Detection pulse generator, control chip and switching power source | |
CN104205634B (en) | High Resolution pulse width modulation device | |
CN204350419U (en) | Many LED strip drive circuit | |
CN204068705U (en) | Switching power supply circuit | |
WO2022144004A1 (en) | Solar charging circuit, charging method, electronic device and storage medium | |
Yuan et al. | The principle and realization of single-phase SPWM wave based on the counter method | |
CN109149948A (en) | Storage medium, two-way resonance circuit output voltage adjusting method, apparatus and system | |
CN201207634Y (en) | Dead zone time modulation circuit and audio power amplifier | |
CN105185297B (en) | A kind of the pulse width modulation conduction method and system of LED displays driving | |
CN104640326B (en) | The high precision constant current LED drive circuit realized using digital method | |
CN101895253B (en) | Refrigeration control method realized by sinusoidal pulse width modulation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160727 |