CN105393649B - 用于制造印刷电路板元件的方法 - Google Patents
用于制造印刷电路板元件的方法 Download PDFInfo
- Publication number
- CN105393649B CN105393649B CN201480024834.4A CN201480024834A CN105393649B CN 105393649 B CN105393649 B CN 105393649B CN 201480024834 A CN201480024834 A CN 201480024834A CN 105393649 B CN105393649 B CN 105393649B
- Authority
- CN
- China
- Prior art keywords
- component
- composite bed
- insulating materials
- layer
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000002131 composite material Substances 0.000 claims abstract description 97
- 239000004020 conductor Substances 0.000 claims abstract description 50
- 239000011810 insulating material Substances 0.000 claims abstract description 46
- 239000004033 plastic Substances 0.000 claims abstract description 28
- 229920003023 plastic Polymers 0.000 claims abstract description 28
- 239000011888 foil Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 61
- 239000002313 adhesive film Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000010276 construction Methods 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229920001187 thermosetting polymer Polymers 0.000 claims description 8
- 239000002985 plastic film Substances 0.000 claims description 6
- 229920006255 plastic film Polymers 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 239000012811 non-conductive material Substances 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 150000002118 epoxides Chemical class 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims 1
- 230000035699 permeability Effects 0.000 claims 1
- 230000004888 barrier function Effects 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 238000003780 insertion Methods 0.000 description 8
- 230000037431 insertion Effects 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 239000012774 insulation material Substances 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 239000006071 cream Substances 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000002349 favourable effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000013067 intermediate product Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000012876 carrier material Substances 0.000 description 2
- 238000011437 continuous method Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229920002972 Acrylic fiber Polymers 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000009766 low-temperature sintering Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- -1 wherein Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0064—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a polymeric substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
- H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
- H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/27505—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8212—Aligning
- H01L2224/82136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/82138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
一种用于制造印刷电路板元件的方法,该印刷电路板元件具有至少一个电子的构件,所述构件具有由电触点或导电层定义的连接侧,并且所述构件连接到临时载体以进行定位并且嵌入绝缘材料中;构件直接设置在作为临时载体的塑料膜上的预定位置处,之后在构件的与所述塑料膜对置的一侧设置具有至少一个载体和导电体、优选还具有绝缘材料的复合层,所述载体背离构件,之后去除塑料膜;然后将构件嵌入绝缘材料中。优选在将构件嵌入绝缘材料中之后,在构件上与第一复合层对置的一侧并且在构件的嵌入部上施加另一个复合层。
Description
本发明涉及一种用于制造印刷电路板元件的方法,该印刷电路板元件具有至少一个电子构件,其具有由电触点或导电层定义的连接侧,其中,构件连接到临时载体以进行定位,并且嵌入绝缘材料中。
在设置有电子构件的设备的产品功能越来越多、而这样的电子构件越来越小型化以及要对印刷电路板装配的这样的电子构件的数量越来越大的情况下,在技术上越来越多地使用具有多个电子构件的性能更高的以阵列形状构造的单元或封装,其具有大量触点或接头,同时这些触点之间的距离越来越小。由于该原因,在产品尺寸、要使用的构件和印刷电路板同时减小的情况下,在需要的多个接触点上装配电子构件越来越难。
已经提出了将电子构件至少部分地集成到印刷电路板中,例如参见WO 03/065778A、WO 03/065779 A或WO 2004/077902 A。然而,在这些已知技术中不利的是,在印刷电路板的基体元件、即基板中要设置凹陷或孔、即空腔,用于容纳电子构件。为了接触构件,使用焊接工艺和粘接技术,其中,通常在不同的类型的材料之间产生接触点(一方面是导体迹线,另一方面是电子构件的接触点或连接点)。尤其在具有大的温差或温度变化范围的环境中使用这样的***的情况下,接触点或连接点的区域中的不同的材料由于不同的热膨胀系数而产生应力,其可能导致接触点或连接点开裂,由此导致单元发生故障。此外,可以假设,制造触点附加地需要的孔、尤其是激光孔对构件产生负荷。此外不利的是,***要产生的空腔中的构件通过焊膏和粘接线与导体迹线和接触表面的接触变得困难,或者尤其是在波动的温度负荷的情况下使用时,不能可靠地实现。印刷电路板制造过程期间的高压力和温度也可能对嵌入并接触的构件产生负荷。负荷可能更重的电子构件的散热也成问题。
在WO 2010/048654 A1中描述了一种用于将电子构件集成到印刷电路板中的技术,其中,借助胶将构件固定在稍后移除的优选施加有导电层的载体上。然后,将构件嵌入绝缘材料中,其上又施加有导电层。在这种构造中,绝缘层、例如预浸材料在加热时具有与胶不同的膨胀系数,从而在随后的加热和硬化步骤中,导致印刷电路板元件、尤其是在构件的区域中翘曲。这种翘曲例如可能处于大约150μm的数量级。此外,在借助微钻孔、即所谓的μvias接触构件时,也产生问题。
类似地也适用于在DE 10 2009 029 201 A1中描述的用于制造包括微米或纳米结构元件的构件的技术。在此使用经由连接层承载导电层的多层载体,例如尤其是所谓的RCC(树脂镀铜)膜,也就是说具有环氧树脂层和铜层,其中,铜层经由连接层连接到稍后移除的实际上是临时的载体。环氧树脂层和铜层保留在印刷电路板元件上。只要实际的载体仍然存在,则对这些层施加电子构件的组,之后用绝缘材料封装其。在此,在加热和硬化过程中由于不同的膨胀系数也导致所制造的印刷电路板元件的扭曲或翘曲。
现在,本发明所要解决的技术问题是至少尽可能地改善这些问题,并且能够制造尤其是在简化的接触的情况下也能够可靠地集成电子构件的印刷电路板或者印刷电路板元件。尤其是应当在制造印刷电路板期间实现一种结构,其相对于相应使用的材料实现对称性,从而能够在加热和加压或者硬化过程中避免印刷电路板的翘曲。此外,还旨在实现印刷电路板结构无气泡。
相应地,本发明提供一种如开头所给出的用于制造印刷电路板元件的方法,其特征在于,构件直接设置在作为临时载体的塑料膜上的预定位置处,之后在构件的与所述塑料膜对置的一侧设置具有至少一个载体和导电体、优选还具有绝缘材料的复合层,其中,载体背离构件,之后去除塑料膜,然后将构件嵌入绝缘材料中。
在从属权利要求中给出了该方法的有利实施方式和扩展方案。
在本方法中,不仅可以放弃使用印刷电路板的基板,在该基板中必须制造用于构件的腔室(空腔),而且还在印刷电路板的、更准确地说是包围电子构件的材料的可能的无故障方面实现了提高的可靠性,因为能够避免在其它情况下尤其在集成较大的构件时总是重复出现的气泡。这通过可以在真空下进行相应的加热或硬化或者层压步骤来实现,由此能够保持在材料内部无气泡;这种气泡的避免尤其在触点区域中是有利的。对于本方法还重要的是,整个临时载体在本方法期间又被移除,并且实现印刷电路板构造的对称结构,这显著地有助于避免所制造的印刷电路板在硬化步骤中由于在不同材料的情况下的不同的聚合收缩而扭曲。对于这种对称结构,相应地还特别有利的是,在将构件嵌入绝缘材料中之后,在构件上与第一复合层对置的一侧并且在构件的嵌入部上施加具有至少一个导电体和载体、优选还具有绝缘材料的另一个复合层。此外,利用这种方法还能够以有利的方式构造多层印刷电路板,由此在其中在多个平面内实现电路部分。
在此,“嵌入”不仅应当理解为仅在侧面对构件进行封装,还应当理解为包括覆盖的封装。
可以简单地使用本身是传统的粘接膜作为临时载体,其中,该粘接膜适宜地可以由例如具有丙烯酸塑料或硅酮的粘接层在例如由PET材料制成的载体层或者薄金属膜、例如铝上构造。这种粘接膜或者粘接带在市场上可以获得,并且也被称为“胶带”。
在嵌入电子构件的过程中(与根据DE 10 2009 029 201 A1类似),获得一种用于印刷电路板的“基体”。在将电子构件嵌入绝缘材料的步骤中,还可以在电子构件的背离“连接侧”的一侧覆盖该电子构件,但不一定必须这样做。在此,“连接侧”应当被理解为构件的电触点所在的或者至少大部分触点所在的构件侧,然后其中,虽然如此,在对置的一侧、即后侧,也可以存在导体层或金属化部,如下面将进一步详细说明的那样。
对于嵌入,一种有利的方法的特征在于,将构件嵌入作为绝缘材料的用于嵌入的经过预处理的预浸材料中,该预浸材料具有用于构件的凹陷。在此,援用在印刷电路板制造中常见的技术,因为经过预处理的预浸材料对于印刷电路板中的基板和绝缘层的构造通常完全是常用的。然而,在这种情况下,要在预浸材料中设置用于电子构件的凹陷、即所谓的“腔室”或空腔。
一种有利的备选方法的特征在于,将构件嵌入复合层的绝缘材料中,所述绝缘材料具有至少等于构件厚度的层厚。在此有利的是,单独地设置绝缘材料的独有步骤变得多余,因为复合层的绝缘材料直接用于电子构件的嵌入。
在本方法中还有利的是,在电子构件的连接侧可实现薄的绝缘层,其中,构件的触点和在印刷电路板元件完成时存在于那里的导电表面之间的绝缘层的相对小的厚度,使构件与结构化的导电表面的导电连接变得容易,由此能够实现较高的连接密度。
如果使用具有介电层的构件,所述介电层设置在构件的一侧,其中,该构件以与所述介电层对置的一侧设置在塑料膜上,则也可以以有利的方式实现构件的触点区域中的这种薄的绝缘层。因此在这种情况下,电子构件以连接侧向上远离临时载体地、即“面朝上”地设置在临时载体上。然后,在该侧施加尤其是没有绝缘材料的复合层,之后在构件的对置侧移除临时载体,以便随即能够从该侧将构件嵌入绝缘材料中以及优选设置另一复合层。
当在电子构件的一侧设置介电层时,存在如下可能性:将该介电层或绝缘材料层设置在“连接侧”或者构件的与触点对置的一侧,然后在该侧设置没有绝缘材料而仅具有载体和导体的复合层;之后如所描述的那样将临时载体从构件的连接侧去除,并且进行构件的封装或嵌入。
此外,本方法的一个有利实施方式的特征在于,使用具有导电层的构件,所述导电层设置在构件的一侧,其中,该构件以与所述导电层对置的一侧设置在塑料膜上。因此在该方法中,构件“面朝下”地设置在临时载体上。在构件的与触点对置的一侧上的导电层一方面可以用于接触构件,例如用作接地电极,并且另外还可以用于散热。在此,通常也优选在构件的承载该导电层的一侧设置没有绝缘材料、即仅具有载体和导体的复合层。
此外,如果在将由载体和导电体构成的复合层连接到构件之前,在该复合层上,例如通过印刷,在复合层的导电体上在构件的位置处施加例如膏状的导电材料,并且在将复合层连接到构件之后,去除塑料膜,则得到一种特别合理的方法。在该方法中,在与用于构件的临时载体对置的一侧设置具有局部的导电材料部分的复合层时,能够在同一个步骤中在电子构件的后侧进行金属化。
此外,还有利的是,在去除塑料膜之后,例如通过印刷在与构件的连接侧对置的一侧施加例如膏状的导电材料。在该方法中,在不同的处理步骤中实现更简单的配准,因为可以省略用于复合层的导体层的配准。
如所提到的,在本方法中,不同的加热和硬化或层压步骤可以在真空中进行,尤其是可以在真空中设置复合层,以便由此实现所希望的无气泡特性。
然后,在本方法中特别有利的是,在塑料膜上与构件同时地设置至少一个配准元件,用于在随后的方法步骤中使用。通过与电子构件同时地设置(装配)配准元件,不仅可以省去对传统的配准标记的配准步骤,而且还对于随后的处理步骤实现特别高的准确性。
为了补偿可能具有不同高度的待嵌入的电子构件和/或为了补偿这些电子构件的制造公差,根据另一优选实施方式提出了,连接塑料膜与可压缩材料。通过为临时载体设置至少部分地可压缩的材料,可以在设置或者处理多个电子构件时以简单并且可靠的方式考虑高度差,而不需要例如在制造设备上进行复杂的适配工作或者使用不同的原材料。
由于形状稳定性的原因,业已证明有利的是,复合层和/或另一复合层的载体由诸如金属的外形或尺寸稳定的材料、例如由铜、铝或者由尤其是具有UV可透过性的外形或尺寸稳定的聚合物形成。
对于层压过程,在复合层与构件和/或包围构件的层之间的尤其简单并且可靠的连接尤其有利的是,复合层和/或另一复合层的绝缘材料由粘度在连接到构件期间发生改变的材料、例如热固性塑料形成。在这种情况下,尤其建议,粘度发生改变的材料由在连接、尤其是层压处理之后硬化的热固性塑料形成。
为了在制造印刷电路板时,实现在进一步处理或加工步骤和/或在可能恶劣的环境条件下的其它使用期间的相应的机械强度和/或形状稳定性,还规定,复合层和/或另一复合层的绝缘材料由不可变形的介电材料形成,在所述不可变形的介电材料上设置由不导电材料形成的另一个层,所述不导电材料的粘度在连接到构件期间发生改变。这种尺寸稳定的材料赋予要制造的印刷电路板或印刷电路板中间产品足够的形状稳定性以及强度。
考虑到在制造印刷电路板的范围内出现的提高的温度,还有利地规定,选择具有高于220℃、尤其是高于250℃的熔点的材料,作为不可变形的介电材料。这些要求可以以简单并且可靠的方式来满足,例如方法是为绝缘材料选择硬化的热固性塑料、例如环氧化物,这对应于根据本发明的方法的另一优选实施方式。
在印刷电路板的厚度的最小化的意义上,还提出了复合层的导电层由具有小于20μm的厚度、尤其是具有10nm至10μm之间的厚度的金属、优选铜形成;为了制造这样薄的、尤其是在10nm或者几十纳米范围内的金属层,优选使用喷涂。
此外,在临时载体的尺寸稳定的设计的意义上,对于第一方法步骤中的操作还有利地规定,连接塑料膜与尺寸稳定的层、优选金属板,在使用可压缩材料的情况下,所述尺寸稳定的层可去除地设置在可压缩材料的背离构件的一侧。
在嵌入电子构件并且至少在电子构件的触点或导电表面的区域中连接到复合层之后,为了接触所嵌入的构件,优选规定,在电子构件与复合层以及必要时在另一侧与至少另一个复合层连接、尤其是层压之后,执行至少对复合体的至少一个导电层的结构化和/或与所嵌入的电子构件的触点或导电层的接触。这种接触通过本身已知的方法步骤来执行,其中,代替事后的结构化,例如还可以使用复合层的这些构造,在这些构造中例如导电层事先已经相应于待与其接触的电子构件进行结构化。
如已经叙述的,可以规定,提供多个可能具有不同的尺寸、尤其是不同的高度的电子构件。
以下根据在附图中示意性地示出的实施例进一步阐述本发明。在附图中:
图1a至图1g示出了根据本发明的用于将至少一个电子构件集成到印刷电路板或印刷电路板中间产品中的方法的连续的方法步骤;
图2a至图2d示出了根据本方法的另一实施方式制造印刷电路板元件时的连续的方法步骤;
图3a至图3c示出了另一变型的制造方法的步骤;
图4a至图4g示出了根据本方法的又一不同的实施方式的用于制造印刷电路板或印刷电路板元件的方法的步骤;
图5a至图5g示出了根据再一不同的制造方法的方法步骤;
图6a至图6g示出了按照根据本发明的又一变型的制造方法的连续的方法步骤;
图7示出了通过相对于根据图1至图6的实施方式变型的临时载体的示意性局部截面图,其中,进一步示意性地并且夸大地示出了该临时载体上的两个厚度不同的构件;以及
图8以局部截面图示意性地示出了具有复合层的实施例,该复合层具有作为绝缘材料的局部层、尺寸稳定层和可硬化层。
在图1a中可以看到,多个电子构件1布置在用于对电子构件1进行临时支撑的形式为塑料膜2、尤其是粘接膜2'(参见图7)的临时载体上,其中,电子构件1的触点3背离塑料膜2(所谓的“面朝上”位置)。代替所示出的触点3,也可以在背离塑料膜2的一侧设置要嵌入或者要集成的电子构件1的导电的、尤其是结构化的表面。为了简单起见,下面将构件1的该侧称为连接侧,但是其中,原则上对置的一侧也可以具有一个或多个触点或导体表面,例如作为接地连接。例如,IGBT构件在一侧具有源极和栅极连接,并且在对置的一侧具有漏极连接。
随后,根据在图1b中示出的方法步骤,在电子构件1上在触点3的一侧布置复合层4,其中,在图1b中示出的实施方式中,复合层4由不导电材料制成的层5(下面简称为绝缘材料5或介电层5)、导电材料制成的层6(下面简称为导体6)和载体层7(下面简称为载体7)构成。
复合层4能够同时以其绝缘材料5覆盖要嵌入或要集成的构件1。
随后,根据在图1c中示出的方法步骤,在复合层4和电子构件1之间进行连接。该连接例如可以通过层压来进行,其中为此,如示意性地示出的,可以使用加热的压力装置或冲头8,也可参考图1c中的示出加压的箭头P。
在将电子构件1连接到复合层4之后,尤其是在将触点3嵌入绝缘材料5中的情况下,移除塑料膜2,并且将获得的单元旋转180°,如在图1d中所示出的,以继续制造印刷电路板或者印刷电路板元件或中间产品。
相应地,在图1e中示出的方法步骤中可以看到,为了嵌入电子构件1,通过绝缘层9、例如通过设置例如由预浸料形成的其它层或层次9,对电子构件1进行封装,该预浸料设有与电子构件1的布置以及尺寸一致的相应凹槽或凹陷(空腔)10。
但是在此还可以想到,在仍然是液体的树脂中浇注构件1,随后将其硬化。
此外,当复合层4的绝缘或介电层5具有足够的厚度,即厚度至少等于构件1的厚度时,如在图1c中通过5A示意性地示出的,也已经可以在根据图1c的步骤中进行构件1的封装;因此在这种情况下,将每个构件1直接嵌入复合层4的绝缘材料或介电质5(或5A)中,也就是说,由此不需要诸如例如根据图1e的预浸材料9的单独的绝缘材料。
为了进一步构造要制造的印刷电路板,在图1f中可以看到,为了产生基本上对称的布置结构,在施加绝缘材料9或预浸料9之后,可以在构件1的背离触点3的一侧与复合层4类似地布置另一复合层11。与复合层4的构造尽可能一致地,该另一复合层11也包括不导电材料制成的层12、即绝缘层12、导电材料制成的层13、即导体13以及载体层14或简称为(可剥离或去除的)载体14。
该另一复合层11优选尽可能与复合层4相同(“镜像相同”)地构造,以便由此在图1f中示出的结构中实现对称性。这种对称构造在随后进行最终层压和硬化时非常有利,如在图1g中所示出的,以由此避免可能由于不同的聚合收缩造成的在对所有层进行硬化的层压过程中印刷电路板元件的弯曲或者“成碗状”或翘曲。在这种情况下,还有利的是,在本方法中完全移除临时载体,从而最后在构件1的两侧获得例如具有绝缘材料5或12以及导体6或13的对称结构。
在图1f中,示出了处于彼此连接、尤其是层压在一起的状态中的各个层或层次,从而整体上已经进行了构件1的相应嵌入。
为了进一步处理或加工要制造的印刷电路板,在图1g中可以看到,在移除相应的载体7或14之后,复合层的导电层6和13被结构化,其中,还可以看到与构件1的触点3的接触部15以及导电层6或13中的附加的通孔16。这种结构化或接触部本身被看作是已知的,因此对此不需要进一步讨论。
当然,在下面阐述的方法示例中也可以考虑这些其它方式。
利用上面(和下面)描述的方法,可以与构件1的大小无关地进行电子构件1在“印刷电路板”中的嵌入,此外尤其有利的是,不向印刷电路板中引入形成异物并且可能产生气泡的胶。构件1与复合层4或11的固定可以在真空中进行,其中,不需要溶剂并且避免了气泡。此外,在构件1的触点3和要与其(在结构化之后)连接的导体层6之间获得了较小的距离,这在布置用于接触的激光孔时是有利的。此外,在一个步骤中进行构件1与复合层4(还有11)的连接。总体上,通过所描述的方法能够获得相对特别薄的印刷电路板结构。
这些措施和优点也适用于下面描述的根据图2至图8的实施例。
在图2中的子图、即图2a至图2d中,如也在随后的图中所示的那样,用对应的附图标记表示与图1中的元件对应的元件,当存在变型时,在必要时设置撇号。
在图2中示出的方法又涉及将电子构件1相对于导体层6固定在固定位置,其中,同样要在施加介电材料的位置避免气泡。
在根据图2的方法中,电子构件1也“面朝上”、也就是说以连接侧向上地(与根据图1相同)施加在位于其下方的用作临时载体的塑料膜2、尤其是粘接膜上,参见图2a以及根据图2b的随后的方法步骤,在图2a中示出了构件1还在该粘接膜2上方一定距离处。与在根据图1的方法中不同地,随后接着在构件1的连接侧不施加三层的复合层4,而是施加两层的复合层4'。之所以这样设置是因为参见图2a,先前在构件1上在触点3上施加了绝缘层或介电层5',其中,其在此例如是无气泡的B阶段介电质(即部分硬化的热固性塑料的绝缘材料)。
根据图2c,在根据图2b将构件1固定在粘接膜2上之后,设置先前提到的具有导体层6和载体层7的两层的复合层4'。
构件1上的局部介电层5'可以特别薄,因此可以在构件1和复合层4'的导体层6之间实现尤其小的距离,这如所提到的那样在在稍后在钻出激光孔或导孔时接触连接部3的情况下特别有利。
复合层4'在构件1上、更准确地说在其薄介电层5'上的层压本身也可以利用构件1的指向下的连接侧、即“面朝下”地进行,也就是说通过在塑料膜2上施加具有介电层5'的构件1来进行。
此外,在根据图2的方法中,可以如前面根据图1d至图1g所进行的那样,也就是说在旋转该结构(参见图2d)并且去除临时载体(参见图2d中的箭头x)之后,将构件1嵌入绝缘材料、即预浸料9中,可以设置另一复合层11,同样也可以没有绝缘材料5,然后去除载体7或14。优选又在真空下进行层压或硬化,其中,应用提高的温度,以使介电质5'最终硬化。以这种方式,在构件1、介电层5'和导体层6或13之间实现无气泡的连接。之后,又将导体层6或13结构化,并且产生到构件1的连接部的触点。
在图3中示出的方法中,同样使用涂覆有介电质5'的电子构件1,然而与图2相比,该介电质5'现在分别位于与构件1的连接侧、即设置有触点3的一侧对置的一侧上。然后,将构件1“面朝下”、即以其触点3面对又用作临时载体的塑料膜或粘接膜2地固定在该临时载体上,参见图3a和3b。之后,根据如在图3c中示出的步骤,将两层的复合层4'、即没有根据图1的绝缘层5,施加并且层压在构件1背离粘接膜2的一侧上。然后,又可以将所获得的结构旋转180°,但是这在图3中未进一步示出;剥下或移除粘接膜2,并且随即可以在将构件1嵌入绝缘材料、如根据图1的预浸料9中之后,施加在此具有绝缘层12的附加的复合层11。
在图4的子图4a至4g中示出了用于制造印刷电路板或印刷电路板元件的本方法的另一变型,其中,使用构件1,在其与触点3对置的一侧涂覆有导电材料20,所述导电材料20同样可以无气泡地施加,并且形成部分硬化的(“B阶段”)层或者预干燥层(金属颗粒材料)。该构件1在此又“面朝下”地施加在作为临时载体设置的粘接膜2、通常为塑料膜2上,参见相比于图4a的图4b。之后,与在根据图3的实施例中类似,在构件1的对置的一侧在构件1的导电材料层20上施加具有导体6和载体7的两层的复合层4',参见图4c。然后,将该结构旋转180°,参见图4d,并且将用作临时载体的粘接膜2从构件1或其触点3上移除,参见图4d中的箭头x。之后,与在图1f和1g中已经示出并且根据这些图所描述的类似,又将构件1封装或嵌入绝缘材料例如预浸料9中,在绝缘材料中设置有凹槽或空腔,并且在其上施加具有绝缘材料12、导体13和载体14的附加的复合层11,参见图4f。随后,去除载体7或14,并且将绝缘材料9最终硬化,从而获得根据图4g的具有硬化的绝缘材料体9'的状态。之后还进行描述过的、在此未更详细地示出的导体结构化和接触。
在根据图4的方法中,也可以在真空下在提高的温度下进行层压,其中,在构件1、导电材料6或12和导体层20之间实现无气泡的连接。
构件1上的导电材料20可以由包含部分硬化(即处于B阶段)的树脂形式的粘合剂和金属粉末、例如银的带状材料获得。这种材料是无气泡的,并且被施加在构件1的“后侧”。该层20的材料在室温下不进行粘接,并且需要提高的温度以使其与金属层、即导体6连接。导电材料20可以在制造完成的印刷电路板中用于散热和/或用作触点,例如用于IGBT晶体管的漏电极。
根据图5的方法变型相对于根据图4的方法变型在如下方面进行了变型:现在,在将构件1以其触点3所在的一侧(即“面朝下”)施加在临时载体粘接膜2上(图5a)之后,将构件1连接到包含载体7和导体6的复合层4',其中,该复合层4'还在与电子构件1(在粘接膜2上)的位置对应的位置上设有导电材料20'或由该材料制成的相应子层20'。由导电材料制成的这些层20'在其构造或其结构以及其功能方面对应于如前面根据图4说明的层20,其中,在那里’将层20预先施加在构件1上,而不是复合层4'上。在将具有导电子层20'的复合层4'层压在构件1上(参见图5c)之后,又将所获得的结构旋转180°,参见图5d,并且将粘接膜2形式的临时载体移除,参见图5d中的箭头x。随后根据图5e、5f和5g的步骤对应于先前说明的步骤4e、4f和4g,因此可以省略重复的描述。
层或子层20或20'的导电材料例如也可以由包含金属粉末、例如银和粘合剂的膏构成,而不由带状材料构成。该膏可以通过热烧结。其可以预先通过印刷、例如丝网印刷、刻板印刷和类似的涂覆技术施加在导体层6上(或者构件1上)。该膏在提高的温度下被干燥,以去除粘合剂和溶剂。在该材料干燥之后,获得多孔结构。在真空中进行连接又防止在构件1和导电层20或20'之间的连接表面处注入气泡。在层压处理期间,通过应用压力和温度压缩该多孔结构,从而通过该低温烧结处理相应地形成固定的金属层。
在根据图6的方法变型中,在图6a至6d中示出的方法步骤实际上对应于根据图1a至1d的方法步骤,然而其中,在图6的子图中去除了冲头8(参见图1c)。在该方面,在此可以省略重复的说明。
在根据图6d的步骤之后,根据图6e,在构件1上,也就是说在构件1的与连接侧对置的一侧,施加由导电金属膏构成的层20”。如先前结合图5所描述的,干燥用于层20”的导电膏。
在首先将构件1连同层20”如所描述的嵌入预浸料绝缘材料9中之后,进行具有导体13和载体14(参见图6f)、即没有绝缘层12的附加的两层的复合层11'的层压。最后,在去除载体7和14之后,获得具有“印刷电路板体9'”的根据图6g的复合结构。
这种方法的优点是,配准处理步骤时的耗费减少。在根据图5的方法中,需要将具有固定在其上的构件1的临时载体与复合层4'上的导电膏20'对齐;与此相反,在图6的示例中,金属导电膏存在于构件1上,而省略了与导体层6的配准。
在对复合层11'进行加热和层压时,膏或层20'或20”的厚度有时收缩50%。
为了对要嵌入的构件1进行定位或配准,通常可以在临时载体上设置配准元件或标记。还特别有利的是,为了进行随后的处理步骤而设置如在图1a至1e中示意性地示出的配准元件17。即使在移除粘接膜2之后,这些配准元件17也保留在单元中。
除了这些配准元件17之外,也可以使用已经存在于塑料膜2上的构件1作为配置元件。
为了对构件1进行临时固定,如所说明的,载体塑料膜2优选设计为尤其是具有压敏胶的粘接带或粘接膜,这使得能够在例如在图1c中示出的方法步骤之后,以简单的方式可靠地定位并且临时固定构件1,以及随后简单地移除临时载体。另一方面,在构件1的可靠定位方面,为临时载体使用尽可能尺寸稳定的载体材料是有利的。
为了补偿要容纳的构件1的不同高度和必要时要容纳的构件1的尺寸的制造公差,还可能适宜的是,为临时载体配备使得能够压入较厚的构件1的可压缩材料。通过高度不同的构件1之间的这种补偿,在例如根据图1b和1c的随后的制造步骤中,能够准确地将构件1连接到共同的复合层4。
如先前所示出的临时载体的这种构造可以从图7中的图示中得到。在此示出的临时载体是具有包含粘接层21以及例如由PET材料制成的承载该粘接层21的载体层22的粘接膜2'形式的塑料膜的多层结构。作为胶,例如可以使用丙烯酸或硅酮材料。根据图7,在该粘接膜2'下方设置有例如由特氟隆材料制成的可压缩层23,其允许例如由于其结构或由于公差差异而具有例如较大的厚度的构件1'在一定程度上的压入。以这种方式,如在图7中用虚线示出的,可以在稍后的施加复合层4或4'的步骤中更容易地将该复合层4或4'施加在构件1、1'上的基本一致的水平上。
对于前面已经提到的良好的尺寸稳定性,在如在图7中示出的这种临时复合载体2的情况下,还可以施加尺寸稳定的层或层次25、例如金属片,并且在可压缩层23的下侧或外侧设置连接层24。所述连接层24优选由本身已知的可通过热或者通过UV辐射溶解的胶形成,其中,可以将尺寸稳定层25例如通过加热与粘接层或连接层24一起从临时载体的剩余部分上去除,之后可以将剩余的临时载体、即粘接层2'和可压缩材料层23从构件1(1')上去除,也就是说在如所描述的首先在构件1、1'的对置的一侧施加复合层4(或4')之后。在使用UV可溶解的胶的情况下,对于载体25使用UV可透过的材料,以便能够在层压过程之后进行去除。
对于其它处理或加工步骤期间的相应机械强度,优选复合层4的载体7还可以由相应尺寸稳定的材料构成,例如由铜、铝等金属构成,或者由尺寸稳定的聚合物构成。此外,还可以想到,在复合层4的绝缘材料层5的区域中(并且在复合层11中以对应的方式)***尺寸稳定的层。这在图8中以示意性的步骤示出,其中,在例如也可以用于在临时载体上嵌入构件1并且具有与此对应的厚度的绝缘材料层5C上方,设置由不可变形的介电材料构成的层5B。该不可变形的介电材料5B例如是具有高于220℃、尤其是高于250℃的熔点的材料。由此,在硬化真正的绝缘层5C时,该尺寸稳定的层5B不受影响。
为了实现要制造的印刷电路板的较小厚度,对于导体层6或者附加的导体层13选择相对小的厚度,所述厚度例如选择为小于20μm,尤其是在10nm和10μm之间。施加过程例如可以借助喷涂来进行。
为了保持构件1的相应接触或者构件1、尤其是具有触点3的表面与复合层4或11的绝缘层5或12之间的连接,该绝缘层5或12也可以由相应耐热的材料、例如硬化的热固性塑料、诸如环氧化物形成。通过将这种材料用于层5或12,也能够可靠地保持触点3和导体层6或13之间的希望的相应较小的距离,从而又能够相应地使印刷电路板的高度最小化。
补充地应当注意,在附图中示出的各个元件的尺寸关系或相对尺寸不是按比例绘制的。
利用本方法,也能够实现多层印刷电路板。通过多次重复在附图中示出和描述的方法步骤,可以获得多层印刷电路板,其中,能够以简单并且可靠的方式在不同的等级或平面内集成电子构件1。
Claims (31)
1.一种用于制造印刷电路板元件的方法,该印刷电路板元件具有至少一个电子的构件,所述构件具有由电触点或导电层定义的连接侧,其中,构件连接到临时载体以进行定位并且嵌入绝缘材料中,其特征在于,构件直接设置在作为临时载体的塑料膜上的预定位置处,之后在构件的与所述塑料膜对置的一侧设置具有至少一个载体和导电体的复合层,所述载体背离构件,之后去除塑料膜,然后将构件嵌入绝缘材料中。
2.根据权利要求1所述的方法,其特征在于,所述复合层还具有绝缘材料。
3.根据权利要求1所述的方法,其特征在于,在将构件嵌入绝缘材料中之后,在构件上与第一复合层对置的一侧并且在构件的嵌入部上施加具有至少一个导电体和载体的另一复合层。
4.根据权利要求3所述的方法,其特征在于,所述另一复合层还具有绝缘材料。
5.根据权利要求1所述的方法,其特征在于,使用粘接膜作为临时载体。
6.根据权利要求1所述的方法,其特征在于,将构件嵌入作为用于嵌入的绝缘材料使用的经过预处理的预浸材料中,该预浸材料具有用于构件的凹陷。
7.根据权利要求1所述的方法,其特征在于,将构件嵌入复合层的绝缘材料中,所述绝缘材料具有至少等于构件的厚度的层厚。
8.根据权利要求1至7中任一项所述的方法,其特征在于,使用具有介电层的构件,所述介电层设置在构件的一侧上,其中,该构件以与所述介电层对置的一侧设置在塑料膜上。
9.根据权利要求1至7中任一项所述的方法,其特征在于,使用具有导电层的构件,所述导电层设置在构件的一侧上,其中,该构件以与所述导电层对置的一侧设置在塑料膜上。
10.根据权利要求1至7中任一项所述的方法,其特征在于,在将由载体和导电体构成的复合层连接到构件之前,在该复合层上,通过印刷在复合层的导电体上在构件的位置处设置膏状的导电材料,并且在将复合层连接到构件之后,去除塑料膜。
11.根据权利要求1至7中任一项所述的方法,其特征在于,在去除塑料膜之后,通过印刷将膏状的导电材料施加在与构件的连接侧对置的一侧上。
12.根据权利要求1所述的方法,其特征在于,在真空中设置复合层。
13.根据权利要求1所述的方法,其特征在于,在塑料膜上与构件同时地设置至少一个配准元件,用于在随后的方法步骤中使用。
14.根据权利要求1所述的方法,其特征在于,将所述塑料膜与可压缩材料相连。
15.根据权利要求1所述的方法,其特征在于,将所述塑料膜与尺寸稳定的层相连,在使用可压缩材料的情况下,所述尺寸稳定的层可去除地设置在可压缩材料的背离构件的一侧上。
16.根据权利要求15所述的方法,其特征在于,所述尺寸稳定的层是金属板。
17.根据权利要求1所述的方法,其特征在于,复合层和/或另一复合层的载体由尺寸稳定的材料或者由尺寸稳定的聚合物构成。
18.根据权利要求17所述的方法,其特征在于,所述尺寸稳定的材料是金属。
19.根据权利要求18所述的方法,其特征在于,所述金属是铜或铝。
20.根据权利要求17所述的方法,其特征在于,所述尺寸稳定的聚合物具有UV通透性。
21.根据权利要求1所述的方法,其特征在于,复合层和/或另一复合层的绝缘材料由粘度在连接到构件期间发生改变的材料构成。
22.根据权利要求21所述的方法,其特征在于,所述粘度在连接到构件期间发生改变的材料是热固性塑料。
23.根据权利要求1所述的方法,其特征在于,复合层和/或另一复合层的绝缘材料由不可变形的介电材料构成,在所述不可变形的介电材料上设置由不导电材料制成的另一个层,所述不导电材料的粘度在连接到构件期间发生改变。
24.根据权利要求23所述的方法,其特征在于,选择具有高于220℃的熔点的材料,作为不可变形的介电材料。
25.根据权利要求23所述的方法,其特征在于,选择具有高于250℃的熔点的材料,作为不可变形的介电材料。
26.根据权利要求23至25中任一项所述的方法,其特征在于,所述绝缘材料具有被硬化为不可变形的材料的热固性塑料。
27.根据权利要求26所述的方法,其特征在于,所述被硬化为不可变形的材料的热固性塑料是环氧化物。
28.根据权利要求1所述的方法,其特征在于,在设置复合层和/或另一复合层之后,将其导电体结构化。
29.根据权利要求1所述的方法,其特征在于,在层压复合层和/或另一复合层之后,将其导电体结构化。
30.根据权利要求1所述的方法,其特征在于,在设置复合层和/或另一复合层之后,建立与构件的触点的接触连接。
31.根据权利要求1所述的方法,其特征在于,在层压复合层和/或另一复合层之后,建立与构件的触点的接触连接。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ATA50222/2013A AT514074B1 (de) | 2013-04-02 | 2013-04-02 | Verfahren zum Herstellen eines Leiterplattenelements |
ATA50222/2013 | 2013-04-02 | ||
PCT/AT2014/050066 WO2014161020A1 (de) | 2013-04-02 | 2014-03-17 | Verfahren zum herstellen eines leiterplattenelements |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105393649A CN105393649A (zh) | 2016-03-09 |
CN105393649B true CN105393649B (zh) | 2018-04-10 |
Family
ID=50513625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480024834.4A Active CN105393649B (zh) | 2013-04-02 | 2014-03-17 | 用于制造印刷电路板元件的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10426040B2 (zh) |
EP (1) | EP2982226B1 (zh) |
CN (1) | CN105393649B (zh) |
AT (1) | AT514074B1 (zh) |
WO (1) | WO2014161020A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3206229B1 (en) * | 2016-02-09 | 2020-10-07 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Methods of manufacturing flexible electronic devices |
WO2018172525A1 (en) * | 2017-03-24 | 2018-09-27 | Cardlab Aps | Assembly of a carrier and a plurality of electrical circuits fixed thereto, and method of making the same |
JP2022028180A (ja) * | 2020-08-03 | 2022-02-16 | 日本航空電子工業株式会社 | デバイス及びデバイスの製造方法 |
DE102022120293A1 (de) | 2022-08-11 | 2024-02-22 | Rolls-Royce Deutschland Ltd & Co Kg | Verfahren zur Herstellung einer Leiterplattenanordnung |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0647090A1 (en) * | 1993-09-03 | 1995-04-05 | Kabushiki Kaisha Toshiba | Printed wiring board and a method of manufacturing such printed wiring boards |
CN102656954A (zh) * | 2009-09-03 | 2012-09-05 | At&S奥地利科技及***技术股份公司 | 用于连接电路板的多个元件的方法、电路板以及这种方法的应用 |
CN102845140A (zh) * | 2010-04-13 | 2012-12-26 | At&S奥地利科技及***技术股份公司 | 用于将电子部件集成到印刷电路板中的方法以及具有在其中集成的电子部件的印刷电路板 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08167630A (ja) * | 1994-12-15 | 1996-06-25 | Hitachi Ltd | チップ接続構造 |
US6576494B1 (en) | 2000-06-28 | 2003-06-10 | Micron Technology, Inc. | Recessed encapsulated microelectronic devices and methods for formation |
US20030102572A1 (en) * | 2001-09-13 | 2003-06-05 | Nathan Richard J. | Integrated assembly protocol |
FI119215B (fi) * | 2002-01-31 | 2008-08-29 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli |
FI115285B (fi) * | 2002-01-31 | 2005-03-31 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi |
FI119583B (fi) * | 2003-02-26 | 2008-12-31 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
WO2005078789A1 (en) * | 2004-01-13 | 2005-08-25 | Infineon Technologies Ag | Chip-sized filp-chip semiconductor package and method for making the same |
JP2005347547A (ja) * | 2004-06-03 | 2005-12-15 | Inventic Corp | 半導体素子の接続リードの半田付けのショート防止方法 |
TWI251910B (en) | 2004-06-29 | 2006-03-21 | Phoenix Prec Technology Corp | Semiconductor device buried in a carrier and a method for fabricating the same |
TWI373113B (en) | 2008-07-31 | 2012-09-21 | Unimicron Technology Corp | Method of fabricating printed circuit board having semiconductor components embedded therein |
AT12316U1 (de) * | 2008-10-30 | 2012-03-15 | Austria Tech & System Tech | Verfahren zur integration eines elektronischen bauteils in eine leiterplatte |
US9324672B2 (en) * | 2009-08-21 | 2016-04-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package |
DE102009029201B4 (de) * | 2009-09-04 | 2019-05-09 | Robert Bosch Gmbh | Verfahren zur Herstellung eines ein mikro- oder nanostrukuriertes Bauelement umfassenden Bauteils |
KR101095130B1 (ko) * | 2009-12-01 | 2011-12-16 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
AT13055U1 (de) * | 2011-01-26 | 2013-05-15 | Austria Tech & System Tech | Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt |
US8487426B2 (en) * | 2011-03-15 | 2013-07-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with embedded die and manufacturing methods thereof |
-
2013
- 2013-04-02 AT ATA50222/2013A patent/AT514074B1/de not_active IP Right Cessation
-
2014
- 2014-03-17 CN CN201480024834.4A patent/CN105393649B/zh active Active
- 2014-03-17 EP EP14718312.3A patent/EP2982226B1/de active Active
- 2014-03-17 US US14/781,724 patent/US10426040B2/en not_active Expired - Fee Related
- 2014-03-17 WO PCT/AT2014/050066 patent/WO2014161020A1/de active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0647090A1 (en) * | 1993-09-03 | 1995-04-05 | Kabushiki Kaisha Toshiba | Printed wiring board and a method of manufacturing such printed wiring boards |
CN102656954A (zh) * | 2009-09-03 | 2012-09-05 | At&S奥地利科技及***技术股份公司 | 用于连接电路板的多个元件的方法、电路板以及这种方法的应用 |
CN102845140A (zh) * | 2010-04-13 | 2012-12-26 | At&S奥地利科技及***技术股份公司 | 用于将电子部件集成到印刷电路板中的方法以及具有在其中集成的电子部件的印刷电路板 |
Also Published As
Publication number | Publication date |
---|---|
CN105393649A (zh) | 2016-03-09 |
US10426040B2 (en) | 2019-09-24 |
EP2982226B1 (de) | 2016-08-17 |
AT514074A4 (de) | 2014-10-15 |
AT514074B1 (de) | 2014-10-15 |
WO2014161020A1 (de) | 2014-10-09 |
EP2982226A1 (de) | 2016-02-10 |
US20160044794A1 (en) | 2016-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5064210B2 (ja) | 電子モジュール及びその製造方法 | |
US11172572B2 (en) | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module | |
US20220053633A1 (en) | Embedding Component in Component Carrier by Component Fixation Structure | |
JP5160895B2 (ja) | 電子モジュールの製造方法 | |
US5224265A (en) | Fabrication of discrete thin film wiring structures | |
US7532453B2 (en) | Built-in capacitor type wiring board and method for manufacturing the same | |
US7229293B2 (en) | Connecting structure of circuit board and method for manufacturing the same | |
CN102090155B (zh) | 用于将至少一个电子构件集成到印制线路板中的方法以及印制线路板 | |
US9253888B2 (en) | Method for integrating an electronic component into a printed circuit board or a printed circuit board intermediate product, and printed circuit board or printed circuit board intermediate product | |
JP6103055B2 (ja) | 樹脂多層基板の製造方法 | |
US20100163168A1 (en) | Method for manufacturing wiring board with built-in component | |
CN103747616B (zh) | 元器件内置模块 | |
CN105393649B (zh) | 用于制造印刷电路板元件的方法 | |
US20100163172A1 (en) | Method for manufacturing wiring board with built-in component | |
KR20060066115A (ko) | 전자 모듈 제조 방법 | |
JP2010153498A (ja) | 樹脂封止パッケージ及びその製造方法 | |
CN103311222B (zh) | 半导体封装件及其形成方法 | |
EP2141973A1 (en) | Method of providing conductive structures in a multi-foil system and multi-foil system comprising same | |
US10455703B2 (en) | Method for producing a printed circuit board with an embedded sensor chip, and printed circuit board | |
US8677615B2 (en) | Method for embedding electrical components | |
JPH0563112B2 (zh) | ||
WO2013119643A1 (en) | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module | |
JP5456113B2 (ja) | 樹脂封止パッケージ | |
CN101682993B (zh) | 用于制造电子组件的方法以及电子组件 | |
JP2004111702A (ja) | 配線基板およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |