CN104966663A - LTPS film, preparation method thereof, and TFT - Google Patents
LTPS film, preparation method thereof, and TFT Download PDFInfo
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- CN104966663A CN104966663A CN201510268994.XA CN201510268994A CN104966663A CN 104966663 A CN104966663 A CN 104966663A CN 201510268994 A CN201510268994 A CN 201510268994A CN 104966663 A CN104966663 A CN 104966663A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 63
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005224 laser annealing Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 239000011248 coating agent Substances 0.000 claims description 43
- 238000000576 coating method Methods 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 239000010408 film Substances 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 25
- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 9
- 238000006356 dehydrogenation reaction Methods 0.000 claims description 4
- 229910002804 graphite Inorganic materials 0.000 claims description 4
- 239000010439 graphite Substances 0.000 claims description 4
- -1 graphite alkene Chemical class 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 129
- 239000007789 gas Substances 0.000 description 13
- 238000002425 crystallisation Methods 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000003595 mist Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000008025 crystallization Effects 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 9
- 229910002091 carbon monoxide Inorganic materials 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
- 210000002381 plasma Anatomy 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 238000001953 recrystallisation Methods 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 241000826860 Trapezium Species 0.000 description 2
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005660 chlorination reaction Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 229910000809 Alumel Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 238000004050 hot filament vapor deposition Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/02444—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
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Abstract
Provided is a LTPS film preparation method, comprising the steps of: forming a buffer layer on a substrate; performing composition processing on the buffer layer, and forming a groove on the buffer layer corresponding with a non-channel region; forming a graphene layer in the groove; depositing an amorphous silicon layer on the buffer layer; and performing laser annealing processing on the amorphous silicon layer to allow the amorphous silicon to form a p-Si layer. The LTPS film is provided with the graphene layer in the corresponding area of the no-channel region, and utilizes the thermal conductivity of grapheme to form a temperature gradient in the film, thereby ensuring that LTPS p-Si grains are larger and are uniformly distributed.
Description
Technical field
The present invention relates to technical field, particularly relate to preparation method and the thin-film transistor of a kind of low-temperature polysilicon film and thin-film transistor.
Background technology
Polysilicon (p-Si) film has much larger than amorphous silicon (a-Si) and the high carrier mobility intended with monocrystalline silicon comparability, normal replacement amorphous silicon is applied to the active layer of thin-film transistor (TFT), therefore shows in (AMLCD) and active organic LED (AMOLED) at the active liquid crystal of integrated peripheral drive and has very important application.The substrate of the polysilicon membrane of flat-panel monitor is the glass being difficult to bear high-temperature technology, and under the restriction of this condition, low temperature polycrystalline silicon (LTPS) technology is industry inevitable choice.
With regard to current technology, low-temperature polysilicon silicon technology mainly contains following several: short annealing solid phase crystallization method (RTA), quasi-molecule laser annealing crystallization method (ELA), metal induced lateral crystallization (MILC) and heated filament catalytic chemical gaseous phase deposition (Cat-CVD) etc.Wherein, ELA and MILC is that the use of current industrial circle is the most extensive.
ELA belongs to liquid phase recrystallization method, and polysilicon grain prepared by the method is large, and intercrystalline defect is few, and therefore its TFT device performance is superior, such as, has high field-effect mobility, low subthreshold value rolling values and low threshold voltage.The method that ELA makes low temperature polycrystalline silicon is on glass, grow a resilient coating, then grows amorphous silicon, and utilize excimer laser to scan amorphous silicon, amorphous silicon is subject to high temperature melting recrystallization and forms polysilicon.In ELA processing procedure, amorphous silicon becomes critical complete melting (nearly completely melts) state after being subject to high temperature, and then recrystallization forms polysilicon.Can according to low-yield to the crystallization of high-energy direction during recrystallization, low temperature is to the crystallization of high temperature direction.In prior art, amorphous silicon layer is directly formed on resilient coating, in the process of quasi-molecule laser annealing, the situation of being heated of amorphous silicon layer regional reaches unanimity, be in disorder in the starting point of recrystallization and the direction of growth of crystal grain, cause the low temperature polycrystalline silicon crystallite dimension after recrystallization less than normal, intercrystalline crystal boundary is on the high side, affect the electron mobility of polysilicon, and then affect the reaction speed of flat panel display.
Summary of the invention
Based on this, be necessary for the problems referred to above, a kind of low-temperature polysilicon film and preparation method thereof and thin-film transistor be provided, the crystal grain of the polysilicon of the low-temperature polysilicon film that this preparation method obtains is comparatively large, distribution uniform.
A preparation method for low-temperature polysilicon film, it comprises the steps:
Substrate forms resilient coating;
Patterning processes is carried out to described resilient coating, the described resilient coating that non-channel region is corresponding forms groove;
Graphene layer is formed in described groove;
Deposition of amorphous silicon layers on described resilient coating;
Laser annealing process is carried out to described amorphous silicon layer, makes described amorphous silicon layer form polysilicon layer.
Wherein in an embodiment, the step forming graphene layer in described groove comprises: deposited graphite alkene on described resilient coating, carries out etching processing to described Graphene, to retain Graphene corresponding to non-channel region, forms graphene layer.
Wherein in an embodiment, using plasma strengthens chemical vapor deposition method and deposits described graphene layer.
Wherein in an embodiment, described resilient coating comprises the silicon nitride layer and silicon oxide layer that stack gradually on the substrate.
Wherein in an embodiment, the degree of depth of described groove is less than the thickness of described silicon oxide layer.
Wherein in an embodiment, before laser anneal step is carried out to described amorphous silicon layer, also comprise and high temperature dehydrogenation is carried out to described amorphous silicon layer.
Wherein in an embodiment, described laser anneal step, adopts XeCl laser.
Wherein in an embodiment, the thickness of described amorphous silicon layer is 40 ~ 60nm.
A kind of low-temperature polysilicon film, described low-temperature polysilicon film adopts the arbitrary described preparation method of preceding claim to obtain.
A kind of thin-film transistor, it comprises above-mentioned low-temperature polysilicon film.
Above-mentioned low-temperature polysilicon film, owing to being provided with graphene layer in corresponding region, non-channel region, utilizes the thermal conductivity of Graphene formation temperature gradient in silicon thin film, and the crystal grain making the polysilicon of the low-temperature polysilicon film obtained is comparatively large, distribution uniform.
Accompanying drawing explanation
Fig. 1 is preparation method's schematic flow sheet of low-temperature polysilicon film in one embodiment of the invention;
Fig. 2 A-2E is respectively the structural representation of each step of the low-temperature polysilicon film shown in Fig. 1 in preparation process.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar improvement when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
A preparation method for low-temperature polysilicon film, comprises the steps: to form resilient coating on substrate; Patterning processes is carried out to described resilient coating, the described resilient coating that non-channel region is corresponding forms groove; Graphene layer is formed in described groove; Deposition of amorphous silicon layers on described resilient coating; Laser annealing process is carried out to described amorphous silicon layer, makes described amorphous silicon layer form polysilicon layer.
Refer to Fig. 1, it is the flow chart of low-temperature polysilicon film preparation method in one embodiment of the invention.
S110: form resilient coating on substrate.
Refer to Fig. 2 A, clean substrate 100 forms resilient coating 200, and substrate 100 can be glass substrate or flexible base, board.The resilient coating 200 formed can improve the degree of adhesion between amorphous silicon to be formed and substrate, is conducive to reducing heat-conduction effect, slows down by the cooldown rate of the silicon of LASER HEATING, is conducive to the crystallization of polysilicon.Meanwhile, can also prevent the metal ion in substrate from diffusing to active layer, reduce impurity defect, and the generation of leakage current can be reduced.
Particularly, utilize plasma chemical vapor deposition (PECVD) to deposit the certain thickness resilient coating of one deck on the glass substrate, such as, described certain thickness is 50 ~ 100nm.Deposition materials can be the silica (SiO of individual layer
x) rete or silicon nitride (SiN
x) rete, or be silica (SiO
x) and silicon nitride (SiN
x) lamination.In the present embodiment, refer to Fig. 2 A, resilient coating 200 comprises the silicon nitride layer 210 and silicon oxide layer 220 that stack gradually on the substrate 100, such as, silicon nitride layer 210 is arranged between substrate 100 and silicon oxide layer 220, is conducive to follow-up hydrogenation process like this, and obtains good electric property.Particularly, the thickness of described silicon nitride and silicon oxide stack is 50 ~ 100nm.And for example, silicon nitride layer 210 is 1 ~ 1.5:0.8 ~ 1.6 with the thickness proportion of silicon oxide layer 220; Such as, silicon nitride layer 210 is 1:1 with the thickness proportion of silicon oxide layer 220.Such as, the thickness of silicon oxide layer is 20 ~ 60nm.
Wherein, SiN is formed
xthe reacting gas of rete is SiH
4, NH
3, N
2mist, or be SiH
2cl
2, NH
3, N
2mist; Form SiO
xthe reacting gas of rete is SiH
4, N
2the mist of O, or be SiH
4, silester (TEOS) mist.
S120, patterning processes is carried out to resilient coating, the resilient coating that non-channel region is corresponding forms groove.
Refer to Fig. 2 B, by patterning processes, the resilient coating 200 corresponding to non-channel region carries out partial etching, to make resilient coating 200 to be formed patterned groove 221, concrete, the region that described groove is corresponding is the non-channel region of active layer in thin-film transistor to be formed.Such as, dry etching is carried out to the resilient coating of non-channel region, removes the resilient coating of corresponding region, non-channel region, to make resilient coating to be formed patterned groove structure.The figure of pre-groove structure.And for example, the etching gas that described dry etching adopts comprises Ar, O
2, CO, CO
2, H
2, SF
6, C
xf
yor C
xf
yh
zin one or several.And for example, the etching gas that described dry etching adopts comprises Ar, O
2, CO, CO
2, H
2, SF
6, CF
4or CHF
3in one or several.
And for example, the degree of depth of described groove is less than the thickness of described silicon oxide layer.And for example, the degree of depth of described groove is 1 ~ 10nm, and and for example, the degree of depth of described groove is 2 ~ 8nm.And for example, the degree of depth of described groove is 4 ~ 5nm.And for example, the cross section of described groove is trapezium structure, and the width of the openend of described groove is greater than the width of bottom.And for example, the cross section of described groove is rectangular configuration.
S130, in groove, form graphene layer.
Refer to Fig. 2 C, in groove 221, fill Graphene, form graphene layer 230.Such as, deposited graphite alkene on described resilient coating, carries out etching processing to described Graphene, to retain Graphene corresponding to non-channel region, forms graphene layer.And for example, using plasma enhancing chemical vapor deposition method deposits described graphene layer.And for example, stripping preparation method is adopted to form described graphene layer.And for example, utilize chemical vapour deposition technique to grow multi-layer graphene continuously on the metallic substrate, then metal substrate is fallen as sacrifice layer corrosion, multi-layer graphene is attached in described groove.And for example, described graphene layer is the Graphene of p-type doping.
Such as, described graphene layer is the Graphene of 3 ~ 15 layers.And for example, described Graphene is 5 ~ 10 layer graphenes.And for example, the thickness of described graphene layer is identical with the degree of depth of described groove, that is, described Graphene flushes with described groove top; And for example, the thickness of described graphene layer is 60% ~ 90% of the degree of depth of described groove, like this, is conducive to efficiently filling Graphene, enhances productivity.Certainly, according to actual conditions, the thickness of graphene layer can also be adjusted.
S140, on the buffer layer deposition of amorphous silicon layers.
Refer to Fig. 2 D, deposition of amorphous silicon layers 300 on resilient coating 200.Such as, using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique deposition of amorphous silicon layers on the insulating layer.And for example, depositing temperature general control is below 500 DEG C.
In the present embodiment, the thickness of amorphous silicon layer is 40nm ~ 60nm.Certainly, also can need according to concrete technique to select suitable thickness.Such as, the thickness of amorphous silicon layer is 42nm ~ 55nm, and and for example, the thickness of amorphous silicon layer is 45nm, 48nm, 50nm, 51nm, 52nm or 54nm.
S150, laser annealing process is carried out to amorphous silicon layer, make amorphous silicon layer form polysilicon layer.
Refer to Fig. 2 E, laser annealing process is carried out to amorphous silicon layer 300, make amorphous silicon layer 300 form polysilicon layer 400.
Such as, laser annealing can adopt the excimer lasers such as chlorination xenon (XeCl), KrF (KrF), argon fluoride (ArF).In the present embodiment, wavelength is adopted to be that the XeCl laser of 308nm is to carry out quasi-molecule laser annealing.Laser beam is linear light sorurce after optical system.
Such as, the pulse recurrence rate (pulse repetition ratio) of quasi-molecule laser annealing is 300Hz ~ 800Hz, and and for example, the pulse recurrence rate of quasi-molecule laser annealing is 400Hz ~ 600Hz; And for example, sweep span (scanpitch) is 15 μm ~ 30 μm; And for example, laser energy density is 250 ~ 600mJ/cm
2, and for example, laser energy density is 350 ~ 500mJ/cm
2; And for example, sweep speed is preferably 0.5mm/s ~ 50mm/s, and and for example, sweep speed is 1mm/s ~ 30mm/s, and and for example, sweep speed is 2mm/s ~ 10mm/s.
Preferably, before carrying out laser annealing technique, need to carry out dehydrogenation to amorphous silicon layer, make hydrogen content be down to less than 2%, prevent the generation of the quick-fried phenomenon of hydrogen.Such as, thermal anneal process is adopted to be got rid of from this crystallization predecessor by hydrogen.
Laser irradiates solid-state amorphous silicon film, and it is heat energy that silicon absorbs light energy conversion, from solid state transformed be complete molten condition; During the postradiation crystallisation by cooling of light, because graphene layer has good heat conductivility, the non-channel region of silicon thin film is in non-fully molten condition, and the channel region of silicon thin film is then in complete molten condition; Under the effect of temperature gradient power, the solid-liquid face of silicon thin film crystallization is constantly advanced to channel region by the non-channel region of both sides, thus realizes the super transverse crystallization of silicon crystal grain, obtains the large and polysilicon layer be evenly distributed of crystallite dimension.
Above-mentioned low-temperature polysilicon film, owing to being provided with graphene layer in corresponding region, non-channel region, utilizes the thermal conductivity of Graphene formation temperature gradient in silicon thin film, and the crystal grain making the polysilicon of the low-temperature polysilicon film obtained is comparatively large, distribution uniform.
The present invention also provides the low-temperature polysilicon film obtained by a kind of above-mentioned preparation method, and this low-temperature polysilicon film not only can be used for the making of thin-film transistor, and can be used for solar cell material, or in the making of other semiconductor device.
Another embodiment of the present invention also provides a kind of preparation method of thin-film transistor, and it comprises the steps:
S210, on substrate, form resilient coating.
Such as, plasma chemical vapor deposition (PECVD) is utilized to deposit the certain thickness resilient coating of one deck on the glass substrate.Deposition materials can be the silica (SiO of individual layer
x) rete or silicon nitride (SiN
x) rete, or be silica (SiO
x) and silicon nitride (SiN
x) lamination.In the present embodiment, described resilient coating comprises and is sequentially laminated on silicon nitride layer on substrate and silicon oxide layer, is conducive to follow-up hydrogenation process like this, and obtains good electric property.Particularly, the thickness of described silicon nitride is 50 ~ 100nm, and the thickness of described silica is 150 ~ 300nm.Wherein, SiN is formed
xthe reacting gas of rete is SiH
4, NH
3, N
2mist, or be SiH
2cl
2, NH
3, N
2mist; Form SiO
xthe reacting gas of rete is SiH
4, N
2the mist of O, or be SiH
4, silester (TEOS) mist.
S220, patterning processes is carried out to resilient coating, the resilient coating that non-channel region is corresponding forms groove.
Such as, by patterning processes, the resilient coating corresponding to non-channel region carries out partial etching, to make resilient coating to be formed patterned groove, concrete, and the region that described groove is corresponding is the non-channel region of active layer in thin-film transistor to be formed.Such as, dry etching is carried out to the resilient coating of non-channel region, removes the resilient coating of corresponding region, non-channel region, to make resilient coating to be formed patterned groove structure.And for example, the etching gas that described dry etching adopts comprises Ar, O
2, CO, CO
2, H
2, SF
6, C
xf
yor C
xf
yh
zin one or several.And for example, the etching gas that described dry etching adopts comprises Ar, O
2, CO, CO
2, H
2, SF
6, CF
4or CHF
3in one or several.
And for example, the degree of depth of described groove is less than the thickness of described silicon oxide layer.And for example, the degree of depth of described groove is 1 ~ 10nm, and and for example, the degree of depth of described groove is 2 ~ 8nm.And for example, the degree of depth of described groove is 4 ~ 5nm.And for example, the cross section of described groove is trapezium structure, and the width of the openend of described groove is greater than the width of bottom.And for example, the cross section of described groove is rectangular configuration.
S230, in groove, form graphene layer.
Such as, deposited graphite alkene in described buffering, carries out etching processing to described Graphene, to retain Graphene corresponding to non-channel region, forms graphene layer.And for example, using plasma enhancing chemical vapor deposition method deposits described graphene layer.And for example, stripping preparation method is adopted to form described graphene layer.And for example, utilize chemical vapour deposition technique to grow multi-layer graphene continuously on the metallic substrate, then metal substrate is fallen as sacrifice layer corrosion, multi-layer graphene is attached in described groove.And for example, described graphene layer is the Graphene of p-type doping.
Such as, described graphene layer is the Graphene of 3 ~ 15 layers.And for example, described Graphene is 5 ~ 10 layer graphenes.And for example, the thickness of described graphene layer is identical with the degree of depth of described groove, that is, described Graphene flushes with described groove top.Certainly, according to actual conditions, the thickness of graphene layer can also be adjusted.
S240, on the buffer layer deposition of amorphous silicon layers, and laser annealing process is carried out to amorphous silicon layer, make amorphous silicon layer form polysilicon layer.
Such as, using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique deposition of amorphous silicon layers on the insulating layer.And for example, depositing temperature general control is below 500 DEG C.
In the present embodiment, the thickness of amorphous silicon layer is 40nm ~ 60nm.Certainly, also can need according to concrete technique to select suitable thickness.Such as, the thickness of amorphous silicon layer is 42nm ~ 55nm, and and for example, the thickness of amorphous silicon layer is 45nm, 48nm, 50nm, 51nm, 52nm or 54nm.
Such as, laser annealing can adopt the excimer lasers such as chlorination xenon (XeCl), KrF (KrF), argon fluoride (ArF).In the present embodiment, wavelength is adopted to be that the XeCl laser of 308nm is to carry out quasi-molecule laser annealing.Laser beam is linear light sorurce after optical system.
Such as, the pulse recurrence rate (pulse repetition ratio) of quasi-molecule laser annealing is 300Hz ~ 800Hz, and and for example, the pulse recurrence rate of quasi-molecule laser annealing is 400Hz ~ 600Hz; And for example, sweep span (scanpitch) is 15 μm ~ 30 μm; And for example, laser energy density is 250 ~ 600mJ/cm
2, and for example, laser energy density is 350 ~ 500mJ/cm
2; And for example, sweep speed is preferably 0.5mm/s ~ 50mm/s, and and for example, sweep speed is 1mm/s ~ 30mm/s, and and for example, sweep speed is 2mm/s ~ 10mm/s.
Preferably, before carrying out laser annealing technique, need to carry out dehydrogenation to amorphous silicon layer, make hydrogen content be down to less than 2%, prevent the generation of the quick-fried phenomenon of hydrogen.Such as, thermal anneal process is adopted to be got rid of from this crystallization predecessor by hydrogen.
S250, patterning processes is carried out to polysilicon layer, be formed with active layer.
Such as, particularly, it comprises the following steps:
S251, utilize photoetching process to form mask, adopt dry etching method to form figure, form the active layer comprising source region, drain region and channel region, namely the active layer of graphene layer corresponding region is the active layer in source region to be formed or drain region.
S252, ion implantation is carried out to active layer, realize channel doping.
The object of adulterating to raceway groove is the threshold voltage in order to adjusting means.Such as, when needing the threshold voltage of thin-film transistor to move to positive direction, boron element doping is carried out to active layer; When needing the threshold voltage of thin-film transistor to move to negative direction, P elements doping or arsenic element doping are carried out to active layer; And if do not need adjusting threshold voltage according to technique, then do not need that ion implantation is carried out to active layer and realize channel doping.
S260, on active layer deposition of gate insulating barrier.
Such as, adopt chemical gaseous phase depositing process, the substrate defining active layer forms gate insulator.And for example, depositing temperature general control is below 500 DEG C.And for example, the thickness of gate insulator can be 80 ~ 200nm, also can need to select suitable thickness according to concrete technology.And for example, gate insulator adopts silica, the silicon nitride of individual layer, or the lamination of the two.
S270, on gate insulator deposition of gate metal level, by patterning processes, formed grid.
Such as, adopt the method deposition of gate metal levels such as sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapour deposition (CVD) (LPCVD), Films Prepared by APCVD (APCVD), electron cyclotron resonance microwave plasmas chemical vapour deposition (CVD) (ECR-CVD), then, mask plate (mask) is utilized to carry out exposing, develop and etching, gate metal layer is graphical, form grid.
Such as, the material of gate metal layer is the metal or alloy such as molybdenum, aluminium, chromium, copper, alumel and molybdenum and tungsten alloy, and for example, uses the combination of above-mentioned different materials.In the present embodiment, the thickness of gate metal layer is 100 ~ 800nm, and certainly, the thickness of gate metal layer also can need to select suitable thickness according to concrete technology.
S280, using grid as mask, ion implantation is carried out to the non-channel region of active layer, form source region and drain region.
Such as, the ion implantation mode with mass-synchrometer is adopted in the present embodiment.And for example, according to design needs, injected media is the gas containing boron element and/or phosphorus element-containing, to form P type or N-type TFT.Such as, adopt containing boron element, as with B
2h
6/ H
2mist be injected media, such as, B
2h
6with H
2ratio be 1% ~ 30%; Implantation Energy scope is 5 ~ 50KeV, and preferred energy range is 20 ~ 30KeV; Implantation dosage scope is 1 × 10
13~ 1 × 10
17atoms/cm
3, preferably, implantation dosage scope is 5 × 10
14~ 5 × 10
15atoms/cm
3; And for example, phosphorus element-containing is adopted, as with PH
3/ H
2mist as injected media.As with PH
3/ H
2mist be injected media, such as, PH
3with H
2ratio be 1% ~ 30%; Implantation Energy scope is 20 ~ 110KeV, and preferred energy range is 50 ~ 70KeV; Implantation dosage scope is 1 × 10
13~ 1 × 10
17atoms/cm
3, preferably, implantation dosage scope is 5 × 10
14~ 5 × 10
15atoms/cm
3.
S290, on grid deposit passivation layer, and form via hole at gate insulator and passivation layer, and make source electrode and drain electrode.
Particularly, can be the passivation layer of 200nm ~ 800nm by chemical vapor deposition method deposit thickness, such as, passivation layer is oxide, nitride or oxynitrides, and and for example, passivation layer is single layer structure or sandwich construction, and for example, the gas forming passivation layer is SiH
4, NH
3, N
2or SiH
4, N
2o.
Such as, adopt the method for dry etching, form mask with photoetching process, passivation layer and gate insulator form via hole to expose source region and drain region.Wherein, in dry etch process, the gas containing fluorine element or chloride element can be adopted, as SF
6, CF
4, CHF
3, CCl
2f
2deng gas or These gases and O
2mist as etch media, adopt reactive ion etching method, plasma etching method or inductively coupled plasma etching method to etch.
Particularly, above passivation layer, adopt sputtering mode, thermal evaporation methods or plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, sub-atmospheric CVD mode or electron cyclotron resonance chemical vapour deposition (CVD) mode to form metal level.Above metal level, adopt photoetching process to form photolithographic mask with photoresist, and adopt wet etching or dry etching to form the figure comprising source electrode and drain electrode.
Due to the cooling recrystallization stage at silicon thin film, the solid-liquid face of polysilicon grain advances from low-temperature region to high-temperature area, in the crystallization time that laser annealing technique is limited, polysilicon grain larger in its crystallite dimension of incipient stage, distribution also more orderly; Therefore, in the manufacturing process of above-mentioned thin-film transistor, the resilient coating of the source region of active layer and corresponding region, drain region is provided with graphene layer, utilize the thermal conductivity of Graphene formation temperature gradient in silicon thin film, to make, the polysilicon grain of the active layer channel region in close source region and drain region is comparatively large, distribution is also more orderly, and then improve active layer channel region carrier mobility and reduce its leakage current, thus improve the quality of thin-film transistor.In addition, Graphene is a kind of semiconductor not having energy gap, has higher carrier mobility, and therefore Graphene can be used as a part for active layer, to improve the carrier mobility of whole thin-film transistor.
The present invention also provides a kind of thin-film transistor, comprises thin-film transistor prepared by said method.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a preparation method for low-temperature polysilicon film, is characterized in that, comprises the steps:
Substrate forms resilient coating;
Patterning processes is carried out to described resilient coating, the described resilient coating that non-channel region is corresponding forms groove;
Graphene layer is formed in described groove;
Deposition of amorphous silicon layers on described resilient coating;
Laser annealing process is carried out to described amorphous silicon layer, makes described amorphous silicon layer form polysilicon layer.
2. preparation method according to claim 1, it is characterized in that, the step forming graphene layer in described groove comprises: deposited graphite alkene on described resilient coating, carries out etching processing to described Graphene, to retain Graphene corresponding to non-channel region, form graphene layer.
3. preparation method according to claim 2, is characterized in that, using plasma strengthens chemical vapor deposition method and deposits described graphene layer.
4. preparation method according to claim 1, is characterized in that, described resilient coating comprises the silicon nitride layer and silicon oxide layer that stack gradually on the substrate.
5. preparation method according to claim 4, is characterized in that, the degree of depth of described groove is less than the thickness of described silicon oxide layer.
6. preparation method according to claim 1, is characterized in that, before carrying out laser anneal step, also comprises and carries out high temperature dehydrogenation to described amorphous silicon layer described amorphous silicon layer.
7. preparation method according to claim 1, is characterized in that, described laser anneal step, adopts XeCl laser.
8. preparation method according to claim 1, is characterized in that, the thickness of described amorphous silicon layer is 40 ~ 60nm.
9. a low-temperature polysilicon film, is characterized in that, described low-temperature polysilicon film adopts arbitrary described preparation method in claim 1 ~ 8 to obtain.
10. a thin-film transistor, is characterized in that, comprises low-temperature polysilicon film as claimed in claim 9.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206257A (en) * | 2016-08-12 | 2016-12-07 | 昆山国显光电有限公司 | The method preparing low-temperature polysilicon film and transistor |
| CN106356287A (en) * | 2016-09-29 | 2017-01-25 | 昆山国显光电有限公司 | Preparation method for low-temperature polycrystalline silicon thin film and semiconductor structure |
| WO2018145515A1 (en) * | 2017-02-09 | 2018-08-16 | 京东方科技集团股份有限公司 | Thin film transistor and fabrication method therefor, display substrate and display device |
| WO2018214119A1 (en) * | 2017-05-25 | 2018-11-29 | 华为技术有限公司 | Graphene field-effect transistor and preparation method therefor |
| CN109817644A (en) * | 2019-01-30 | 2019-05-28 | 武汉华星光电半导体显示技术有限公司 | A kind of tft array substrate and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080182392A1 (en) * | 2007-01-29 | 2008-07-31 | Innolux Display Corp. | Method for fabricating polysilicon layer with large and uniform grains |
| CN102856173A (en) * | 2012-09-29 | 2013-01-02 | 京东方科技集团股份有限公司 | Polycrystalline silicon film, preparation method thereof, array substrate and display device |
| CN103730336A (en) * | 2013-12-30 | 2014-04-16 | 深圳市华星光电技术有限公司 | Method for defining growth direction of polycrystalline silicon |
| CN103972050A (en) * | 2014-05-14 | 2014-08-06 | 京东方科技集团股份有限公司 | Preparation method of polycrystalline silicon thin film, polycrystalline silicon thin film transistor and array substrate |
| CN104037066A (en) * | 2014-06-25 | 2014-09-10 | 深圳市华星光电技术有限公司 | Method for defining growth direction of polycrystalline silicon |
| CN104465401A (en) * | 2014-12-15 | 2015-03-25 | 信利（惠州）智能显示有限公司 | Thin film transistor low-temperature polycrystalline silicon thin film manufacturing method |
-
2015
- 2015-05-22 CN CN201510268994.XA patent/CN104966663B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080182392A1 (en) * | 2007-01-29 | 2008-07-31 | Innolux Display Corp. | Method for fabricating polysilicon layer with large and uniform grains |
| CN102856173A (en) * | 2012-09-29 | 2013-01-02 | 京东方科技集团股份有限公司 | Polycrystalline silicon film, preparation method thereof, array substrate and display device |
| CN103730336A (en) * | 2013-12-30 | 2014-04-16 | 深圳市华星光电技术有限公司 | Method for defining growth direction of polycrystalline silicon |
| CN103972050A (en) * | 2014-05-14 | 2014-08-06 | 京东方科技集团股份有限公司 | Preparation method of polycrystalline silicon thin film, polycrystalline silicon thin film transistor and array substrate |
| CN104037066A (en) * | 2014-06-25 | 2014-09-10 | 深圳市华星光电技术有限公司 | Method for defining growth direction of polycrystalline silicon |
| CN104465401A (en) * | 2014-12-15 | 2015-03-25 | 信利（惠州）智能显示有限公司 | Thin film transistor low-temperature polycrystalline silicon thin film manufacturing method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206257A (en) * | 2016-08-12 | 2016-12-07 | 昆山国显光电有限公司 | The method preparing low-temperature polysilicon film and transistor |
| CN106356287A (en) * | 2016-09-29 | 2017-01-25 | 昆山国显光电有限公司 | Preparation method for low-temperature polycrystalline silicon thin film and semiconductor structure |
| CN106356287B (en) * | 2016-09-29 | 2019-03-26 | 昆山国显光电有限公司 | The preparation method and semiconductor structure of low-temperature polysilicon film |
| WO2018145515A1 (en) * | 2017-02-09 | 2018-08-16 | 京东方科技集团股份有限公司 | Thin film transistor and fabrication method therefor, display substrate and display device |
| WO2018214119A1 (en) * | 2017-05-25 | 2018-11-29 | 华为技术有限公司 | Graphene field-effect transistor and preparation method therefor |
| CN109817644A (en) * | 2019-01-30 | 2019-05-28 | 武汉华星光电半导体显示技术有限公司 | A kind of tft array substrate and preparation method thereof |
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|---|---|
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