CN104932654A - Clock control method and apparatus - Google Patents
Clock control method and apparatus Download PDFInfo
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- CN104932654A CN104932654A CN201510012682.2A CN201510012682A CN104932654A CN 104932654 A CN104932654 A CN 104932654A CN 201510012682 A CN201510012682 A CN 201510012682A CN 104932654 A CN104932654 A CN 104932654A
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Abstract
The present invention provides a clock control method and apparatus. The apparatus comprises a hibernation mode management module and a hibernation policy execution module. The hibernation policy execution module is such configured that: after a shallow hibernation mode is started and when a service module is running, a clock control device disables a non-working analog IP in the shallow hibernation mode according to a clock control policy acquired from a shallow hibernation register; and upon completion of running of the service module, the clock control device enables the analog IP disabled in the shallow hibernation mode according to the clock control policy acquired from the shallow hibernation register. The hibernation policy execution module is further such configured that: when a deep hibernation mode is started, the clock control device automatically disables a non-working analog I{ in the deep hibernation mode; and after the deep hibernation mode is started and in the advent of an external interruption, the clock control device automatically enables the analog IP disclosed in the deep hibernation mode. According to the present invention, the gate clock is automatically managed by using a hardware system, thereby greatly improving the processing performance.
Description
Technical field
The invention belongs to clock control field, particularly relate to a kind of clock control method and device.
Background technology
Power managed is exactly always the key of chip development design, is the basis of whole chip low consumption work, and a good power consumption management method not only can improve the travelling speed of whole chip but also its low consumption can be made to operate, prolongs standby time.
Traditional power consumption management method, mainly through its composition module is divided into multiple clock area, then with the embedded software of DPM technology manage each clock area clock supply realize, the input of its clock is closed completely for the module not participating in work at present, clock supply is reopened when needs participation work
As shown in Figure 1, software merit rating 1.1 register, then 1.1 registers realize the gated clock of modules with 1.2 latch Latch below, 1.3 jointly with door, and software is according to dispatching needs, the clock of opening/closing corresponding module.
As shown in Figure 2, the gated clock of CPU needs the packaging group of extra wrapper and Java to set up, and software, according to working order, configures 2.1 control registers, then with 2.2AHB (Advanced High Performance Bus below; Advanced High-Performance Bus) bus controller, 2.3 finite state machines, 2.4 latch Latch, 2.5 and door jointly realize to cpu clock control (comprising: close, open).
Said method all needs the very clear operating process of peopleware, adds the complicacy of software, have impact on chip performance.
Summary of the invention
The invention provides a kind of clock control method and device, to solve the problem.
The present invention also provides a kind of clock control method, comprises the following steps:
According to park mode type, perform corresponding dormancy strategy; Wherein, described park mode type comprises: shallow dormancy pattern, deep sleep mode.
The present invention also provides a kind of clock control device,
Comprise park mode administration module, dormancy strategy execution module; Wherein, described park mode administration module is connected with described dormancy strategy execution module;
Described park mode administration module, for managing shallow dormancy pattern and deep sleep mode;
Dormancy strategy execution module, for after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Dormancy strategy execution module, when also starting for deep sleep mode, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Dormancy strategy execution module, after also starting for deep sleep mode, when external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
Compared to prior art, according to a kind of clock control method provided by the invention and device, adopt hardware system automatically to manage gated clock, too much participate in without the need to software, greatly improve handling property, reduce software complexity; In addition, in the process of management gated clock, automatic switch storer and safe IP etc., realize further power managed; In addition, the design, in system level design, independent of CPU, adds the reusability of design.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Figure 1 shows that prior art Clock management figure and clock administration module;
Figure 2 shows that prior art cpu clock control chart and MCU Wrapper;
Figure 3 shows that structure principle chart of the present invention;
Figure 4 shows that clock control method processing flow chart under the shallow dormancy pattern of the embodiment of the present invention 4;
Figure 5 shows that clock control method processing flow chart under the deep sleep mode of the embodiment of the present invention 5;
Figure 6 shows that the clock control method processing flow chart of the embodiment of the present invention 4, example 5;
Figure 7 shows that clock control device structural drawing of the present invention.
Embodiment
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
As shown in Figure 3, comprise: CPU, shallow dormancy register, algorithm computing module, EEPROM/flash write and wipe operational module, DMA (Direct Memory Access, direct memory access (DMA)) operational module, deep sleep mode, the management of Simulation with I P switch, clock control device.
In advance at shallow dormancy register configuration clock control strategy;
When business module runs, clock control device according to the described clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Under closedown shallow dormancy pattern, work simulation IP does not comprise: close cpu clock, and unlatching algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module.
After business module runs, clock control device according to the described clock control strategy from the acquisition of described shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Described business module produces system-level look-at-me after running, shot clock opertaing device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern.
The Simulation with I P closed under opening shallow dormancy pattern comprises: closedown algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module, open cpu clock.
Business module comprises: algorithm computing module, EEPROM/flash write and wipe operational module, DMA (Direct Memory Access, direct memory access (DMA)) operational module.
EEPROM (Electr ical ly Erasable Programmable Read-Only Memory, band EEPROM (Electrically Erasable Programmable Read Only Memo)).
Described clock control strategy comprises business module running status and cpu clock, Simulation with I P control strategy, the business module clock table of comparisons, as shown in table 1:
Business module running status and cpu clock, Simulation with I P control strategy, the business module clock table of comparisons
| Business module running status | Cpu clock | Simulation with I P control strategy | Business module clock |
| Business module runs | Close | Close not work simulation IP | Open |
| Business module runs complete | Open | Open the Simulation with I P of closedown | Close |
Table 1
When deep sleep mode starts, clock control device automatically performs to close under deep sleep mode not work simulation IP;
When external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
Under closedown deep sleep mode, work simulation IP does not comprise: close cpu clock, close not work simulation IP, crystal oscillator OSC in Closure panel;
The Simulation with I P closed under opening deep sleep mode comprises: open crystal oscillator OSC on sheet, opens the not work simulation IP of closedown, opens cpu clock; Wherein, described not work simulation IP comprises safe IP.
When deep sleep mode starts, system clock is reduced to low-limit frequency by system automatically, closes cpu clock, closes all not work simulation IP, comprise safe IP, OSC etc.
External interrupt carrys out interim waken system, and main operation has: the dormant control signal of scavenge system level, opens crystal oscillator OSC on sheet, opens the not work simulation IP (comprising safe IP) of closedown, opens cpu clock.
As shown in Figure 4, downcpu_symmetry_en signal is the enable algorithm dormancy flow process signal of initial configuration; Symmetry_en signal is algorithm enable signal, once enabled systems automatically performs shallow dormancy power managed flow process; Cpu_gate_crypt signal is for controlling close/open cpu clock; Sleep_ctl is the dormant control signal of system-level generation; Counter_vrenb signal opens closedown for control simulation IP's; Symmetry_gate_insys_r signal is for controlling the opening/closing of encryption and decryption clock; Crypt_dstn signal and crypt_current signal are for controlling the automatic lifting of encryption and decryption clock; Crypto_symmetry_int signal is by the dormant control signal sleep_ctl of scavenge system level.
As shown in Figure 5, sleep_deep signal is the indicator signal entering deep dormancy state that CPU informs; Sys_dstn and sys_current is used for the automatic lifting of control system clock; Cpu_gate_sleep is for controlling close/open cpu clock; Sleep_ctl is the dormant control signal of system-level generation; Sleep_ctl2 and sleep_ctl is similar, has only put when deep dormancy, for generation of osc_gate signal, and the close/open of control OSC; Intr will remove sleep_ctl and sleep_ct2 simultaneously.
Figure 6 shows that the clock control method processing flow chart of the embodiment of the present invention 4, example 5, comprise the following steps:
Step 601: in advance at shallow dormancy register configuration clock control strategy;
Step 602: after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Under closedown shallow dormancy pattern, work simulation IP does not comprise: close cpu clock, and unlatching algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module.
Step 603: business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
The Simulation with I P closed under opening shallow dormancy pattern comprises: closedown algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module, open cpu clock.
Step 604: when deep sleep mode starts, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Under closedown deep sleep mode, work simulation IP does not comprise: close cpu clock, close not work simulation IP (comprising safe IP), crystal oscillator OSC in Closure panel.
Step 605: after deep sleep mode starts, when external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode;
The Simulation with I P closed under opening deep sleep mode comprises: open crystal oscillator OSC on sheet, opens the not work simulation IP (comprising safe IP) of closedown, opens cpu clock.
Figure 7 shows that clock control device structural drawing of the present invention, comprise park mode administration module, dormancy strategy execution module; Wherein, described park mode administration module is connected with described dormancy strategy execution module;
Described park mode administration module, for managing shallow dormancy pattern and deep sleep mode;
Dormancy strategy execution module, for after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Dormancy strategy execution module, when also starting for deep sleep mode, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Dormancy strategy execution module, after also starting for deep sleep mode, when system-level interruption arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
Compared to prior art, according to a kind of clock control method provided by the invention and device, adopt hardware system automatically to manage gated clock, too much participate in without the need to software, greatly improve handling property, reduce software complexity; In addition, in the process of management gated clock, automatic switch storer and safe IP etc., realize further power managed; In addition, the design, in system level design, independent of CPU, adds the reusability of design.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a clock control method, is characterized in that, comprises the following steps:
According to park mode type, perform corresponding dormancy strategy; Wherein, described park mode type comprises: shallow dormancy pattern, deep sleep mode.
2. method according to claim 1, is characterized in that, after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Wherein, shallow dormancy pattern also comprises: in advance at shallow dormancy register configuration clock control strategy before starting.
3. method according to claim 2, is characterized in that, described clock control strategy comprises business module running status and cpu clock, Simulation with I P control strategy, the business module clock table of comparisons.
4. method according to claim 2, is characterized in that, described business module comprises: algorithm computing module, EEPROM/flash write and wipe operational module, direct memory access (DMA) operational module.
5. method according to claim 4, is characterized in that, under closedown shallow dormancy pattern, work simulation IP does not comprise: close cpu clock, and unlatching algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module.
6. method according to claim 4, it is characterized in that, described business module produces system-level look-at-me after running, shot clock opertaing device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern.
7. method according to claim 6, is characterized in that, the Simulation with I P closed under opening shallow dormancy pattern comprises: closedown algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module, open cpu clock.
8. method according to claim 1, is characterized in that, when deep sleep mode starts, clock control device automatically performs to close under deep sleep mode not work simulation IP;
When external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
9. method according to claim 8, is characterized in that, under closedown deep sleep mode, work simulation IP does not comprise: close cpu clock, close not work simulation IP, crystal oscillator OSC in Closure panel; The Simulation with I P closed under opening deep sleep mode comprises: open crystal oscillator OSC on sheet, opens the not work simulation IP of closedown, opens cpu clock; Wherein, described not work simulation IP comprises safe IP.
10. a clock control device, is characterized in that, comprises park mode administration module, dormancy strategy execution module; Wherein, described park mode administration module is connected with described dormancy strategy execution module;
Described park mode administration module, for managing shallow dormancy pattern and deep sleep mode;
Dormancy strategy execution module, for after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Dormancy strategy execution module, when also starting for deep sleep mode, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Dormancy strategy execution module, after also starting for deep sleep mode, when external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111339001A (en) * | 2020-03-09 | 2020-06-26 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588274A (en) * | 2004-09-21 | 2005-03-02 | 威盛电子股份有限公司 | Circuit andm ethod for coordinating south-north bridge circuit and CPU at different energy saving state |
| CN1858676A (en) * | 2006-05-31 | 2006-11-08 | 威盛电子股份有限公司 | Method for setting equipment power management state and equipment power consumption saving method |
| CN101105713A (en) * | 2007-08-24 | 2008-01-16 | 威盛电子股份有限公司 | Data transmission rate regulation method and computer system |
| CN102520782A (en) * | 2011-12-15 | 2012-06-27 | 江苏中科梦兰电子科技有限公司 | Power supply management method based on automatic adjustment of processor nuclear number |
| US20140181555A1 (en) * | 2012-12-21 | 2014-06-26 | Devadatta V. Bodas | Managing a power state of a processor |
-
2015
- 2015-01-09 CN CN201510012682.2A patent/CN104932654B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588274A (en) * | 2004-09-21 | 2005-03-02 | 威盛电子股份有限公司 | Circuit andm ethod for coordinating south-north bridge circuit and CPU at different energy saving state |
| CN1858676A (en) * | 2006-05-31 | 2006-11-08 | 威盛电子股份有限公司 | Method for setting equipment power management state and equipment power consumption saving method |
| CN101105713A (en) * | 2007-08-24 | 2008-01-16 | 威盛电子股份有限公司 | Data transmission rate regulation method and computer system |
| CN102520782A (en) * | 2011-12-15 | 2012-06-27 | 江苏中科梦兰电子科技有限公司 | Power supply management method based on automatic adjustment of processor nuclear number |
| US20140181555A1 (en) * | 2012-12-21 | 2014-06-26 | Devadatta V. Bodas | Managing a power state of a processor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111339001A (en) * | 2020-03-09 | 2020-06-26 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
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Effective date of registration: 20200731 Address after: 2505 COFCO Plaza, No.2, nanmenwai street, Nankai District, Tianjin Patentee after: Xin Xin finance leasing (Tianjin) Co.,Ltd. Address before: 100094 No. 6 Yongjia North Road, Beijing, Haidian District Patentee before: DATANG MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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Effective date of registration: 20211025 Address after: 100094 No. 6 Yongjia North Road, Beijing, Haidian District Patentee after: DATANG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 300110 2505 COFCO Plaza, No. 2, nanmenwai street, Nankai District, Tianjin Patentee before: Xin Xin finance leasing (Tianjin) Co.,Ltd. |
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