Summary of the invention
The invention provides a kind of clock control method and device, to solve the problem.
The present invention also provides a kind of clock control method, comprises the following steps:
According to park mode type, perform corresponding dormancy strategy; Wherein, described park mode type comprises: shallow dormancy pattern, deep sleep mode.
The present invention also provides a kind of clock control device,
Comprise park mode administration module, dormancy strategy execution module; Wherein, described park mode administration module is connected with described dormancy strategy execution module;
Described park mode administration module, for managing shallow dormancy pattern and deep sleep mode;
Dormancy strategy execution module, for after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Dormancy strategy execution module, when also starting for deep sleep mode, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Dormancy strategy execution module, after also starting for deep sleep mode, when external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
Compared to prior art, according to a kind of clock control method provided by the invention and device, adopt hardware system automatically to manage gated clock, too much participate in without the need to software, greatly improve handling property, reduce software complexity; In addition, in the process of management gated clock, automatic switch storer and safe IP etc., realize further power managed; In addition, the design, in system level design, independent of CPU, adds the reusability of design.
Embodiment
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
As shown in Figure 3, comprise: CPU, shallow dormancy register, algorithm computing module, EEPROM/flash write and wipe operational module, DMA (Direct Memory Access, direct memory access (DMA)) operational module, deep sleep mode, the management of Simulation with I P switch, clock control device.
In advance at shallow dormancy register configuration clock control strategy;
When business module runs, clock control device according to the described clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Under closedown shallow dormancy pattern, work simulation IP does not comprise: close cpu clock, and unlatching algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module.
After business module runs, clock control device according to the described clock control strategy from the acquisition of described shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Described business module produces system-level look-at-me after running, shot clock opertaing device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern.
The Simulation with I P closed under opening shallow dormancy pattern comprises: closedown algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module, open cpu clock.
Business module comprises: algorithm computing module, EEPROM/flash write and wipe operational module, DMA (Direct Memory Access, direct memory access (DMA)) operational module.
EEPROM (Electr ical ly Erasable Programmable Read-Only Memory, band EEPROM (Electrically Erasable Programmable Read Only Memo)).
Described clock control strategy comprises business module running status and cpu clock, Simulation with I P control strategy, the business module clock table of comparisons, as shown in table 1:
Business module running status and cpu clock, Simulation with I P control strategy, the business module clock table of comparisons
Business module running status |
Cpu clock |
Simulation with I P control strategy |
Business module clock |
Business module runs |
Close |
Close not work simulation IP |
Open |
Business module runs complete |
Open |
Open the Simulation with I P of closedown |
Close |
Table 1
When deep sleep mode starts, clock control device automatically performs to close under deep sleep mode not work simulation IP;
When external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
Under closedown deep sleep mode, work simulation IP does not comprise: close cpu clock, close not work simulation IP, crystal oscillator OSC in Closure panel;
The Simulation with I P closed under opening deep sleep mode comprises: open crystal oscillator OSC on sheet, opens the not work simulation IP of closedown, opens cpu clock; Wherein, described not work simulation IP comprises safe IP.
When deep sleep mode starts, system clock is reduced to low-limit frequency by system automatically, closes cpu clock, closes all not work simulation IP, comprise safe IP, OSC etc.
External interrupt carrys out interim waken system, and main operation has: the dormant control signal of scavenge system level, opens crystal oscillator OSC on sheet, opens the not work simulation IP (comprising safe IP) of closedown, opens cpu clock.
As shown in Figure 4, downcpu_symmetry_en signal is the enable algorithm dormancy flow process signal of initial configuration; Symmetry_en signal is algorithm enable signal, once enabled systems automatically performs shallow dormancy power managed flow process; Cpu_gate_crypt signal is for controlling close/open cpu clock; Sleep_ctl is the dormant control signal of system-level generation; Counter_vrenb signal opens closedown for control simulation IP's; Symmetry_gate_insys_r signal is for controlling the opening/closing of encryption and decryption clock; Crypt_dstn signal and crypt_current signal are for controlling the automatic lifting of encryption and decryption clock; Crypto_symmetry_int signal is by the dormant control signal sleep_ctl of scavenge system level.
As shown in Figure 5, sleep_deep signal is the indicator signal entering deep dormancy state that CPU informs; Sys_dstn and sys_current is used for the automatic lifting of control system clock; Cpu_gate_sleep is for controlling close/open cpu clock; Sleep_ctl is the dormant control signal of system-level generation; Sleep_ctl2 and sleep_ctl is similar, has only put when deep dormancy, for generation of osc_gate signal, and the close/open of control OSC; Intr will remove sleep_ctl and sleep_ct2 simultaneously.
Figure 6 shows that the clock control method processing flow chart of the embodiment of the present invention 4, example 5, comprise the following steps:
Step 601: in advance at shallow dormancy register configuration clock control strategy;
Step 602: after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Under closedown shallow dormancy pattern, work simulation IP does not comprise: close cpu clock, and unlatching algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module.
Step 603: business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
The Simulation with I P closed under opening shallow dormancy pattern comprises: closedown algorithm computing module, EEPROM/flash write the clock wiping operational module, direct memory access (DMA) operational module, open cpu clock.
Step 604: when deep sleep mode starts, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Under closedown deep sleep mode, work simulation IP does not comprise: close cpu clock, close not work simulation IP (comprising safe IP), crystal oscillator OSC in Closure panel.
Step 605: after deep sleep mode starts, when external interrupt arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode;
The Simulation with I P closed under opening deep sleep mode comprises: open crystal oscillator OSC on sheet, opens the not work simulation IP (comprising safe IP) of closedown, opens cpu clock.
Figure 7 shows that clock control device structural drawing of the present invention, comprise park mode administration module, dormancy strategy execution module; Wherein, described park mode administration module is connected with described dormancy strategy execution module;
Described park mode administration module, for managing shallow dormancy pattern and deep sleep mode;
Dormancy strategy execution module, for after shallow dormancy pattern starts, when business module runs, clock control device according to the clock control strategy obtained from shallow dormancy register, not work simulation IP under closedown shallow dormancy pattern;
Business module run after, clock control device according to the clock control strategy obtained from shallow dormancy register, the Simulation with I P closed under opening shallow dormancy pattern;
Dormancy strategy execution module, when also starting for deep sleep mode, clock control device automatically performs to close under deep sleep mode not work simulation IP;
Dormancy strategy execution module, after also starting for deep sleep mode, when system-level interruption arrives, the Simulation with I P that clock control device is closed under automatically performing and opening deep sleep mode.
Compared to prior art, according to a kind of clock control method provided by the invention and device, adopt hardware system automatically to manage gated clock, too much participate in without the need to software, greatly improve handling property, reduce software complexity; In addition, in the process of management gated clock, automatic switch storer and safe IP etc., realize further power managed; In addition, the design, in system level design, independent of CPU, adds the reusability of design.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.