CN104600116A - 场效应半导体构件及其制造方法 - Google Patents
场效应半导体构件及其制造方法 Download PDFInfo
- Publication number
- CN104600116A CN104600116A CN201410592595.4A CN201410592595A CN104600116A CN 104600116 A CN104600116 A CN 104600116A CN 201410592595 A CN201410592595 A CN 201410592595A CN 104600116 A CN104600116 A CN 104600116A
- Authority
- CN
- China
- Prior art keywords
- region
- semiconductor
- semiconductor mesa
- mesa
- top side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 274
- 230000005669 field effect Effects 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 45
- 230000008859 change Effects 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000002019 doping agent Substances 0.000 claims description 20
- 230000011218 segmentation Effects 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 description 27
- 230000015556 catabolic process Effects 0.000 description 18
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 229910002601 GaN Inorganic materials 0.000 description 9
- 230000005684 electric field Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 2
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- -1 InGaP (InGaPa) Chemical compound 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000004378 air conditioning Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000012885 constant function Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/6634—Vertical insulated gate bipolar transistors with a recess formed by etching in the source/emitter contact region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Composite Materials (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明涉及一种场效应构件,包括半导体主体,其在边缘区域从背面延伸至半导体主体的表面,并且半导体主体包括半导体台面,半导体台面以垂直于背面和/或表面的竖直的方向延伸至安置在表面之上的一个高度(hM)处的半导体台面顶侧,其中,半导体主体在竖直的横截面中还包括:漂移区,其至少在边缘区域中延伸至表面并且部分地安置在半导体台面之中;以及至少部分地安置在半导体台面之中的主体区,其与漂移区形成第一pn结,第一pn结在半导体台面的两个侧壁之间延伸,其中,第一pn结在水平方向上离半导体台面顶侧的垂直距离(d)会变化并且在由两个侧壁隔开的中央区域中采用最大的值(d1),并且其中,该最大的值(d1)至少为高度(hM)的70%。
Description
技术领域
本发明的实施形式涉及场效应半导体构件,尤其是涉及垂直的场效应半导体晶体管以及涉及场效应半导体构件的制造方法。
背景技术
半导体晶体管尤其是场效应控制的半导体晶体管诸如n金属氧化物半导体场效应晶体管(MOSFET)和具有绝缘栅极的双极型晶体管(IGBT)将被用于不同的应用之中,其中尤其是用作在电源供应装置及整流器、电动车、空调以及甚至音响设备之中的开关。
迄今为止,功率半导体构件主要根据在尽可能小的面积需求(A)时的小的导通电阻(Ron)、尤其是根据小的乘积Ron*A、根据快速的开关和/或较低的开关损耗来加以优化。电感式负载能够在开关过程中产生较大的电压尖峰,从而附加地保护受控的功率半导体构件。
尤其是对于高功率的电路来说通常使用DMOS-场效应晶体管,例如DMOSFET(双扩散金属氧化物半导体场效应晶体管),通过双注入来形成其通道结构。迄今为止,DMOS晶体管实施为平的DMOS晶体管或者实施为沟道MOS晶体管(沟槽MOS晶体管)。平的DMOS晶体管尤其是在更高的截止电压(>30V)时需要相对大的半导体面积,这将使得该产品变得昂贵。沟槽MOS晶体管需要非常小的半导体面积,但是在其制造时将会带来更高的工艺开销,例如为了提供对于一个电压等级合适的边缘闭合。通常来说,在沟槽MOS晶体管中面积获利会超过额外的工艺开销,由此总体上达到了成本节约。在功率受限的和/或所谓的多芯片产品(在此附加于DMOS-晶体管需要另外的信号路径和导线)之中并不能充分地利用该面积获利,因为对于待整流的能量和/或导线和焊盘来说需要某个最小半导体面积。然而,这样的面积在复杂的DMOS技术中是昂贵的。
因此,存在对于经改善的场效应半导体构件的以及场效应半导体构件的经改善的制造方法的需求。
发明内容
依据一种实施形式,场效应构件包括半导体主体,所述半导体主体在边缘区域从背面延伸至所述半导体主体的表面,并且所述半导体主体包括半导体台面,所述半导体台面以垂直于所述背面和/或所述表面的竖直的方向延伸至安置在所述表面之上的一个高度处的半导体台面顶侧,其中,所述半导体主体在竖直的横截面中还包括:漂移区,其至少在所述边缘区域中延伸至所述表面并且部分地安置在所述半导体台面之中;以及至少部分地安置在所述半导体台面之中的主体区,其与所述漂移区形成第一pn结,所述第一pn结在所述半导体台面的两个侧壁之间延伸,其中,所述第一pn结在水平方向上离所述半导体台面顶侧的垂直距离会变化并且在由两个侧壁隔开的中央区域中采用最大的值,并且其中,所述最大的值至少为所述高度的70%。
依据一种实施形式,场效应构件包括半导体主体,其在边缘区域从背面延伸至表面,并且所述半导体主体包括半导体台面,所述半导体台面以平行于所述背面的法向量和/或所述表面的法向量的竖直的方向延伸至安置在所述表面之上的半导体台面顶侧,其中,所述半导体主体在竖直的横截面中还包括:漂移区,其至少在所述边缘区域中延伸至所述表面并且部分地安置在所述半导体台面之中;以及至少部分地安置在所述半导体台面之中的主体区,其包括两个分别与所述半导体台面的两个侧壁中的一个相邻的第一部分区域和在两个第一部分区域之间安置的第二部分区域,其中,所述两个第一部分区域和所述第二部分区域与所述漂移区形成第一pn结,所述第一pn结在所述半导体台面的两个侧壁之间延伸,其中,所述第二部分区域在所述漂移区竖直地比所述两个第一部分区域更深地加以延伸,并且其中,所述第二部分区域比所述两个第一部分区域具有更大的最大掺杂浓度。
依据一种实施形式,用于制造场效应构件的方法包括以下步骤:提供晶圆,所述晶圆包括第一功率类型的第一半导体层、安置在所述第一半导体层之上的第二功率类型的第二半导体层和安置在所述第二半导体层之上的第三半导体层,所述第二半导体层与所述第一半导体层形成第一pn结,所述第三半导体层与所述第二半导体层形成第二pn结并且延伸至所述晶圆的顶侧;在所述晶圆的所述顶侧之上形成具有多个开口的台面掩膜;通过所述台面掩膜来蚀刻所述晶圆,使得产生多个深的沟道和安置在所述多个深的沟道之间的多个半导体台面,其中,所述多个深的沟道延伸入所述第一半导体层;以及将所述第一功率类型的掺杂物注入至少一个与所述第一pn结相邻的半导体区域。
对于专业人员来说,在阅读以下详细的说明书和查看附图时能够得出另外的特征和优点。
附图说明
在附图中的部件并非必须一定按比例绘制,其中,重点其实是在于阐述本发明的基本构思。此外,在附图中相同的附图标记描述相对应的部分。附图中:
图1A和图1B示出了穿过依据一个实施形式的场效应半导体构件的竖直的截面图;
图2示出了穿过依据一个实施形式的场效应半导体构件的竖直的截面图;以及
图3至图9示出了在依据本发明的方法的多个步骤期间或者之后的穿过半导体晶圆的竖直的截面图。
具体实施方式
在接下来的详细的说明书中参阅作为本文档的组成部分的并且在其中示意性地示出了本发明所实际实现的特定的实施形式的附图。方向指示如“上”、“下”、“前”、“后”、“前面的”、“后面的”等将参照附图上所描述的方向地采用。因为一些实施形式的构件能够定位在一系列不同的方向上,所以方向指示用于示意而不用于限制。指出了能够使用另外的实施形式并且采取结构性的或者逻辑的改变,而不超出本发明的范围。因此从接下来详细的说明并不会读出受限制的含义并且本发明的范围将通过权利要求加以确定。此外,在这种关联上还表示:特征或者特征组合(例如材料或者其组合)和/或多个领域的装置,这些装置在说明书中、在附图中和/或在多个权利要求中仅仅明确地参照一种装置来加一个公开,对于本领域的专业人员来说只要未给出其他的则也同样公开了所属的制造方法的相应的特征或者特征组合。与对于专业人员所公开的特征或者特征组合相类似地,在说明书、附图和/或权利要求中仅明确地参照制造方法加以公开的特征或者特征组合也相应地给出了所制造的装置的相应的特征或者特征组合。
从现在开始将详细地阐述不同的实施形式,其中的一个或者多个示例将在附图中示出。每个示例均是为了阐述目的而给出的并且并不被理解为对于本发明的限制。示例性地,能够作为某个实施形式的一部分加以示出或者描述的特征能够在其他实施形式之中或者与其他实施形式相关联地加以应用,从而得出另外的实施形式。本发明应该包含这样的改变或者变型。这些示例将使用特定的语言加以描述,这些语言不旨在限制所附的权利要求的范围。附图并不是按照比例绘制的并且仅用于示意之目的。出于清楚之缘由,只要是为了示出区别,在不同的附图之中的相同的元件或者制造步骤将以相同的附图标记加以描述。
表述“水平”在本说明书的范围之中应当描述这样的方向,该方向基本上平行于半导体基体或者半导体主体的第一或者水平表面地加以延伸。其能够例如为晶圆或者芯片的表面。
在本说明书之中能够得出:半导体基体或者半导体主体的第二表面由下面的或者背面的表面(背面)来形成,其典型地是平的并且平行于第一表面。
表述“竖直”在本说明书的范围之中描述这样的方向,该方向基本上垂直于第一表面和/或第二表面,也就是说基本上与半导体基体或者半导体主体的第一表面的法线方向和/或第二表面的法线方向平行。概念“上面”和“下面”描述了参照与竖直的方向相关的另外的结构特征的结构特征的相对的布置。
本专利申请的上下文中,同义地使用的概念“台面(Mesa)”和“半导体台面”描述了在两个相邻的沟道之间的半导体区域,这两个相邻的沟道延伸入半导体基体或者半导体主体的竖直横截面之中。典型地,在该半导体台面之中设置形成pn结的至少两个半导体区。
典型地,在激活的区域中,多个半导体台面在竖直的方向上从第一表面延伸至半导体基体或者半导体主体的设置在第一表面之上的顶侧或者限定该顶侧。该半导体基体或者半导体主体的顶侧接下来将被描述为半导体台面顶侧。典型地,该半导体台面顶侧基本上与第一表面和/或第二表面平行。
在本专利申请中,n掺杂的半导体区域被描述为第一功率类型的半导体区域,而p掺杂的半导体区域被描述为第二功率类型的半导体区域。替代地,能够构造具有与之相反的掺杂关系的半导体构件,使得第一功率类型相应于p掺杂并且第二功率类型能够相应于n掺杂。此外,在一些附图中通过为掺杂类型提供“-”或者“+”来给出相对的掺杂浓度。例如,“n-”表示小于“n”掺杂区域的掺杂浓度的掺杂浓度,而“n+”掺杂区域具有大于“n”掺杂区域的掺杂浓度的掺杂浓度。当给出了相对的掺杂浓度时,只要未明确提出,则并不意味着具有相同的相对掺杂浓度的掺杂区域必须拥有相同的绝对掺杂浓度。例如,两个不同的n+掺杂区域具有不同的绝对掺杂浓度。同样对于n+掺杂区域和p+掺杂区域的示例也适用。
在本专利申请中所描述的特定的实施形式尤其是但是并不仅仅是指场效应半导体构件,尤其是涉及诸如竖直的MOSFET的场效应半导体晶体管及其制造方法。
典型地涉及具有设置在顶侧的源金属层和在顶侧的附近的典型地设置在半导体台面之间的沟道之中的绝缘的栅极和设置在相反的背面之上的漏金属层的竖直的功率MOSFET。这些金属层典型地也提供相应的连接端,例如在接触面区域之中。该竖直的半导体功率晶体管典型地在激活的区域之中包含多个单元,例如MOSFET单元,用于传输和/或控制负载电流。此外,由上面来看,该激活的面能够至少部分地由至少一个边缘闭合结构来包围。
在本说明书的上下文中,表述“金属层”应当描述具有金属的或者近乎金属的关于导电性的特性的区域或者层。一个金属层能够与半导体区域接触并且构造电极、接触面(焊盘)和/或半导体构件的连接端。该金属层能够由诸如Al、Ti、W、Cu和Co的金属组成或者包括这样的金属,但是也能够由关于导电性的金属的或者近乎金属的特性的材料来制造,诸如强n或者p掺杂的Si聚合物、TiN或者导电的硅化物诸如TaSi2、TiSi2、PtSi、CoSi2、WSi2或者诸如此类的。该金属层也能够包含不同的导电材料,例如多种材料的叠加(Stapel)。
表述“边缘闭合结构”诸如其在本专利申请之中所使用的那样应该描述这样的结构,其提供过渡区域,在该过渡区域之中围绕半导体构件的激活的区域的高的电场逐渐地变化为在该构件的边缘的电势和/或变化为诸如地的参考电势。该边缘闭合结构能够通过将电场线分布在连接区域来例如避免在该pn结的附近的场强。
表述“功率半导体构件”应当在本专利申请的范围内描述在具有高电压和/或高电流控制或者开关容量()的单个的芯片之上的半导体构件。换句话说,该功率半导体构件对于高的电流典型地覆盖在安培级的范围内和/或高的电压例如在约10V之上或者在约500V之上。在本专利申请的范围内,术语“功率半导体构件”和“功率半导体元件”是同义词。
表述“场效应”在本专利申请的范围内描述第一功率类型的有导通能力的“通道”的通过电场获取的构造和/或导通能力的控制和/或在第二功率类型的半导体区域中的通道的形式,典型地是第二功率类型的主体区。由于场效应的缘故,通过该通道区域来构造和/或控制在与主体区相邻的第一功率类型的源区和与该主体区相邻的该第一功率类型的漂移区之间的单极的电流路径。该漂移区能够与第一功率类型的更高掺杂的漏极区接触。
该漏极区与漏金属层欧姆式接触。该源区和该主体区与源金属层欧姆式接触。在本申请的上下文中,当在该半导体构件处和/或之上未施加任何电压或者仅施加较小的检验电压时,表述“欧姆式接触”描述了在相应的元件或者半导体构件的一部分之间存在欧姆式的电流路径。在本专利申请的范围之中,表述“电接触”、“电连接”和“欧姆式接触”作为同义词来使用。
在本专利申请的上下文中,概念“MOS”(金属氧化物半导体)应当理解为包括通常的概念“MIS”(金属隔离器半导体)。例如,概念MOSFET(金属氧化物半导体场效应晶体管)应当理解为包含具有栅极隔离器的场效应晶体管(FET),其不是氧化物或者换句话说MOSFET在通常的意义上被用于IGFET(具有隔离的栅极的半导体场效应晶体管)或者MISFET(金属隔离器半导体场效应晶体管)。
在本专利申请的上下文中,表述“开关”描述了这样的半导体结构,其典型地描述功率MOSFET或者功率IGBT,如此地加以配置,以便其能够传输通常在安培级的负载电流并且能够中断该负载电流。
在本专利申请的上下文中,表述“栅极”描述了这样的电极,其与主体区相邻并且绝缘并且如此地加以配置,使得通过对栅极的合适的控制能够通过主体区来构造和/或控制在源区和漂移区之间的通道区域。
接下来主要参照硅半导体构件来阐述以下实施形式,其涉及半导体构件和用于构造半导体构件的方法。相应地,单晶半导体区域或者单晶半导体层典型地为单晶区域或者硅层。然而,该半导体主体也能够由分别对于半导体构件的制造合适的半导体材料来加以制造。例如,这样的材料尤其是诸如硅(Si)或者锗(Ge)、诸如碳化硅(SiC)或者锗化硅(SiGe)的IV族化合物半导体材料、两种、三种或者四种III-V族半导体材料诸如氮化镓(GaN)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、磷化铟镓(InGaPa)、氮化铝镓(AlGaN)、氮化铝铟(AlInN)、氮铟化镓(InGaN)、氮化铝镓铟(AlGaInN)或砷磷化铟镓(InGaAsP)以及两种或者三种II-VI族半导体材料,诸如碲化镉(CdTe)和碲化汞镉(HgCdTe),以仅仅列举一些材料。以上所提及的半导体材料也能够描述为具有同质结(Homoübergang)的半导体材料。当两种不同的半导体材料相互组合时,以同质结来构造一种半导体材料。例如对于具有同质结的半导体材料来说尤其是在没有限制的情况下为具有同质结的氮化铝镓(AlGaN)-氮化铝镓铟(AlGaInN)、铟镓氮(InGaN)-氮化铝镓铟(AlGaInN)、铟镓氮(InGaN)-氮化镓(GaN)、氮化铝镓(AlGaN)-氮化镓(GaN)、氮化铟镓(InGaN)-氮化铝镓(AlGaN)、硅、碳化硅(SixC1-x)和硅-锗半导体材料。对于功率半导体应用来说,目前主要的硅、碳化硅、砷化镓和氮化镓材料能够得以应用。当半导体主体包括诸如碳化硅或者氮化镓的具有较高的带隙(>2eV)的材料时,其具有高的击穿场强或者高的关键的雪崩击穿场强(雪崩击穿场强),所以相应的半导体区域的掺杂能够选为更高,这将降低开启状态电阻RON,其接下来也被描述为接通电阻RON。
图1A示出了穿过竖直的场效应半导体构件100a的竖直截面。该场效应半导体构件100a包括半导体主体40,其处于边缘区域120之中,该边缘区域延伸直至基本上竖直地定向的侧面或者边41,例如从半导体主体40的背面102延伸至第一表面101的锯缘。在接下来,第一表面101也描述为表面101。背面102由半导体主体40的第二表面来形成,其典型地基本上平行于第一表面101,如在两个引入的法向向量en所标识的那样。此外,该半导体主体40具有带有两个基本上竖直地定向的侧壁21的半导体台面20,然而这两个之中在图1A中出于清楚的缘由仅仅以附图标记21示出了左边的侧壁。该半导体台面20具有竖直的高度或者最大竖直维度hM。根据电压等级的不同,该高度hM位于约500nm至约5μm的范围之中,典型地在约500nm至约2μm的范围之中。
在示例的实施例中,该半导体台面20和该侧壁21以竖直的方向en延伸直至在设置在第一表面101之上的半导体主体40的第三表面103之上的高度hM,该第三表面基本上平行于第一和第二表面101、102并且形成该半导体主体40的顶侧103。
在另外的实施例中,侧壁21相对于第一和/或第二表面101、102倾斜。
此外,半导体台面20的表面103在竖直横截面示图中也分为多个部分和/或至少部分地是弯曲的。在该实施例中,半导体台面20同样限定了一个基本上与第一和第二表面101、102平行的半导体主体40的顶侧103,其位于与第一表面101相距hM处。
因为该台面20或者多个半导体台面20形成或者至少部分地限定该顶侧103,所以该顶侧103接下来也描述为台面顶侧103。
典型地,该半导体主体40在激活的区域110之中具有多个半导体台面20,它们从第一表面101延伸至顶侧103,其中,在竖直的横截面示图中相邻的半导体台面分别通过深度为hM的深的(竖直的)沟道50相互隔开。然后,图1A相应于相应的横截面的左边的边缘断面,其右边的边缘断面典型地实施为与图1A呈镜相对称。典型地,激活的区域110在顶视图中由边缘区域120所包围。
依据一个实施形式,半导体主体40在竖直的横截面上另外具有第一功率类型的漂移区1(接下来也描述为漂移区域)、第二功率类型的主体区2(接下来也描述为主体区域)和第一功率类型的源区3(接下来也描述为源区域)。其中,漂移区1在边沿区域120以及在深的沟道50中延伸至第一表面101并且部分地延伸至该激活的区域110的半导体台面20之中。与之相反地,源区3完全地或者该主体区2至少大部分地设置在半导体台面20之中。主体区2与漂移区1共同形成第一pn结14并且与源区3共同形成第二pn结15,该第二pn结15设置在第一pn结14之上并且延伸至侧壁21。
典型地,在激活的区域之中设置有多个台面20,它们通过相应的深的沟道50相互隔开。如以下将参照图3至图9所详细地阐述的那样,能够尤其有效地并且高性价比地制造包括可选的边缘结构的此类的半导体结构。其中,在晶圆上生成任一种拓扑图案之前将实施用于生成双扩散MOS基本结构(注入、扩散以生成主体区和源区2、3)的工艺技术较敏感的工艺步骤。由此能够在相同的有效的面积利用时、例如在传统的生成沟道MOSFET时,附加地至少进一步避免由于在多个台面20处的级别和边效应带来的控制,并且因此显著地降低工艺控制。因为在台面蚀刻时同样在边缘区域120中分隔源区和主体区2、3,所以此外能够明显地降低甚至完全省掉用于边缘结构的附加的工艺花费。
依据一种实施形式,第一pn结14在该半导体台面20的两个侧壁21之间延伸,其中,该pn结14与半导体台面顶侧103的竖直的距离在水平的方向上变化,也就是说是该侧壁21的水平的距离的非恒定的函数,并且假设其最大值d1在半导体台面20的由两个侧壁21所隔开的中央区域2c之中,即在该半导体台面20的参照水平的方向的中间的或者中央的区域2c之中。其中,该最大值d1为该高度hM的至少70%,更为典型地为该高度hM的至少80%并且甚至更为典型地为该高度hM的至少90%。典型地,该最大值d1小于该高度hM的200%例如小于该高度hM的150%,更为典型地小于该高度hM的120%并且甚至更为典型地小于该高度hM的110%。最大值d1的选择能够取决于半导体构件100a的电压等级和绝对高度(沟道深度)hM。所以,在非常平的半导体台面20处具有500nm或者至少该最大值d1也能够大于该高度hM的200%例如该高度hM的约300%。在图1A中所示出的示例性实施例中,作为侧壁21的水平的距离的函数的pn结14离半导体台面顶侧103的竖直的距离d是分段恒定的并且在侧壁21处及其周围采用其最小值d2,该最小值小于该高度hM并且例如能够处于该高度hM的50%至90%的范围之中。
由此该主体区2在该台面20的中央区域竖直地更深地延伸入该漂移区1,这将引起,在那在截断情况下也就是在第一pn结14在截断方向上运行时该电场线会变密,从而使得在相应的高的截断电压时在漂移区1之中的雪崩击穿会置于中央区域2c之下。以这样的方式能够到达该构件的高的稳定性,尤其是相对于重复的雪崩击穿来说。
为此,该第一pn结14和主体区2在竖直的横截面上关于通过该台面20的中央的竖直轴镜相对称,以便将水平方向上的雪崩击穿点置于该台面20的基本上的中间并且从而使得雪崩电流远离台面20的两个侧壁21和在那典型地施加的介电质,因此能够得以保护使其免于能源载体(“热充电载体”)的侵入。但是,该pn结14也能够非对称地加以实施,以便在雪崩击穿的情况下适当地引导出电流。
此外能够将该主体区2在该pn结的附近和在中央区域2c之中设置具有比在主体区2的离侧壁21更近的区域之中的更高的最大掺杂材料浓度。由此,在截断的情况下电场线的对焦以及由此在雪崩击穿情况下的电流线的对焦进一步地得以改善。换句话说,在第一pn结处掺杂材料浓度的梯度能够在水平方向上变化并且在由两个侧壁21隔开的中央区域2c之中采取最大值。尤其地,在中央区域2c之中的主体区2能够具有带有升高的掺杂材料浓度的部分区域,如接下来参照图1B详细地加以阐述的那样。
在图1B中作为竖直的横截面所示出的场效应构件100b的示例性实施例中,半导体主体40包括漂移区1和至少部分地设置在半导体台面20之中的主体区2,漂移区1在边缘区域120中延伸至第一表面101并且部分地设置在半导体台面20之中,主体区2具有两个与由半导体台面20的两个侧壁21相邻的第一部分区域2a和一个在两个第一部分区域2a之间设置的第二部分区域2b,其中,该两个第一部分区域2a和该第二部分区域2b与漂移区1形成第一pn结14,其在半导体台面20的两个侧壁21之间延伸,其中,第二部分区域2b竖直地比两个第一部分区域2a更深地延伸入漂移区1之中并且第二部分区域2b比两个第一部分区域2a具有更大的最大掺杂材料浓度。
因为台面20的在中央区域2c之中设置的第二部分区域2b竖直地更深地延伸入漂移区1之中并且比相邻的第一部分区域2a具有更高的掺杂材料浓度,所以在那里在截断情况下如此地集中电场线,使得在相应高的截断电压的情况下在漂移区1之中的雪崩击穿置于中央区域2c之下。以这样的方式达到了尤其是针对重复的雪崩击穿的该构件的更高的稳定性。
典型地,第二部分区域2b的最大的掺杂材料浓度被提高了相对于第一部分区域2a的最大的掺杂材料浓度的至少五倍,更为典型地至少十倍。
典型地,在顶侧103与分别在两个第一部分区域2a中的一个和漂移区1之间所形成的第一pn结14的第一分段之间的最大竖直的第一距离(由于清晰的缘故在图1B中未示出,在图1A中相应于d2)小于在顶侧103和第一表面101之间的竖直的距离hM,并且在顶侧103和在第二部分区域2b和漂移区1之间所形成的第一pn结14的第二分段之间的最大竖直的第二距离(由于清晰的缘故在图1B中同样未示出,在图1A中相应于d1)大于最大竖直的第一距离。但是,与之上参照图1A的阐述相类似地,最大竖直的第二距离也能够大于该高度hM的200%。
典型地,在台面20的侧壁中的至少一个之上设置有栅极介电区域30(例如热氧化物)和与该栅极介电区域30相邻的栅极12以及在半导体台面20之上所设置的源金属层10与主体区2和源区2欧姆式接触,其中,位于沟道之中的栅极12与源金属层绝缘。此外,在背面102之上典型的在图1B中未示出的漏金属层与漂移区1欧姆式接触地设置,使得场效应构件100b能够作为竖直的MOSFET来运行。
源金属层10典型地仅仅设置在第一pn结14之上,而栅极12典型地部分地设置在该第一pn结14之上并且部分地在其之下,然而典型地仅仅设置于该第一表面101之上。
在示例性的实施例中,源区2和第二部分区域2b通过位于平的沟道51之中的沟道接触与源金属层10欧姆式连接,其中,第二部分区域2b同时能够承担包括相应的通道区的第一部分区域2a的主体接触区的功能,以便实现好的闭锁稳定性。在另一种实施形式之中,第二部分区域2b延伸直至顶侧103或者至少几乎延伸至该顶侧103。在又一个实施形式之中,第二部分区域2b通过相应高掺杂的并且在第二部分区域2b之上设置的、也能够起到主体接触区的作用的半区或者硅化物而与设置在顶侧103之上的源金属层10欧姆式连接。
图2示出了穿过场效应构件100的竖直的横截面的左边的断面图示。该场效应构件100与上面参照图1A和图1B所阐述的场效应构件100a、100b相类似并且能够同样作为MOSFET来运行。在激活的区域110之中,然而设置有多个台面20。此外,在背面102之上设置有漏金属层11,其通过高掺杂的漏区4而与漂移区1欧姆式接触。此外,第一pn结14在主体区2和漂移区1之间在所示出的示例性横截面图示之中分别不是分段线性而是如此地弯曲,使得相应的第一pn结14离顶侧103的竖直的距离作为水平的距离的函数首先从相应的台面20的一个侧壁起增长,然后采用最大值并且然后在接近第二相应的侧壁的过程中重新回落。
这将引起在截断情况下的电场线的对焦并且由此在雪崩击穿时的电流线的对焦。这将在图2中附加地标注的在雪崩击穿时的等位线19加以明晰地表述,在其上电场线或者电流线垂直。此外,在图2中通过点状的小圆示出了最高的碰撞电离的区域。从中可以看出,能够实现将雪崩击穿置于第一pn结之下并且在水平方向上关于相应的台面20分别定为在中间。如本发明所基于的数字模拟的精确的分析那样,由此能够一方面使得雪崩击穿电流均匀地分布在台面20之上并且另一方面远离台面20的侧壁并且由此远离设置在栅极12、12a和台面20之间的栅极介电质30。这将显著地提高示例的n通道MOSFET 100相对于重复的雪崩击穿的鲁棒性,从而使得MOSFET100对于相应的应用、尤其是功率应用诸如电机控制良好地合适。电感式负载能够在开关过程中产生大的电压尖峰,半导体开关100能够通过限定地流过的雪崩击穿效应(雪崩击穿倍增效应)在击穿时较好地保护其免于电压尖峰的伤害。因此,能够省掉相应外部的保护器接线。
由至侧面41的等位线19的曲线此外清楚,即电等位线19由于处于更深处的边缘区域120而非常平坦地设置在整个结构性的面之下,该边缘区域在竖直的方向上仅仅延伸直至第一表面101。这对于未示出的辅助结构诸如电流或者温度传感器以及在激活的区域(单元场区域)110之中的栅极指(Gatefingern)的附加的注入来说尤其是非常有利的。尤其地,在半导体主体40中提高了的电场能够在深的沟道50、50a的角处避免边缘单元(至边缘41以及或者至辅助结构)并且由此改善晶体管的可靠性。典型地,该深的沟道50、50a延伸直至进入半导体主体的相同的深度hM。也能够设置深的沟道50在激活的区域120之中相较于在边缘区域120之中的深的沟道50a稍微更深地延伸进入半导体主体和/或漂移区1或者在侧面41的附近的在边缘区域120之中的半导体主体也比在激活的区域120达到稍微更高处,但是并未延伸至顶侧103。
此外能够设置基本上仅通过台面20中的一些台面来引导出雪崩击穿电流,例如通过每个第二或者第三半导体台面20来实现,由此使得其他的台面的主体区至少在中央区域之中未如此深地延伸入漂移区1之中。
依据一个实施例,在构件100的边缘区域120之中设置至少一个边缘闭合结构12b,其在顶视图中在半导体台面20和侧面41之间设置。由此能够改善半导体构件100的截断能力。典型地,在所示出的横截面之中该边缘区域在约30μm至约50μm或者至约100μm或者甚至至200μm之间的范围之中。
在图2中所示出的示例性实施例之中,该边缘闭合结构被实施为设置在第一表面101之上的场板12a、12b,其在与接近边缘的台面20相邻的分段12a也起到栅极的作用。然而,这仅仅是一个示例。该边缘闭合结构也能够具有与源金属层10相连接的场板、浮动场板、一个或者多个在漂移区1中在第一表面101附近注入的浮动的(浮荡的)p掺杂的半导体区(“浮置保护环”)、所谓的VLD-结构(“横向掺杂的变化”)和/或至少一个在第一表面101和侧面41附近设置的并且高n掺杂的通道停止区。
接下来将描述用于制造参照图1A至图2来阐述的场效应半导体构件的方法。其中,在图3至图9中分别示出了穿过该半导体构件结构的竖直的横截面图示。
首先,提供半导体晶圆40例如硅晶圆,其在接下来也被描述为晶圆40。该半导体晶圆40包括n掺杂的单晶的第一半导体层1、设置在第一半导体层1之上的p掺杂的单晶的第二半导体层2和设置在第二半导体层2之上的n掺杂的单晶的第三半导体层3,第二半导体层2与第一半导体层1形成第一pn结14而第三半导体层3比第一半导体层1更高地掺杂并且与第二半导体层2形成第二pn结15并且延伸直至晶圆40的顶侧103。在制造好的场效应半导体构件100之中,第一半导体层1、第二半导体层2以及第三半导体层3的其余的部分形成漂移区1、主体区2和源区3。
依据一个实施例,在顶侧103上在整个区域产生介电层31,例如通过分离或者热氧化。
在此之后,在晶圆40的顶侧103之上产生具有多个开口的光结构化的掩膜7,这些开口接下来用于产生半导体台面并且因此也被描述为台面掩膜7。由此得出的结构100在图3中加以示出。图3典型地仅仅是出了整个晶圆40的一小部分并且然后示出了来自多个平行地制造的半导体构件100中的基本上的一个半导体构件,其在之后的分割工艺中得出的侧面(侧边)41在图3中通过虚的竖直线加以示出。典型地,掩膜7中的多个第一开口在所示出的竖直横截面之中在之后的分离区域之中比在多个第一开口之间的掩膜7之中的第二开口具有更大的水平间隙(或者在顶视图中具有更大的开口面积)。
如在图3中所示出的那样,晶圆40包括典型地附加的n掺杂的单晶的第四半导体层4,其比第一半导体层1更高地掺杂,其延伸直至该晶圆的背面102并且在制造好的构件100中典型地形成漏区4。该第四半导体层4能够直接地与第一半导体层1相邻。在另外的实施形式之中,在第四半导体层4和第一半导体层1之间设置另一个n掺杂的半导体层,其最大掺杂材料浓度典型地在该区域之中处于第一半导体层1的最大掺杂材料浓度和第四半导体层4的最大掺杂材料浓度之间并且在制造好的半导体构件之中能够形成场停止层。
第一、第二和第三半导体层1、2、3能够通过外延和相应的注入以及热退火(“热处理”)来产生。这典型地如此加以实现,使得第一pn结14和第二pn结15相互之间并且与顶侧103和背面102基本上平行。
现在,晶圆40在使用台面掩膜7的情况下加以蚀刻,其中,也蚀刻介电层31。这将如此地加以实现,即深的沟道50、50a和在深的沟道50、50a之间设置的半导体台面20形成高度hM,其中,深的沟道50、50a延伸直至在第一半导体层1之中的基本上与背面102平行的第一表面101。由此得出的结构100在图4中加以示出。
典型地,深的沟道50、50a以约500nm至约2μm或者甚至约5μm的范围延伸直至进入第一半导体层1。
典型地,位于边缘区域120的深的沟道50a在所示出的竖直的横截面中具有比位于激活的区域110之中的深的沟道50更大的水平间隙。这将简化在该边缘区域之中的边缘闭合结构的之后的产生。
现在,在深的沟道50、50a之中绝缘的栅极12、12a能够得以形成。其中,在深的沟道50、50a的底部并且在台面20的侧壁21以及深的沟道50、50a处例如通过热氧化物或者借助于分离工艺典型地形成另外的介电区域33。在此之后,深的沟道50、50a能够部分地通过导通材料例如高掺杂的聚硅来填充,以便形成栅极12、12a。这能够通过分离以及接下来部分地回蚀所分离的材料来实现。其中,另外的介电质区33如此地实现,即另外的介电质区33在深的沟道50a之中的厚度与在深的沟道50之中是不同的和/或另外的介电质区33在侧壁21的厚度与在相应的深的沟道50、50a或者相应的台面20处的厚度是不一样的。此外能够设置,在栅极12(12a)之上分别形成另一个介电质区34,例如通过所分离的聚硅的热氧化。
依据另一个实施例,在深的沟道50a之中的绝缘的栅极12a如此地加以构造,从而同时形成为与半导体绝缘的场板,其在第一表面101之上并且以相应的相邻的侧面41为方向加以延伸并且具有一个或者多个级别。在该实施例中另一个介电质区33能够在深的沟道50a中如此地加以形成,使得其厚度即竖直的间隙在一个或者多个级别中提高至接下来的侧面41。
在此之后,诸如TEOS(正硅酸乙酯)的氧化物的中间介电质9从顶侧103分离,以便覆盖栅极12、12a。在接下来的平整化工艺之中例如CMP-工艺(化学机械打磨)中能够在顶侧103形成一个层用于接触印刷。图5示出了结构100,在其之后在顶侧103之上形成相应的光掩膜62。
接下来将借助于光掩膜62通过中间介电质9和在台面蚀刻之后在台面20之上的介电的层31的保留的部分蚀刻平的沟道51,以便在中央区域部分地暴露台面20的源区3。图6示出了在光掩膜62再次去除之后的结构100。在其他的实施形式之中,在形成栅极12、12a之前典型地甚至在深的沟道50、50a之中形成介电质区33之前再次去除在台面20之上的介电质的层31。
现在,平的沟道51能够通过另外的蚀刻步骤而变得更深,从而使得平的沟道51能够通过源区3延伸直至主体区2甚至部分地延伸入主体区2,但是典型地并未延伸至漂移区1之中。
取而代之,平的沟道51也能够在蚀刻步骤之中通过中间介电质9、介电层31和源区3来蚀刻。
如通过虚线的箭头在图7中所示出的那样,如今p型(例如硼)掺杂材料从顶侧103通过平的沟道51注入主体区2和/或漂移区1。当代替n通道场效应半导体构件而制造p通道场效应半导体构件时,所示出的n和p型掺杂区域的掺杂能够相互更换并且在该步骤中该n型(例如磷)掺杂材料能够从顶侧103起加以注入。
其中,也能够在不同的深度实现多种注入,其中,多种注入之中的至少一种能够实现在第一pn结14的稍上面或者在其下面,也就是说在竖直的范围内围绕该第一pn结14,例如相应于该高度hM的10%。
根据平的沟道51的竖直的深度的不同典型地能够执行一至三次注入。所以,在相对深的沟道51之中p注入是足够的,此外典型地实现如此高的掺杂,使得邻近相应的平的沟道51的区域(在升温之后)也能够实现为主体接触区(同样参见图1B)。此外,取而代之在半导体主体40之中延伸的平的沟道51也能够进行多次p注入。
接下来的升温步骤将会引起所注入的掺杂材料的激活,从而使得第一pn结14在深的沟道50、50a之间的中央的区域2c之中竖直更深地延伸入第一半导体层1之中,相较于如图8所示在半导体台面20的侧壁21处或者其附近而言。在升温步骤期间该掺杂材料能够根据温度、半导体材料和掺杂材料的不同至少部分地更深地扩散至第一半导体层1之中。该升温步骤能够例如实施为所谓的“快速热退火”过程。
因为在台面20处的控制在第二部分区域2b的实现之中在任何情况下仅仅对于掺杂材料分布作出较小的贡献,所以将会以非常小的工艺变化来实施该方法。
该方法典型地如此加以实施,使得在由相应的半导体台面20的侧壁21所隔开的中央的区域2c之中的掺杂浓度在相应的第一pn结14之上或者附近上升。
典型地,如此地实施该方法,使得在顶侧103和该第一pn结14的与相应的侧壁21相邻的第一分段之间的最大竖直的第一距离小于在该顶侧103和该第一pn结14的相应的第二分段之间的最大竖直的第二距离,该相应的第二分段分别设置在该第一pn结14的多个第一分段中的两个之间。典型地,该最大竖直的第二距离处于竖直的距离(hM)的约80%至约150%之间,但是根据构件等级的不同甚至能够大于或者小于所选择的。此外,该方法能够如此地加以实施,使得在相应的半导体台面20的中央的区域2c之中的第一pn结14和第一表面101之间的最大竖直的距离(|d1-hM|)小于该半导体台面20的高度hM的30%,更为典型地小于20%或者甚至小于10%。如上参照图1A至图2所阐述的那样,第一pn结14能够延伸入相应的中央的区域2c之中并且也能够更深地延伸入该漂移区1之中。
现在,例如能够通过分离导通材料(例如金属或者导通的聚硅)以及另一种可选的平整化工艺在平的沟道51中产生沟道接触并且在第一表面101之上产生源金属层10。此外,可选地能够在平的沟道51的侧壁和/或底壁处形成硅化物。
图9示出了MOSFET 100,其后在背面102之上生成漏金属层11并且该晶圆40沿着更宽深的沟道50a分成单个的半导体构件。
借助于所描述的方法能够非常可靠地并且以较低的工艺变化来生成具有主体区2的雪崩击穿型半导体构件100、200,它们分别具有设置在中央区域2c之中的第二部分区域2b,其与漂移区1形成pn结14的一部分并且具有更高的最大掺杂浓度和/或比该主体区2的与第二部分区域2b相邻的第一部分区域2a更深地延伸入漂移区1之中。
尽管本发明公开了不同的示例性的实施形式,但是对于专业人员来说能够对其进行不同的改变或者修改是显而易见的,借助于这样的改变和修改能够达到本发明的一些优点而不会由此偏离本发明的实质和范围。此外,利用实现相同的功能的其它的部件来相应地加以替换对于普通的专业人员来说也是显而易见的。由此可见,参照特定的附图所阐述的特征能够与其他附图的特征相互组合,也就是说在一些情况下这些特征并未加以表述。这样的对于本发明的构思的修改应当由所附的权利要求书加以总结。
空间上的概念诸如“下”、“下面”、“下面的”、“上”、“上面的”以及诸如此类的将有利于更好的描述地加以使用,以便描述一个元件相对第二元件的相对位置。这些概念应当包括除了在附图中所描述的不同的方向之外的构件的不同的方向。此外,诸如“第一”、“第二”和此类的表述也被用于描述不同的元件、区域、范围等并且同样地并不用于限制。在整个说明书中相同的概念描述相同的元件。
在此的语言使用中,概念“具有”、“含有”、“包含”、“包括”和诸如此类的通常包含所示出的元件或者特征的存在的概念但是并不排除额外的元件或者特征。冠词“一个”和“该”应该包括复数和单数,只要未在上下文中明确另外地加以给出的话。
鉴于上面的变型和应用领域能够得出:本发明既不会通过前述的说明书也不会通过附图加以限制。与之相反地,本发明仅仅通过后面的权利要求书和其法律等同物来加以限制。
Claims (20)
1.一种场效应构件(100),其包括半导体主体(40),所述半导体主体在边缘区域(120)从背面(102)延伸至所述半导体主体(40)的表面(101),并且所述半导体主体包括半导体台面(20),所述半导体台面以垂直于所述背面(102)和/或所述表面(101)的竖直的方向延伸至安置在所述表面(101)之上的一个高度(hM)处的半导体台面顶侧(103),其中,所述半导体主体(40)在竖直的横截面中还包括:
-漂移区(1),所述漂移区至少在所述边缘区域中延伸至所述表面(101)并且部分地安置在所述半导体台面(20)之中;以及
-至少部分地安置在所述半导体台面(20)之中的主体区(2),所述主体区与所述漂移区(1)形成第一pn结(14),所述第一pn结在所述半导体台面(20)的两个侧壁(21)之间延伸,其中,所述第一pn结(14)在水平方向上离所述半导体台面顶侧(103)的垂直距离(d)会变化并且在由两个侧壁(21)隔开的中央区域(2c)中采用最大的值(d1),并且其中,所述最大的值(d1)至少为所述高度(hM)的70%。
2.根据权利要求1所述的场效应构件(100),其中,所述最大的值(d1)小于所述高度(hM)的200%。
3.根据前述权利要求中任一项所述的场效应构件(100),其中,所述主体区(2)具有安置在所述中央区域(2c)中的第二部分区域(2b),所述第二部分区域与所述漂移区(1)形成所述第一pn结(14)的一部分并且具有比与所述第二部分区域(2b)相邻的第一部分区域(2a)更高的最大掺杂浓度。
4.根据前述权利要求中任一项所述的场效应构件(100),其中,所述第一pn结(14)在所述竖直的横截面中关于竖直的轴是镜像对称或者不对称。
5.根据前述权利要求中任一项所述的场效应构件(100),其中,所述半导体台面(20)在所述竖直的横截面中具有另一个安置在所述主体区(2)上的源区(3),所述源区与所述主体区(2)形成第二pn结(15)。
6.根据权利要求5所述的场效应构件(100),在所述竖直的横截面之中还包括安置在多个侧壁(21)中的至少一个上的栅极介电区域(30、33)、安置在所述栅极介电区域(33)上的栅极(12)、安置在所述半导体主体(40)上的与所述主体区(2)和所述源区(3)欧姆式接触的源金属层(10)和/或安置在所述背面(102)上的与所述漂移区(1)欧姆式接触的漏金属层(11)。
7.根据权利要求6所述的场效应构件(100),其中,所述源金属层(10)和所述栅极(12)安置在所述表面(101)之上。
8.根据权利要求6或7所述的场效应构件(100),其中,所述半导体主体(40)还包括在所述背面(102)和所述表面(101)之间延伸的侧面(41)和至少一个边缘闭合结构(12b),所述边缘闭合结构在顶视图中安置在所述半导体台面(20)和所述侧面(41)之间。
9.根据权利要求6至8中任一项所述的场效应构件(100),还包括平的沟道(51),所述沟道在所述中央区域(2c)中从所述半导体台面顶侧(103)延伸入所述主体区(2)和/或延伸至所述主体区(2)的所述第一部分区域(2a)。
10.根据前述权利要求中任一项所述的场效应构件(100),其中,所述半导体主体(40)在激活的区域(110)具有多个半导体台面(20)。
11.根据权利要求10所述的场效应构件(100),在所述激活的区域(110)中还包括温度传感器、电流传感器和/或栅极指。
12.根据权利要求10或11所述的场效应构件(100),在所述激活的区域(110)中还包括另一个半导体台面(20),所述另一个半导体台面包括主体区(2),所述主体区与所述漂移区(1)形成pn结(14),其中,所述另一个半导体台面(20)的主体区(2)在竖直的方向上并不和所述半导体台面(20)的所述主体区(2)一样深地延伸入所述漂移区(1)。
13.一种场效应构件(100),包括半导体主体(40),所述半导体主体在边缘区域(120)从背面(102)延伸至表面(101),并且所述半导体主体包括半导体台面(20),所述半导体台面以平行于所述背面(102)的法向量(en)和/或所述表面(101)的法向量(en)的竖直的方向延伸至安置在所述表面(101)之上的半导体台面顶侧(103),其中,所述半导体主体(40)在竖直的横截面中还包括:
-漂移区(1),所述漂移区至少在所述边缘区域中延伸至所述表面(101)并且部分地安置在所述半导体台面(20)之中;以及
-至少部分地安置在所述半导体台面(20)之中的主体区(2),所述主体区包括两个分别与所述半导体台面(20)的两个侧壁(21)中的一个相邻的第一部分区域(2a)和在两个第一部分区域(2a)之间安置的第二部分区域(2b),其中,所述两个第一部分区域(2a)和所述第二部分区域(2b)与所述漂移区(1)形成第一pn结(14),所述第一pn结在所述半导体台面(20)的两个侧壁(21)之间延伸,其中,所述第二部分区域(2b)在所述漂移区(1)竖直地比所述两个第一部分区域(2a)更深地加以延伸,并且其中,所述第二部分区域(2b)具有比所述两个第一部分区域(2a)更大的最大掺杂浓度。
14.根据权利要求13所述的场效应构件(100),其中,在所述半导体台面顶侧(103)和所述第一pn结(14)的在所述两个第一部分区域(2a)中的一个和所述漂移区(1)之间形成的第一分段之间的最大的竖直第一距离(d2)小于在所述半导体台面顶侧(103)和所述表面(101)之间的竖直的距离(hM),和/或其中,在所述半导体台面顶侧(103)和所述第一pn结(14)的在所述第二部分区域(2b)和所述漂移区(1)之间形成的第二分段之间的最大的竖直第二距离(d1)处于所述竖直的距离(hM)的80%至150%的范围之中。
15.一种用于制造场效应构件(100)的方法,包括:
-提供晶圆(40),所述晶圆包括第一功率类型的第一半导体层(1)、安置在所述第一半导体层(1)之上的第二功率类型的第二半导体层(2)和安置在所述第二半导体层(2)之上的第三半导体层(3),所述第二半导体层与所述第一半导体层(1)形成第一pn结(14),所述第三半导体层与所述第二半导体层(2)形成第二pn结(15)并且延伸至所述晶圆(40)的顶侧(103);
-在所述晶圆(40)的所述顶侧(103)之上形成具有多个开口的台面掩膜(7);
-通过所述台面掩膜(7)来蚀刻所述晶圆(40),使得产生多个深的沟道(50、50a)和安置在所述多个深的沟道(50、50a)之间的多个半导体台面(20),其中,所述多个深的沟道(50、50a)延伸入所述第一半导体层(1);以及
-将所述第一功率类型的掺杂物注入至少一个与所述第一pn结(14)相邻的半导体区域。
16.根据权利要求15所述的方法,还包括在所述多个深的沟道(50)中的至少若干个之中形成绝缘的栅极(12、33),和/或在所述半导体台面(20)之中形成所述表面(103)的多个平的沟道(51)。
17.根据权利要求15或16所述的方法,还包括在所述半导体构件之中沿着所述多个深的沟道(50a)中的若干个来分离所述晶圆(40)。
18.根据权利要求15至17中的任一项所述的方法,还包括调温步骤,其中,提供具有相互平行的第一pn结(14)和第二pn结(15)的所述晶圆(40),并且其中,所述如法如此地实施,使得所述第一pn结(14)在所述调温步骤之后在所述多个半导体台面(20)的至少一个之中在中央区域(2c)中竖直地比在所述至少一个半导体台面(20)的侧壁(21)上更深地延伸入所述第一半导体层(1)。
19.根据权利要求15至18中的任一项所述的方法,所述方法如此地加以实施,使得在所述多个半导体台面(20)的至少一个中在由所述至少一个半导体台面(20)的多个侧壁(21)隔开的中央区域(2c)中的掺杂浓度提高到所述第一pn结(14)之上。
20.根据权利要求18至19中的任一项所述的方法,其中,所述方法如此地加以实施,使得所述第一半导体层(1)在所述半导体台面(20)之外形成第一表面(101),所述第一表面位于离所述顶侧(103)一个竖直的距离(hM)处,其中,在所述顶侧(103)和所述第一pn结(14)的与所述多个半导体台面(20)中的一个的侧壁(21)相邻的第一分段之间的竖直的第一距离(d2)小于在所述顶侧(103)和所述第一pn结(14)的与所述第一pn结(14)的第一分段相邻的第二分段之间的竖直第二距离(d1),并且所述第一距离(d2)处于在所述顶侧(103)和所述第一表面(101)之间的竖直的距离(hM)的80%至150%的范围之中。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711433835.6A CN108231868B (zh) | 2013-10-30 | 2014-10-29 | 场效应半导体构件及其制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102013111966.2 | 2013-10-30 | ||
DE102013111966.2A DE102013111966B4 (de) | 2013-10-30 | 2013-10-30 | Feldeffekthalbleiterbauelement und Verfahren zu dessen Herstellung |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711433835.6A Division CN108231868B (zh) | 2013-10-30 | 2014-10-29 | 场效应半导体构件及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104600116A true CN104600116A (zh) | 2015-05-06 |
CN104600116B CN104600116B (zh) | 2018-01-30 |
Family
ID=52811511
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711433835.6A Active CN108231868B (zh) | 2013-10-30 | 2014-10-29 | 场效应半导体构件及其制造方法 |
CN201410592595.4A Active CN104600116B (zh) | 2013-10-30 | 2014-10-29 | 场效应半导体构件及其制造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711433835.6A Active CN108231868B (zh) | 2013-10-30 | 2014-10-29 | 场效应半导体构件及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9391192B2 (zh) |
CN (2) | CN108231868B (zh) |
DE (1) | DE102013111966B4 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108878514A (zh) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | 沟槽栅超结器件及其制造方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9136397B2 (en) | 2013-05-31 | 2015-09-15 | Infineon Technologies Ag | Field-effect semiconductor device |
US9184281B2 (en) | 2013-10-30 | 2015-11-10 | Infineon Technologies Ag | Method for manufacturing a vertical semiconductor device and vertical semiconductor device |
DE102013111966B4 (de) * | 2013-10-30 | 2017-11-02 | Infineon Technologies Ag | Feldeffekthalbleiterbauelement und Verfahren zu dessen Herstellung |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020100933A1 (en) * | 2001-01-30 | 2002-08-01 | Marchant Bruce D. | Field effect transistor having a lateral depletion structure |
CN1729578A (zh) * | 2002-12-19 | 2006-02-01 | 西利康尼克斯股份有限公司 | 具有注入漏极漂移区和厚底部氧化物的沟槽金属-绝缘体-半导体器件及其制造方法 |
CN101719495A (zh) * | 2008-09-30 | 2010-06-02 | 英飞凌科技奥地利有限公司 | 半导体器件及其制造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4887145A (en) * | 1985-12-04 | 1989-12-12 | Hitachi, Ltd. | Semiconductor device in which electrodes are formed in a self-aligned manner |
US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US6764906B2 (en) * | 2001-07-03 | 2004-07-20 | Siliconix Incorporated | Method for making trench mosfet having implanted drain-drift region |
EP1465038B1 (en) | 2003-04-03 | 2013-03-27 | STMicroelectronics (Research & Development) Limited | Memory security device for flexible software environment |
US6979863B2 (en) * | 2003-04-24 | 2005-12-27 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
US7652326B2 (en) * | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US7118970B2 (en) * | 2004-06-22 | 2006-10-10 | Cree, Inc. | Methods of fabricating silicon carbide devices with hybrid well regions |
CN100517719C (zh) * | 2004-06-30 | 2009-07-22 | 先进模拟科技公司 | 有凹进箝位二极管的沟槽金属氧化物半导体场效应晶体管 |
JP4939760B2 (ja) * | 2005-03-01 | 2012-05-30 | 株式会社東芝 | 半導体装置 |
DE112006001516T5 (de) | 2005-06-10 | 2008-04-17 | Fairchild Semiconductor Corp. | Feldeffekttransistor mit Ladungsgleichgewicht |
US7541660B2 (en) * | 2006-04-20 | 2009-06-02 | Infineon Technologies Austria Ag | Power semiconductor device |
US9252251B2 (en) * | 2006-08-03 | 2016-02-02 | Infineon Technologies Austria Ag | Semiconductor component with a space saving edge structure |
DE102007030755B3 (de) * | 2007-07-02 | 2009-02-19 | Infineon Technologies Austria Ag | Halbleiterbauelement mit einem einen Graben aufweisenden Randabschluss und Verfahren zur Herstellung eines Randabschlusses |
US8013340B2 (en) * | 2008-09-30 | 2011-09-06 | Infineon Technologies Ag | Semiconductor device with semiconductor body and method for the production of a semiconductor device |
US8497552B2 (en) * | 2008-12-01 | 2013-07-30 | Cree, Inc. | Semiconductor devices with current shifting regions and related methods |
US9396997B2 (en) * | 2010-12-10 | 2016-07-19 | Infineon Technologies Ag | Method for producing a semiconductor component with insulated semiconductor mesas |
US8754472B2 (en) * | 2011-03-10 | 2014-06-17 | O2Micro, Inc. | Methods for fabricating transistors including one or more circular trenches |
US9318623B2 (en) * | 2011-04-05 | 2016-04-19 | Cree, Inc. | Recessed termination structures and methods of fabricating electronic devices including recessed termination structures |
US8759935B2 (en) * | 2011-06-03 | 2014-06-24 | Infineon Technologies Austria Ag | Power semiconductor device with high blocking voltage capacity |
US8680587B2 (en) * | 2011-09-11 | 2014-03-25 | Cree, Inc. | Schottky diode |
DE102013111966B4 (de) * | 2013-10-30 | 2017-11-02 | Infineon Technologies Ag | Feldeffekthalbleiterbauelement und Verfahren zu dessen Herstellung |
-
2013
- 2013-10-30 DE DE102013111966.2A patent/DE102013111966B4/de active Active
-
2014
- 2014-10-28 US US14/525,398 patent/US9391192B2/en active Active
- 2014-10-29 CN CN201711433835.6A patent/CN108231868B/zh active Active
- 2014-10-29 CN CN201410592595.4A patent/CN104600116B/zh active Active
-
2016
- 2016-05-31 US US15/169,290 patent/US9847387B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020100933A1 (en) * | 2001-01-30 | 2002-08-01 | Marchant Bruce D. | Field effect transistor having a lateral depletion structure |
CN1729578A (zh) * | 2002-12-19 | 2006-02-01 | 西利康尼克斯股份有限公司 | 具有注入漏极漂移区和厚底部氧化物的沟槽金属-绝缘体-半导体器件及其制造方法 |
CN101719495A (zh) * | 2008-09-30 | 2010-06-02 | 英飞凌科技奥地利有限公司 | 半导体器件及其制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108878514A (zh) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | 沟槽栅超结器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN108231868B (zh) | 2022-01-14 |
US9391192B2 (en) | 2016-07-12 |
DE102013111966A1 (de) | 2015-04-30 |
US20160284795A1 (en) | 2016-09-29 |
CN108231868A (zh) | 2018-06-29 |
US9847387B2 (en) | 2017-12-19 |
CN104600116B (zh) | 2018-01-30 |
US20150115353A1 (en) | 2015-04-30 |
DE102013111966B4 (de) | 2017-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US12034065B2 (en) | Semiconductor device including emitter regions and method of manufacturing the semiconductor device | |
CN104518010B (zh) | 集成电路和制造集成电路的方法 | |
JP6006918B2 (ja) | 半導体装置、半導体装置の製造方法、及び電子装置 | |
CN103187442B (zh) | 集成异质结半导体器件和用于生产该半导体器件的方法 | |
CN104599971B (zh) | 用于制造竖直半导体器件的方法和竖直半导体器件 | |
CN102956680A (zh) | 半导体器件及形成半导体器件的方法 | |
CN103972292A (zh) | 半导体装置及其制造方法 | |
CN109244140A (zh) | Ldmos器件及其制造方法 | |
CN104299997A (zh) | 电荷补偿半导体器件 | |
CN107026207A (zh) | 包括横向晶体管的半导体器件 | |
US7436025B2 (en) | Termination structures for super junction devices | |
CN104518032A (zh) | 半导体器件及其制造方法 | |
CN105027290B (zh) | 自适应电荷平衡的mosfet技术 | |
CN104600116A (zh) | 场效应半导体构件及其制造方法 | |
US8455953B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
KR102088181B1 (ko) | 반도체 트랜지스터 및 그 제조 방법 | |
CN102347364B (zh) | 具有漂移区域和补偿区域的半导体器件 | |
US10326013B2 (en) | Method of forming a field-effect transistor (FET) or other semiconductor device with front-side source and drain contacts | |
US20150263163A1 (en) | Semiconductor device | |
US20180145171A1 (en) | Field Effect Transistor (FET) or Other Semiconductor Device with Front-Side Source and Drain Contacts | |
CN114203818A (zh) | 半导体装置 | |
KR20090068561A (ko) | 반도체 소자의 제조방법 | |
EP4328977A1 (en) | Laterally diffused metal oxide semiconductor structure | |
JP2013077662A (ja) | 半導体装置およびその製造方法 | |
JP6110900B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |