CN104283201B - Input stage esd protection circuit - Google Patents
Input stage esd protection circuit Download PDFInfo
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- CN104283201B CN104283201B CN201410461667.1A CN201410461667A CN104283201B CN 104283201 B CN104283201 B CN 104283201B CN 201410461667 A CN201410461667 A CN 201410461667A CN 104283201 B CN104283201 B CN 104283201B
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Abstract
The invention discloses an input stage ESD protection circuit which comprises a power source clamp ESD protection circuit, a ballast module, a transmission gate module, a phase inverter driving module and a diode module. According to the input stage ESD protection circuit, existing detection signal resources in the power source clamp ESD protection circuit are reasonably utilized, the transmission gate module and the ballast module are synchronous driven, it is effectively achieved that electrostatic charges are released through a designed releasing channel under the worst ESD impact situation, the undamped transmission of data is ensured when a chip is normally operated, and meanwhile it is ensured that the additional domain overhead brought to the chip by the ESD protection design is quite small.
Description
Technical field
The present invention relates to integrated circuit electrostatic discharge resist technology field, it is more particularly to a kind of input stage ESD protection electricity
Road.
Background technology
Static discharge (Electronic Static Discharge, ESD) phenomenon is that common physics in daily life is existing
As going to contact the object of other low-resistances after the object with electric charge goes to touch chip pin or the upper electrostatic of chip oneself band
When, electric charge can shift between not iso-electric object.The transfer process of electric charge is the process of transient high-current, for collection
For becoming circuit chip, the transient high-current pulse being brought by esd event can frequently result in the inefficacy of semiconductor device in chip.
The either ESD impact of any pattern, its instantaneous peak point current is attained by several or even tens of amperes of magnitude, significantly
Exceed the electric current normal range of operation of semiconductor device in integrated circuit.
There is provided ESD protection on piece for chip is semiconductor industry with regard to the emphasis of reliability design and difficult point, full chip
ESD Preservation tactics require for the positively and negatively ESD impact pattern between any pin, and protection circuit can be effectively electrostatic electricity
Lotus provides the path of releasing of low-resistance.Input stage esd protection circuit is mainly between input pressure welding point and other different pins
ESD impact provides effective charge discharging resisting path, because the latter linked One function of the input pressure welding point of most of chip
Circuit module is input stage phase inverter, so, the gate oxide of protection input stage phase inverter is the design of input stage esd protection circuit
Principal concern.
Fig. 1 is the structural representation of common input stage esd protection circuit under traditional handicraft, in Fig. 1, in pressure welding point over the ground
Positive ESD impact under, electrostatic charge is released to ground by diode D1 and power clamp ESD protective circuit, in the case,
The bleeder resistance flowing through on charge discharging resisting path is maximum, causes the clamp voltage in pressure welding point maximum, so this situation is input
The worst case that level esd protection circuit design faces.In traditional handicraft, because the thickness of gate oxide is thicker, input stage is anti-
The gate oxide of phase device generally can bear certain high pressure, in addition resistance R in Fig. 1bTo the gate oxide of input stage phase inverter and
Buffer action between pressure welding point, the problem of over-voltage breakdown not under ESD impact in the gate oxide of input stage phase inverter
It is very severe.
The progress of technique allows the semiconductor device in integrated circuit do less and less, and correspondingly, its breakdown voltage is also increasingly
Little.Under advanced technique, the gate oxide of input stage phase inverter when there is the ESD impact of worst case in input, normal face
Face because overvoltage and lead to puncture inefficacy, now, traditional input stage esd protection circuit be no longer able to effective protection input
The gate oxide of level phase inverter.
Content of the invention
(1) technical problem to be solved
The technical problem to be solved in the present invention is input stage esd protection circuit energy how in the ESD impact of worst case
The high current that enough effective static electricity discharge impacts bring, protects the gate oxide of input stage phase inverter not breakdown, and ensures
The undamped transmission of data under normal circumstances, makes the chip area Least-cost that ESD protection brings simultaneously.
(2) technical scheme
In order to solve above-mentioned technical problem, the invention provides a kind of input stage esd protection circuit is it is characterised in that wrap
Include diode (led) module, power clamp ESD protective circuit, ballasting module, transmission gate module, inverter drive module；
When described diode (led) module is used for, between pressure welding point and other chip pin, ESD impact occurs, effectively by electrostatic
Electric charge is directed to releasing on path of designing, in chip normal work, provides data path and power line VDDBetween every
From；
Described power clamp ESD protective circuit is used for detecting described power line VDDAnd the over-pressed thing occurring in pressure welding point
Part, when there being ESD impact to cause over-pressed phenomenon, described power clamp ESD protective circuit sends useful signal, triggers crystal of releasing
Pipe turns on, and disconnects the electrical connection between pressure welding point and input stage phase inverter gate oxide, and increase input stage phase inverter with described
Power line VDDBetween connect resistance it is ensured that electrostatic charge passes through the path of releasing that designs releases, there is no over-voltage events quilt
It is ensured that the undamped transmission of data when detecting, and the transistor that ensures to release is in strict off state；
Described inverter drive module is used for driving described biography according to the signal that described power clamp ESD protective circuit provides
Defeated door module and described ballasting module, make the transmission gate transistor in two modules when the esd event of worst case occurs, complete
Fully closed disconnected, in data transfer, fully open；
Described ballasting module is used for the drive signal sending according to described inverter drive module, dynamically changes input stage
Phase inverter PMOS transistor MpSource electrode and described power line VDDBetween resistance, when an esd event occurs, increase input stage anti-
The M of phase device PMOS transistorpSource electrode and described power line VDDBetween resistance it is ensured that electrostatic charge pass through design release
Path is released, and in chip normal operating, significantly reduces input stage phase inverter PMOS transistor MpSource electrode and described power line
VDDBetween resistance it is ensured that voltage is unattenuated；
Described transmission gate module is used for the drive signal sending according to described inverter drive module, occurs in over-voltage events
When, disconnect the electrical connection between pressure welding point and the gate oxide of input stage phase inverter, meanwhile, force the input input stage phase inverter
Voltage bias to zero, in chip normal operating it is ensured that the normal transmission of data.
Preferably, described power clamp ESD circuit includes the transistor M that releasesbig, resistance R, R2, diode D3、D4、D5、D6,
PMOS transistor Mp1, nmos pass transistor Mfb, phase inverter INV4, INV5；The described transistor M that releasesbigFor nmos pass transistor, its grid
Pole connects described inverter drive module；One end of described resistance R, described PMOS transistor Mp1Source electrode, described crystal of releasing
Pipe MbigDrain electrode all with described power line VDDConnect；The other end of described resistance R and described diode D3Input, described
PMOS transistor Mp1Grid, described nmos pass transistor MfbDrain electrode connect；Described PMOS transistor Mp1Drain electrode, described
Nmos pass transistor MfbGrid, described resistance R2One end be all connected with the input of described phase inverter INV4；Described phase inverter
The outfan of INV4 is connected with the input of described phase inverter INV5, the outfan of described phase inverter INV5 and described crystal of releasing
Pipe MbigGrid connect, described supply voltage VDDPower for described phase inverter INV4, INV5；Described diode D3Negative electrode with
Described diode D4Anode connect, described diode D4Negative electrode and described diode D5Anode connect, described diode D5
Negative electrode and described diode D6Anode connect, described diode D6Negative electrode, described nmos pass transistor MfbSource electrode, described
Resistance R2The other end, the described transistor M that releasesbigSource electrode all with described ground wire VSSConnect.
Preferably, described inverter drive module includes phase inverter INV1, INV2, INV3；The described transistor M that releasesbig's
Grid voltage is driven through described phase inverter INV1, INV2, output overvoltage detectable signal ESD；Described overvoltage detectable signal
ESD carries out logic reversal through described phase inverter INV3, output reversely over-pressed detectable signal ESDX；Pressure welding point voltage is described anti-
Phase device INV1, INV2 are powered, supply voltage VDDPower for described phase inverter INV3.
Preferably, described ballasting module includes nmos pass transistor Mnb, PMOS transistor MpbAnd resistance R1；
Described nmos pass transistor MnbGrid by described reverse overvoltage detectable signal ESDX drive, described PMOS transistor
MpbGrid by described overvoltage detectable signal ESD drive；Described nmos pass transistor MnbDrain electrode, described PMOS transistor Mpb
Source electrode, described resistance R1One end be all connected with described power line VDD；Described nmos pass transistor MnbSource electrode, described PMOS crystal
Pipe MpbDrain electrode, described resistance R1The other end be all connected with inputting PMOS transistor M in pole phase inverterpSource electrode.
Preferably, described transmission gate module includes PMOS transistor Mpt, nmos pass transistor Mnta, nmos pass transistor Mnt；
Described PMOS transistor Mpt, nmos pass transistor MntaGrid all by described overvoltage detectable signal ESD drive, institute
State nmos pass transistor MntGrid by described reverse overvoltage detectable signal ESDX drive；Described PMOS transistor MptSource electrode,
Described nmos pass transistor MntDrain electrode be all connected with described pressure welding point；Described PMOS transistor MptDrain electrode, described nmos pass transistor
MntSource electrode, described nmos pass transistor MntaDrain electrode be all connected with the input of described input stage phase inverter；Described nmos pass transistor
MntaSource ground.
Preferably, described phase inverter INV1, INV2, INV3, INV4, INV5 are CMOS inverter.
(3) beneficial effect
The invention provides a kind of input stage esd protection circuit, by rationally utilizing in power clamp ESD protective circuit
Some detectable signal resources, synchronization is driven to transmission gate module and ballasting module, effectively achieves in the worst ESD impact feelings
Under condition, electrostatic charge passes through the path of releasing that designs and releases, in chip normal operating it is ensured that the undamped transmission of data,
Simultaneously it is ensured that the extra domain expense very little brought to chip of ESD design protection.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the structural representation of common input stage esd protection circuit in traditional handicraft；
Fig. 2 is the structural representation of the input stage esd protection circuit of the present invention；
Fig. 3 is the circuit diagram of the input stage esd protection circuit of the present invention；
Fig. 4 be the input stage esd protection circuit of the present invention when IN end carries out back stagnant dc sweeps, IN1 end, overvoltage detect
Signal, reversely over-pressed detectable signal are with the simulation result schematic diagram returning stagnant scanning voltage change；
When Fig. 5 is chip normal work, IN end in the input stage esd protection circuit of the present invention, IN1 end, INNER end and
The time dependent simulation result schematic diagram of voltage of over-pressed detectable signal.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is described in further detail.Following examples are used for this is described
Bright, but can not be used for limiting the scope of the present invention.
Fig. 2 is the structural representation of the input stage esd protection circuit of the present invention, and described input stage esd protection circuit includes
Diode (led) module, power clamp ESD protective circuit, ballasting module, transmission gate module, inverter drive module.
When described diode (led) module is used for, between pressure welding point and other chip pin, ESD impact occurs, effectively by electrostatic
Electric charge is directed to releasing on path of designing, in chip normal work, provides data path and power line VDDBetween every
From.
Described power clamp ESD protective circuit is used for detecting described power line VDDAnd the over-pressed thing occurring in pressure welding point
Part, when there being ESD impact to cause over-pressed phenomenon, power clamp ESD protective circuit sends useful signal, triggers transistor of releasing and leads
Logical, disconnect the electrical connection between pressure welding point and input stage phase inverter gate oxide, and increase input stage phase inverter and described power supply
Line VDDBetween connect resistance it is ensured that electrostatic charge passes through the path of releasing that designs releases, be detected there is no over-voltage events
Then it is ensured that the undamped transmission of data, and the transistor that ensures to release is in strict off state.
Described inverter drive module is used for driving transmission gate module according to the signal that power clamp ESD protective circuit provides
And ballasting module, make the transmission gate transistor in two modules when the esd event of worst case occurs, complete switch off, counting
According to during transmission, fully open.
Described ballasting module is used for the drive signal sending according to inverter drive module, and dynamic change input stage is anti-phase
Device PMOS transistor MpSource electrode and described VDDBetween resistance, when an esd event occurs, increase input stage phase inverter PMOS brilliant
The M of body pipepSource electrode and described power line VDDBetween resistance it is ensured that electrostatic charge passes through the path of releasing that designs releases,
In chip normal operating, significantly reduce input stage phase inverter PMOS transistor MpSource electrode and described power line VDDBetween electricity
Resistance is it is ensured that voltage is unattenuated.
Described transmission gate module is used for the drive signal sending according to inverter drive module, when over-voltage events occur,
Disconnect the electrical connection between pressure welding point and the gate oxide of input stage phase inverter, meanwhile, force the input electricity input stage phase inverter
Pressure is biased to zero, in chip normal operating it is ensured that the normal transmission of data.
The input stage esd protection circuit that the present invention provides, existing in power clamp ESD protective circuit by rationally utilizing
Detectable signal resource, synchronization is driven to transmission gate module and ballasting module, effectively achieves in the worst ESD impact situation
Under, the path of releasing that electrostatic charge passes through to design is released, in chip normal operating it is ensured that the undamped transmission of data, same
When it is ensured that the extra domain expense very little brought to chip of ESD design protection.
Fig. 3 is the circuit diagram of the input stage esd protection circuit of the present invention；Described diode (led) module includes diode D1, two
Pole pipe and D2.Described diode D1Anode be connected with the pressure welding point of described input stage esd protection circuit, described diode D1's
Negative electrode and the described power line V of described input stage esd protection circuitDDIt is connected.Described diode D2Anode and described input stage
The described ground wire V of esd protection circuitSSIt is connected, described diode D2Negative electrode and described input stage esd protection circuit pressure welding point
It is connected.
Described power clamp ESD circuit includes the transistor M that releasesbig, resistance R, R2, diode D3、D4、D5、D6, PMOS crystalline substance
Body pipe Mp1, nmos pass transistor Mfb, phase inverter INV4, INV5；The described transistor M that releases releasing on pathbigFor NMOS crystal
Pipe, its grid connects described inverter drive module.One end of described resistance R, described PMOS transistor Mp1Source electrode, described let out
Put transistor MbigDrain electrode all with described power line VDDConnect；The other end of described resistance R and the input of described diode D3
End, described PMOS transistor Mp1Grid, described nmos pass transistor MfbDrain electrode connect；Described PMOS transistor Mp1Drain electrode,
Described nmos pass transistor MfbGrid, described resistance R2One end be all connected with the input of described phase inverter INV4；Described anti-
The outfan of phase device INV4 is connected with the input of described phase inverter INV5, and the outfan of described phase inverter INV5 is released with described
Transistor MbigGrid connect, described supply voltage powers for described phase inverter INV4, INV5；Described diode D3Negative electrode
With described diode D4Anode connect, described diode D4Negative electrode and described diode D5Anode connect, described diode
D5Negative electrode and described diode D6Anode connect, described diode D6Negative electrode, described nmos pass transistor MfbSource electrode, institute
State resistance R2The other end, the described transistor M that releasesbigSource electrode all with described ground wire VSSConnect.Preferably described phase inverter
INV4, INV5 are CMOS inverter.
Described inverter drive module includes phase inverter INV1, INV2, INV3, and the input of described phase inverter INV1 connects
The described transistor M that releasesbigGrid, its outfan connect described phase inverter INV2 input；Described phase inverter INV2's is defeated
Go out end and connect described phase inverter INV3 input, the output signal of described phase inverter INV3 is reversely over-pressed detectable signal ESDX,
The output signal of described phase inverter INV2 is over-pressed detectable signal ESD；The voltage of described pressure welding point, that is, end points IN voltage is described
Phase inverter INV1, INV2 power；Described supply voltage is powered for described phase inverter INV3.Described phase inverter INV1, INV2, INV3
It is preferably CMOS inverter.
Described ballasting module includes described ballasting module and includes nmos pass transistor Mnb, PMOS transistor MpbAnd resistance R1；
Described nmos pass transistor MnbGrid by described reverse overvoltage detectable signal ESDX drive, described PMOS transistor MPbGrid
Pole is driven by described overvoltage detectable signal ESD；Described nmos pass transistor MnbDrain electrode, described PMOS transistor MpbSource electrode,
Described resistance R1One end be all connected with described power line VDD；Described nmos pass transistor MnbSource electrode, described PMOS transistor Mpb's
Drain electrode, described resistance R1The other end be all connected with inputting PMOS transistor M in pole phase inverterpSource electrode.Described input pole phase inverter
Including PMOS transistor Mp, nmos pass transistor Mn, described PMOS transistor MpDrain electrode and described nmos pass transistor MnDrain electrode,
Internal circuit connects, described PMOS transistor MpGrid connect described nmos pass transistor MnGrid connect, described NMOS crystal
Pipe MnSource electrode connect described ground wire VSS.
Described transmission gate module includes PMOS transistor Mpt, nmos pass transistor Mnta, nmos pass transistor Mnt；Described PMOS is brilliant
Body pipe Mpt, nmos pass transistor MntaGrid all by described overvoltage detectable signal ESD drive, described nmos pass transistor MntGrid
Extremely described reverse overvoltage detectable signal ESDX is driven；Described PMOS transistor MptSource electrode, described nmos pass transistor MntLeakage
Pole is all connected with described pressure welding point；Described PMOS transistor MptDrain electrode, described nmos pass transistor MntSource electrode, described NMOS brilliant
Body pipe MntaDrain electrode be all connected with the input of described input stage phase inverter；Described nmos pass transistor MntaSource ground.
As shown in figure 3, when the esd event of worst case occurs, over-pressed phenomenon primarily occur ins pressure welding point.Due to pressure welding
Point and described power line VDDBetween there is forward biased diode D1, therefore power line VDDOn over-pressed phenomenon, power supply also occur
Line VDDOn over-pressed phenomenon by resistance R and diode D3、D4、D5And D6Detected, now, PMOS transistor Mp1Drain electrode output
Logic high, this level is exactly the significant level that over-voltage events occur.PMOS transistor Mp1The logic high of drain terminal is first
After two-stage phase inverter INV4, INV5, trigger the transistor M that releasesbig, meanwhile, release transistor MbigGrid voltage warp again
After crossing inverter drive module drive, export effectively over-pressed detectable signal ESD and reversely over-pressed detectable signal ESDX, described anti-
In phase device drive module, the supply voltage of phase inverter is designed without being consistent, and this is by transmission gate module and ballasting module
Transistor needs to complete switch off under the ESD impact event of worst case, in chip normal operating, needs full opening of setting
Meter requires to determine.After transmission gate module receives effective ESD signal and ESDX signal, transmission gate transistor MptAnd MntCompletely
Turn off, disconnect the electrical connection between input stage inverter input and pressure welding point, meanwhile, nmos pass transistor MntaIt is biased into leading
Logical state, forces the input signal zero setting input stage phase inverter, and more one step ensure that the safety of its gate oxide.Ballasting module
After receiving effective ESD signal and ESDX signal, transmission gate transistor MpbAnd MnbComplete switch off, they are with resistance R1After parallel connection
In described power line VDDForm larger resistance and input stage phase inverter between it is ensured that PMOS transistor in input stage phase inverter
MpDo not become the weakness of electrostatic breakdown.
Taking the integrated circuit technology of 65nm as a example, the normal working voltage of chip is 2.5V, the grid oxygen of input stage phase inverter
Change layer breakdown voltage is 6.0V.Fig. 4 show time stagnant scanning simulation result of over-voltage events, as seen from the figure：At IN end relatively
When the positive overvoltage on ground reaches 4.8V, low, the generation of indication over-voltage events is jumped in ESD signal high jump, ESDX signal, now
The not change followed by IN signal of IN1 signal after transmission gate module, but be forced to be biased to zero.Using reverse scan when
Wait, the result of Fig. 4 shows：The trip point that IN1 signal follows IN signal intensity again is lower than the trip point departing from before, this be by
Nmos pass transistor M in power clamp ESD protective circuitfbDetermine, adjust MfbSize can change between two trip points
Away from.In Fig. 4, the saltus step point voltage that IN1 signal follows IN signal intensity again is 3.8V, the normal operating voltage 2.5V to chip
For, the surplus of 1.3V is enough.
In chip normal work, the MG signal of the input stage esd protection circuit of the present invention is logic low, now
ESD signal and ESDX are respectively logic low and logic high, and indication does not have over-voltage events to occur.Transmission gate transistor MptAnd MntComplete
Full open is it is ensured that the normal transmission of data, transmission gate transistor MpbAnd MnbAlso fully open, make described power line VDDTo input
PMOS transistor M in level phase inverterpThe resistance very little of source is it is ensured that the lossless transmission of voltage.When Fig. 5 is chip normal work
Simulation result schematic diagram, in figure, ESD signal maintains very low level all the time, shows the generation not having over-voltage events, IN end
Signal can smoothly be sent to IN1 end, meanwhile, through reverse transfer to INNER end.
The input stage esd protection circuit of the present invention ensure worst case ESD impact occur when, input stage phase inverter
Gate oxide, is not had it is ensured that the extra domain expense very little brought to chip of ESD design protection by the premise of over-voltage breakdown
Very big actual application value.
Embodiment of above is merely to illustrate the present invention, rather than limitation of the present invention.Although with reference to embodiment to this
Bright be described in detail, it will be understood by those within the art that, technical scheme is carried out various combinations,
Modification or equivalent, without departure from the spirit and scope of technical solution of the present invention, the right that all should cover in the present invention will
Ask in the middle of scope.
Claims (6)
1. a kind of input stage esd protection circuit is it is characterised in that include diode (led) module, power clamp ESD protective circuit, town
Flow module, transmission gate module, inverter drive module；
When described diode (led) module is used for, between pressure welding point and other chip pin, ESD impact occurs, effectively by electrostatic electricity
Lotus is directed to releasing on path of designing, in chip normal work, provides data path and power line VDDBetween isolation；
Described power clamp ESD protective circuit is used for detecting described power line VDDAnd the over-voltage events occurring in pressure welding point, when
When having ESD impact to cause over-pressed phenomenon, described power clamp ESD protective circuit sends useful signal, triggers transistor of releasing and leads
Logical, disconnect the electrical connection between pressure welding point and input stage phase inverter gate oxide, and increase input stage phase inverter and described power supply
Line VDDBetween connect resistance it is ensured that electrostatic charge passes through the path of releasing that designs releases, be detected there is no over-voltage events
Then it is ensured that the undamped transmission of data, and the transistor that ensures to release is in strict off state；
Described inverter drive module is used for driving described transmission gate according to the signal that described power clamp ESD protective circuit provides
Module and described ballasting module, make the transmission gate transistor in two modules when the esd event of worst case occurs, close completely
Disconnected, in data transfer, fully open；
Described ballasting module is used for the drive signal sending according to described inverter drive module, dynamically changes input stage anti-phase
Device PMOS transistor MpSource electrode and described power line VDDBetween resistance, when an esd event occurs, increase input stage phase inverter
The M of PMOS transistorpSource electrode and described power line VDDBetween resistance it is ensured that electrostatic charge passes through the path of releasing that designs
Release, in chip normal operating, significantly reduce input stage phase inverter PMOS transistor MpSource electrode and described power line VDDIt
Between resistance it is ensured that voltage is unattenuated；
Described transmission gate module is used for the drive signal sending according to described inverter drive module, when over-voltage events occur,
Disconnect the electrical connection between pressure welding point and the gate oxide of input stage phase inverter, meanwhile, force the input electricity input stage phase inverter
Pressure is biased to zero, in chip normal operating it is ensured that the normal transmission of data.
2. input stage esd protection circuit according to claim 1 is it is characterised in that described power clamp ESD circuit includes
Release transistor Mbig, resistance R, R2, diode D3、D4、D5、D6, PMOS transistor Mp1, nmos pass transistor Mfb, phase inverter INV4,
INV5；The described transistor M that releasesbigFor nmos pass transistor, its grid described inverter drive module of connection；The one of described resistance R
End, described PMOS transistor Mp1Source electrode, the described transistor M that releasesbigDrain electrode all with described power line VDDConnect；Described electricity
The other end of resistance R and described diode D3Input, described PMOS transistor Mp1Grid, described nmos pass transistor MfbLeakage
Pole connects；Described PMOS transistor Mp1Drain electrode, described nmos pass transistor MfbGrid, described resistance R2One end all with described
The input of phase inverter INV4 connects；The outfan of described phase inverter INV4 is connected with the input of described phase inverter INV5, institute
State the outfan of phase inverter INV5 and the described transistor M that releasesbigGrid connect, described supply voltage VDDFor described phase inverter
INV4, INV5 power；Described diode D3Negative electrode and described diode D4Anode connect, described diode D4Negative electrode with
Described diode D5Anode connect, described diode D5Negative electrode and described diode D6Anode connect, described diode D6
Negative electrode, described nmos pass transistor MfbSource electrode, described resistance R2The other end, the described transistor M that releasesbigSource electrode all with
Ground wire VSSConnect.
3. input stage esd protection circuit according to claim 2 is it is characterised in that described inverter drive module includes
Phase inverter INV1, INV2, INV3；The described transistor M that releasesbigGrid voltage driven through described phase inverter INV1, INV2
Dynamic, output overvoltage detectable signal ESD；Described overvoltage detectable signal ESD carries out logic reversal through described phase inverter INV3, output
Reversely over-pressed detectable signal ESDX；Pressure welding point voltage is powered for described phase inverter INV1, INV2, supply voltage VDDFor described
Phase inverter INV3 powers.
4. input stage esd protection circuit according to claim 3 is it is characterised in that described ballasting module includes NMOS crystalline substance
Body pipe Mnb, PMOS transistor MpbAnd resistance R1；
Described nmos pass transistor MnbGrid by described reverse overvoltage detectable signal ESDX drive, described PMOS transistor MpbGrid
Pole is driven by described overvoltage detectable signal ESD；Described nmos pass transistor MnbDrain electrode, described PMOS transistor MpbSource electrode,
Described resistance R1One end be all connected with described power line VDD；Described nmos pass transistor MnbSource electrode, described PMOS transistor Mpb's
Drain electrode, described resistance R1The other end be all connected with PMOS transistor M in input stage phase inverterpSource electrode.
5. input stage esd protection circuit according to claim 3 is it is characterised in that described transmission gate module includes PMOS
Transistor Mpt, nmos pass transistor Mnta, nmos pass transistor Mnt；
Described PMOS transistor Mpt, nmos pass transistor MntaGrid all by described overvoltage detectable signal ESD drive, described
Nmos pass transistor MntGrid by described reverse overvoltage detectable signal ESDX drive；Described PMOS transistor MptSource electrode, institute
State nmos pass transistor MntDrain electrode be all connected with described pressure welding point；Described PMOS transistor MptDrain electrode, described nmos pass transistor Mnt
Source electrode, described nmos pass transistor MntaDrain electrode be all connected with the input of described input stage phase inverter；Described nmos pass transistor
MntaSource ground.
6. input stage esd protection circuit according to claim 3 it is characterised in that described phase inverter INV1, INV2,
INV3, INV4, INV5 are CMOS inverter.
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| CN201410461667.1A CN104283201B (en) | 2014-09-11 | 2014-09-11 | Input stage esd protection circuit |
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| CN201410461667.1A CN104283201B (en) | 2014-09-11 | 2014-09-11 | Input stage esd protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
| US10861845B2 (en) * | 2016-12-06 | 2020-12-08 | Analog Devices, Inc. | Active interface resistance modulation switch |
| CN107579064B (en) * | 2017-08-31 | 2024-03-26 | 广东工业大学 | Stacked electrostatic discharge protection circuit |
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