CN103997383A - Method and device for improving IRIG-B time code decoding precision - Google Patents
Method and device for improving IRIG-B time code decoding precision Download PDFInfo
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- CN103997383A CN103997383A CN201410209192.7A CN201410209192A CN103997383A CN 103997383 A CN103997383 A CN 103997383A CN 201410209192 A CN201410209192 A CN 201410209192A CN 103997383 A CN103997383 A CN 103997383A
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Abstract
The invention belongs to the technical field of data processing and data timing systems, and provides a method and device for improving IRIG-B time code decoding precision. The method comprises the steps that the average clock number of the clock numbers between N adjacent pulses per second is obtained through a counter, and the pulses per second acquire pulse signals with the time interval as one second through a system clock; the standard clock number is acquired according to the average clock number and the preset clock number; the standard clock number and the average clock number are compared, and the system clock is adjusted to count one more or one less clock number in the standard clock number. According to the method, the system precision is improved to the microsecond level, and the continuousness of the microsecond value is effectively kept in external 1PPS.
Description
Technical field
The invention belongs to data processing and data time dissemination system technical field, relate in particular to a kind of method and device of the IRIG-B of raising timing code decode precision.
Background technology
In distributed data acquisition system, often need to analyze the data that multiple equipment synchronizations gather, in system, often have many GPS receivers, because the system clock of GPS receiver and time decoder card is asynchronous, within 1 second time, have larger error, while producing local microsecond signal with the 1PPS signal of GPS receiver, can cause the saltus step of microsecond signal.
Summary of the invention
The embodiment of the present invention provides a kind of method and device of the IRIG-B of raising timing code decode precision, be intended to solve in existing distributed data acquisition system, because the system clock of GPS receiver and time decoder card is asynchronous, while producing local microsecond signal with the 1PPS signal of GPS receiver, can cause the problem of the saltus step of microsecond signal.
On the one hand, provide a kind of method of the IRIG-B of raising timing code decode precision, described method comprises:
Obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time;
According to described average clock number and default clock number, obtain standard time clock number;
Contrast described standard time clock number and described average clock number, adjust described system clock and in described standard time clock number, count or count more less a clock number.
On the other hand, provide a kind of device of the IRIG-B of raising timing code decode precision, described device comprises:
The first acquiring unit, for obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time;
Second acquisition unit, for according to described average clock number and default clock number, obtains standard time clock number;
Clock adjustment unit, for contrasting described standard time clock number and described average clock number, adjusts described system clock and in described standard time clock number, counts or count more less a clock number.
In the embodiment of the present invention, obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time; According to described average clock number and default clock number, obtain standard time clock number; Contrast described standard time clock number and described average clock number, adjust described system clock and in described standard time clock number, count or count more less a clock number, the present invention, makes system accuracy bring up to Microsecond grade, keeps the continuous of microsecond value simultaneously in the time that outside 1PPS is effective.
Brief description of the drawings
Fig. 1 is the realization flow figure of the method for the raising IRIG-B timing code decode precision that provides of the embodiment of the present invention one;
Fig. 2 is the concrete structure block diagram of the device of the raising IRIG-B timing code decode precision that provides of the embodiment of the present invention three.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
In embodiments of the present invention, obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time; According to described average clock number and default clock number, obtain standard time clock number; Contrast described standard time clock number and described average clock number, adjust described system clock and in described standard time clock number, count or count more less a clock number.
Below in conjunction with specific embodiment, realization of the present invention is described in detail:
Embodiment mono-
Fig. 1 shows the realization flow of the method for the raising IRIG-B timing code decode precision that the embodiment of the present invention one provides, and details are as follows:
In step S101, obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time.
In the present embodiment, described counter is specifically 16 or 20.Preferably, N is 8.Described pulse per second (PPS) refers to the umber of pulse of generation per second, is especially spaced apart the pulse signal of 1 second by system clock acquisition time, i.e. 1PPS, and described system clock size preferred value is 10M.Concrete, this step comprises following two steps:
S11. calculate the adjacent clock number between adjacent pulse per second (PPS) by counter;
Wherein, time decoder card obtains the 1PPS signal of outside input with 10M system clock, calculates the adjacent clock number between continuous 2 adjacent 1PPS with the counter of 16 or 20.
S12. calculate the adjacent clock number of a N continuous described adjacent clock number.
Wherein, time decoder card does and on average obtains it and be worth adjacent clock number A continuous 8 adjacent clock numbers.
In step S102, according to described average clock number and default clock number, obtain standard time clock number.
In the present embodiment, described default clock number is that system sets in advance clock number, is specially 1000000.Concrete, this step comprises following two steps:
S21. described average clock number and default clock number are subtracted each other to acquisition difference clock number;
Wherein, time decoder card subtracts each other adjacent clock number A and default clock number to obtain a difference clock number B.
S22. using the ratio of described average clock number and described difference clock number as standard time clock number.
Wherein, the ratio that described average clock is counted A and described difference clock number B by time decoder card is counted F as standard time clock.
In step S103, contrast described standard time clock number and described average clock number, adjust described system clock and in described standard time clock number, count or count more less a clock number.
In the present embodiment, concrete, if described standard time clock number is greater than described average clock number, time decoder card described system clock is counted less a clock number in described standard time clock number; If described standard time clock number is less than described average clock number, time decoder card is described system clock clock number of many meters in described standard time clock number, if described standard time clock number equals described average clock number, time decoder card described system clock calculates strictly according to the facts clock number in described standard time clock number.Wherein, if average clock is counted A, to be greater than 1000000 expression local clocks faster than the clock of GPS receiver, in every standard time clock is counted F clock, counts less a clock number; If average clock is counted A, to be less than 1000000 expression local clocks slower than the clock of GPS receiver, a clock number of many meters in every standard time clock is counted F clock.
The present embodiment, can reach the described standard time clock number of contrast and described average clock number, and the clock number of real-time regulating system clock in described standard time clock number, makes system accuracy bring up to Microsecond grade, keeps the continuous of microsecond value simultaneously in the time that outside 1PPS is effective.
Embodiment bis-
Fig. 2 shows the concrete structure block diagram of the device of the raising IRIG-B timing code decode precision that the embodiment of the present invention two provides, and for convenience of explanation, only shows the part relevant to the embodiment of the present invention.In the present embodiment, the device of this raising IRIG-B timing code decode precision comprises: the first acquiring unit 21, second acquisition unit 22 and clock adjustment unit 23.
Wherein, the first acquiring unit 21, for obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time;
Second acquisition unit 22, for according to described average clock number and default clock number, obtains standard time clock number;
Clock adjustment unit 23, for contrasting described standard time clock number and described average clock number, adjusts described system clock and in described standard time clock number, counts or count more less a clock number.
Further, described the first acquiring unit 21 is specifically for calculating the adjacent clock number between adjacent pulse per second (PPS) by counter; Calculate the average clock number of a N continuous described adjacent clock number.
Further, described second acquisition unit 22 is specifically for subtracting each other acquisition difference clock number by described average clock number and default clock number; Using the ratio of described average clock number and described difference clock number as standard time clock number.
Further, if described clock adjustment unit 23 is greater than described average clock number specifically for described standard time clock number, described system clock is counted less a clock number in described standard time clock number; If described standard time clock number is less than described average clock number, described system clock clock number of many meters in described standard time clock number.
The present embodiment, can reach the described standard time clock number of contrast and described average clock number, and the clock number of real-time regulating system clock in described standard time clock number, makes system accuracy bring up to Microsecond grade, keeps the continuous of microsecond value simultaneously in the time that outside 1PPS is effective.
Further, described N is 8.
The device of the raising IRIG-B timing code decode precision that the embodiment of the present invention provides can be applied in the embodiment of the method one of aforementioned correspondence, and details, referring to the description of above-described embodiment one, do not repeat them here.
It should be noted that in said system embodiment, included unit is just divided according to function logic, but is not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit also, just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step realizing in the various embodiments described above method is can carry out the hardware that instruction is relevant by program to complete, corresponding program can be stored in a computer read/write memory medium, described storage medium, as ROM/RAM, disk or CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a method that improves IRIG-B timing code decode precision, is characterized in that, described method comprises:
Obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time;
According to described average clock number and default clock number, obtain standard time clock number;
Contrast described standard time clock number and described average clock number, adjust described system clock and in described standard time clock number, count or count more less a clock number.
2. the method for claim 1, is characterized in that, the described average clock number that obtains clock number between N adjacent pulse per second (PPS) by counter is specially:
Calculate the adjacent clock number between adjacent pulse per second (PPS) by counter;
Calculate the average clock number of a N continuous described adjacent clock number.
3. the method for claim 1, is characterized in that, described according to described average clock number and default clock number, obtains standard time clock number and is specially:
Described average clock number and default clock number are subtracted each other to acquisition difference clock number;
Using the ratio of described average clock number and described difference clock number as standard time clock number.
4. the method as described in claim 1,2 or 3, is characterized in that, the described standard time clock number of described contrast and described average clock number are adjusted described system clock few meter or count a clock number more and be specially in described standard time clock number:
If described standard time clock number is greater than described average clock number, described system clock is counted less a clock number in described standard time clock number; If described standard time clock number is less than described average clock number, described system clock clock number of many meters in described standard time clock number.
5. the method for claim 1, is characterized in that, described N is 8.
6. a device that improves IRIG-B timing code decode precision, is characterized in that, described device comprises:
The first acquiring unit, for obtain the average clock number of clock number between N adjacent pulse per second (PPS) by counter, described pulse per second (PPS) is spaced apart the pulse signal of 1 second by system clock acquisition time;
Second acquisition unit, for according to described average clock number and default clock number, obtains standard time clock number;
Clock adjustment unit, for contrasting described standard time clock number and described average clock number, adjusts described system clock and in described standard time clock number, counts or count more less a clock number.
7. device as claimed in claim 6, is characterized in that, described the first acquiring unit is specifically for calculating the adjacent clock number between adjacent pulse per second (PPS) by counter; Calculate the average clock number of a N continuous described adjacent clock number.
8. device as claimed in claim 6, is characterized in that, described second acquisition unit is specifically for subtracting each other acquisition difference clock number by described average clock number and default clock number; Using the ratio of described average clock number and described difference clock number as standard time clock number.
9. the device as described in claim 6,7 or 8, is characterized in that, if described clock adjustment unit is greater than described average clock number specifically for described standard time clock number, described system clock is counted less a clock number in described standard time clock number; If described standard time clock number is less than described average clock number, described system clock clock number of many meters in described standard time clock number.
10. device as claimed in claim 6, is characterized in that, described N is 8.
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| CN201410209192.7A CN103997383A (en) | 2014-05-17 | 2014-05-17 | Method and device for improving IRIG-B time code decoding precision |
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| US20080031283A1 (en) * | 2006-08-07 | 2008-02-07 | Martin Curran-Gray | Time synchronization for network aware devices |
| WO2010000190A1 (en) * | 2008-06-30 | 2010-01-07 | 华为技术有限公司 | Calculating method, system and optical network apparatus for synchronous time of passitive optical network |
| US20110052206A1 (en) * | 2008-05-09 | 2011-03-03 | Huawei Technologies Co. Ltd. | Method, system and optical network device for synchronizing time of a passive optical network |
| CN102917284A (en) * | 2012-10-22 | 2013-02-06 | 杭州开鼎科技有限公司 | Precise clock synchronization method based on PON (Passive Optical Network) system |
| CN103152117A (en) * | 2012-09-14 | 2013-06-12 | 南京航空航天大学 | Embedded-type high-precision network time server system |
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2014
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080031283A1 (en) * | 2006-08-07 | 2008-02-07 | Martin Curran-Gray | Time synchronization for network aware devices |
| US20110052206A1 (en) * | 2008-05-09 | 2011-03-03 | Huawei Technologies Co. Ltd. | Method, system and optical network device for synchronizing time of a passive optical network |
| WO2010000190A1 (en) * | 2008-06-30 | 2010-01-07 | 华为技术有限公司 | Calculating method, system and optical network apparatus for synchronous time of passitive optical network |
| CN103152117A (en) * | 2012-09-14 | 2013-06-12 | 南京航空航天大学 | Embedded-type high-precision network time server system |
| CN102917284A (en) * | 2012-10-22 | 2013-02-06 | 杭州开鼎科技有限公司 | Precise clock synchronization method based on PON (Passive Optical Network) system |
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