CN103929203A - Full-parallel-input ring-shift-left QC-LDPC coder - Google Patents

Abstract

The invention provides a full-parallel-input ring-shift-left QC-LDPC coder. The coder comprises a generator polynomial lookup tables storing all circulant matrix generator polynomials in a generating matrix, a b-bit binary multipliers for carrying out scalar multiplication on information field and generated polynomial bits, b (a+1)-bit binary adders for carrying out module-2 addition on products and the contents of shifting registers and one b-bit shifting register for storing the sum of one-bit ring shift left. Finally, verification data are contained in the shifting register. The full-parallel-input ring-shift-left QC-LDPC coder has the advantages of being few in shifting register, small in power consumption, low in cost, high in working frequency, large in throughput and the like.

Description

The ring shift left QC-LDPC encoder of complete parallel input

Technical field

The present invention relates to field of channel coding, particularly the ring shift left QC-LDPC encoder of complete parallel input in a kind of communication system.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code is one of efficient channel coding technology, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.Generator matrix G and the check matrix H of QC-LDPC code are all the arrays being made up of circular matrix, have the feature of segmentation circulation, therefore be called as QC-LDPC code.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right; First of circular matrix is that terminal column circulation moves down the result of 1, and all the other each row are all that its previous column circulation moves down the result of 1.Therefore, circular matrix is characterized by its first trip or first completely.Conventionally, the first trip of circular matrix or first are called as its generator polynomial.

Communication system adopts the QC-LDPC code of system form conventionally, and the left-half of its generator matrix G is a unit matrix, and right half part is by a × c b × b rank circular matrix G _i,jthe array that (0≤i<a, a≤j<t, t=a+c) forms, as follows:

Wherein, I is b × b rank unit matrixs, the full null matrix in the 0th, b × b rank.Capable and the b row of the continuous b of G are called as respectively the capable and piece row of piece.From formula (1), G has the capable and t piece of a piece row.Make circular matrix G _i,jfirst trip g _i,jor first h _i,jit is its generator polynomial.

The corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s=(e ₀, e ₁..., e _{a × b-1}), that rear c piece row are corresponding is verification vector p=(d ₀, d ₁..., d _{c × b-1}).Taking b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1); Verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p _c-1).From v=sG, j-a section verification vector meets

p _j-a＝s ₀G _0,j+s ₁G _1,j+…+s _iG _i,j+…+s _a-1G _a-1,j (2)

Wherein, 0≤i<a, a≤j<t, t=a+c.Order generator polynomial h _i,jcirculation moves down the result of n position, wherein, and 0≤n≤b.So, P in formula (2) _j-ak bit check digit d _{(j-a) × b+k}can be expressed as

$d_{(j-a)\&times;b+k}=s_0{h}_{0,j}^{\&DownArrow;\left(k\right)}+s_1{h}_{1,j}^{\&DownArrow;\left(k\right)}+...+s_i{h}_{i,j}^{\&DownArrow;\left(k\right)}+...+s_{a-1}{h}_{a-1,j}^{\&DownArrow;\left(k\right)}---\left(3\right)$

Wherein, 0≤k<b.

At present, the QC-LDPC encoder of complete parallel input is based on a shift register adder (Shift-Register-Adder, SRA) circuit, as shown in Figure 1.Generator polynomial look-up table L ₀～L _a-1respectively 0th～a-1 piece of pre-stored generator matrix G capable after all generator polynomials in c piece row, information vector s=(e ₀, e ₁..., e _{a × b-1}) complete parallel this circuit of sending into.With to verification section p _j-a(a≤j<t) is encoded to example.In the time that the 0th clock cycle arrives, shift register R ₀～R _a-1respectively from generator polynomial look-up table L ₀～L _a-1load generator polynomial h _{0, j}～h _{a-1, j}, and respectively with message segment s ₀～s _a-1carry out vector and take advantage of, the mould of product 2 and be P _j-athe 0th bit check digit d _{(j-a) × b}.In the time that the 1st clock cycle arrives, shift register R ₀～R _a-11 of ring shift right respectively, content becomes respectively and respectively with message segment s ₀～s _a-1carry out vector and take advantage of, the mould of product 2 and be P _j-athe 1st bit check digit d _{(j-a) × b+1}.Above-mentionedly move to right-take advantage of-Jia process proceeds down.In the time that b-1 clock cycle arrives, shift register R ₀～R _a-11 of ring shift right respectively, content becomes respectively and respectively with message segment s ₀～s _a-1carry out vector and take advantage of, the mould of product 2 and be P _j-alast 1 bit check digit d _{(j-a) × b+b-1}.Use the complete parallel input coding device shown in Fig. 1, can within c × b clock cycle, export by turn whole verification vector p.This scheme needs a × b register, a × b two input and door and a × b two input XOR gate, also needs the generator polynomial of a c × b bit ROM storage circular matrix.

In communication system, the existing solution of the QC-LDPC encoder of complete parallel input has two shortcomings: the one, need a large amount of registers, and cause the power consumption of circuit large, cost is high; The 2nd, modulo 2 adder has a × b input, and the time delay of add operation is long, can cause the operating frequency of encoder low, throughput is little.

Summary of the invention

In communication system there is the shortcoming that power consumption is large, cost is high, operating frequency is low, throughput is little in the existing implementation of QC-LDPC encoder, for these technical problems, the invention provides a kind of complete parallel input coding device based on ring shift left.

As shown in Figure 2, in communication system, the ring shift left QC-LDPC encoder of complete parallel input is mainly made up of 4 parts: generator polynomial look-up table, b position binary multiplier, (a+1) position binary adder and shift register.Cataloged procedure divides 5 steps to complete: the 1st step, entirely parallel input message vector s; The 2nd step, zero clearing shift register R; The 3rd step, generator polynomial look-up table L ₀, L ₁..., L _a-1export respectively in generator matrix G j (a≤j<t) piece row the 0th, 1 ..., the generator polynomial bit that a-1 piece is capable, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁..., M _a-1with message segment s ₀, s ₁..., s _a-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _a-1product by b (a+1) position binary adder A ₀, A ₁..., A _b-1be added with the content of shift register R, (a+1) position binary adder A ₀, A ₁..., A _b-1and be recycled the result moving to left after 1 and deposit shift register R in; The 4th step, repeats the 3rd step b time, now, shift register R storage be verification section p _j-a; The 5th step, changes the value of j taking 1 as step-length increases progressively, and repeats 2nd～4 step c time, and that shift register R obtains successively is verification section p ₀, p ₁..., p _c-1, they have formed verification vector p=(p ₀, p ₁..., p _c-1).

Complete parallel input coding device provided by the invention is simple in structure, can, keeping, under the condition of coding rate, reducing register and time delay, reduce power consumption and cost, improves operating frequency and throughput.

Can be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Brief description of the drawings

Fig. 1 is the complete parallel input QC-LDPC encoder being made up of a shift register adder SRA circuit;

Fig. 2 is a kind of complete parallel input QC-LDPC encoder based on ring shift left.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that, protection scope of the present invention is made to more explicit defining.

Order with respectively generator polynomial g _i,jthe result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.

So, the i item on formula (2) equal sign the right is deployable is

$s_i{G}_{i,j}=e_{i\&times;b}{g}_{i,j}^{r\left(0\right)}+e_{i\&times;b+1}{g}_{i,j}^{r\left(1\right)}+...+e_{i\&times;b+b-1}{g}_{i,j}^{r(b-1)}---\left(4\right)$

Make generator polynomial g _i,j=(g _{i, j, 0}, g _{i, j, 1}..., g _{i, j, b-1}), G _i,jcan be considered the weighted sum of unit matrix ring shift right version,

G _i,j＝g _i,j,0I ^r(0)+g _i,j,1I ^r(1)+…+g _i,j,b-1I ^r(b-1) (5)

So, the i item on formula (2) equal sign the right is deployable is

$s_i{G}_{i,j}\begin{array}{c}=s_i(g_{i,j,0}{I}^{r\left(0\right)}+g_{i,j,1}{I}^{r\left(1\right)}+...+g_{i,j,b-1}{I}^{r(b-1)})\\ =g_{i,j,0}{s}_i{I}^{r\left(0\right)}+g_{i,j,1}{s}_i{I}^{r\left(1\right)}+...+g_{i,j,b-1}{s}_i{I}^{r(b-1)}\\ =g_{i,j,0}{s}_i^{r\left(0\right)}+g_{i,j,1}{s}_i^{r\left(1\right)}+...+g_{i,j,b-1}{s}_i^{r(b-1)}\end{array}---\left(6\right)$

Since by s _iring shift right n position is equivalent to by its ring shift left b-n position, formula (6) can be rewritten as so

$s_i{G}_{i,j}\begin{array}{c}=g_{i,j,0}{s}_i^{l\left(b\right)}+g_{i,j,1}{s}_i^{1(b-1)}+...+g_{i,j,b-1}{s}_{i,j}^{l\left(1\right)}\\ ={\left(g_{i,j,0}{s}_i\right)}^{l\left(b\right)}+{\left(g_{i,j,1}{s}_i\right)}^{l(b-1)}+...+{\left(g_{i,j,b-1}{s}_i\right)}^{l\left(1\right)}\\ ={(0+g_{i,j,0}{s}_i)}^{l\left(b\right)}+{\left(g_{i,j,1}{s}_i\right)}^{l(b-1)}+...+{\left(g_{i,j,b-1}{s}_i\right)}^{l\left(1\right)}\\ {({(0+g_{i,j,0}{s}_i)}^{l\left(1\right)}+g_{i,j,1}{s}_i)}^{l(b-1)}+...+{\left(g_{i,j,b-1}{s}_i\right)}^{l\left(1\right)}\\ ={(...{({(0+g_{i,j,0}{s}_i)}^{l\left(1\right)}+g_{i,j,1}{s}_i)}^{l\left(1\right)}+...+g_{i,j,b-1}{s}_i)}^{l\left(1\right)}\end{array}---\left(7\right)$

By formula (7) substitution formula (2), arrangement can obtain

$p_{j-a}={(...{({(0+\underset{i=0}{\overset{a-1}{\mathrm{\&Sigma;}}}{g}_{i,j,0}{s}_i)}^{l\left(1\right)}+\underset{i=0}{\overset{a-1}{\mathrm{\&Sigma;}}}{g}_{i,j,1}{s}_i)}^{l\left(1\right)}+...+\underset{i=0}{\overset{a-1}{\mathrm{\&Sigma;}}}{g}_{i,j,b-1}{s}_i)}^{l\left(1\right)}---\left(8\right)$

Formula (8) is the process of a take advantage of-Jia-move to left-store, can derive a kind of complete parallel input QC-LDPC encoder based on ring shift left.Fig. 2 is its functional block diagram, is made up of generator polynomial look-up table, b position binary multiplier, (a+1) position binary adder and four kinds of functional modules of shift register.Generator polynomial look-up table L ₀, L ₁..., L _a-1the generator matrix G the 0th that prestores respectively, 1 ..., all circular matrix generator polynomials after a-1 piece is capable in c piece row.Generator polynomial look-up table L ₀, L ₁..., L _a-1output generator polynomial bit respectively with message segment s ₀, s ₁..., s _a-1carry out scalar multiplication, this scalar multiplication is respectively by b position binary multiplier M ₀, M ₁..., M _a-1complete.B position binary multiplier M ₀, M ₁..., M _a-1product and the content of shift register R be added, this addition is by b (a+1) position binary adder A ₀, A ₁..., A _b-1complete.(a+1) position binary adder A ₀, A ₁..., A _b-1and be recycled the result moving to left after 1 and deposit shift register R in.

Generator polynomial look-up table L ₀, L ₁..., L _a-1circular matrix generator polynomial after storage QC-LDPC code generator matrix in c piece row.Generator polynomial look-up table L ₀～L _a-1store respectively 0th～a-1 piece of G capable after all generator polynomials in c piece row, for arbitrary row, store successively a, a+1 ..., t-1 piece is listed as corresponding generator polynomial.Generator polynomial look-up table L ₀～L _a-1the bit of serial output generator polynomial.

The invention provides a kind of complete parallel input QC-LDPC coding method based on ring shift left, be applicable to the QC-LDPC code in communication system, its coding step is described below:

The 1st step, entirely parallel input message vector s;

The 2nd step, zero clearing shift register R;

The 3rd step, generator polynomial look-up table L ₀, L ₁..., L _a-1export respectively in generator matrix G j (a≤j<t) piece row the 0th, 1 ..., the generator polynomial bit that a-1 piece is capable, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁..., M _a-1with message segment s ₀, s ₁..., s _a-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _a-1product by b (a+1) position binary adder A ₀, A ₁..., A _b-1be added with the content of shift register R, (a+1) position binary adder A ₀, A ₁..., A _b-1and be recycled the result moving to left after 1 and deposit shift register R in;

The 4th step, repeats the 3rd step b time, now, shift register R storage be verification section p _j-a;

The 5th step, changes the value of j taking 1 as step-length increases progressively, and repeats 2nd～4 step c time, and that shift register R obtains successively is verification section p ₀, p ₁..., p _c-1, they have formed verification vector p=(p ₀, p ₁..., p _c-1).

Be not difficult to find out from above step, whole cataloged procedure needs c × b clock cycle altogether, identical with the existing complete parallel input encode method based on a SRA circuit.

In communication system, the existing solution of QC-LDPC encoder needs a × b register, a × b two input and door and (a × b-1) individual two input XOR gate, and the present invention needs b register, a × b two input and door and b × a two input XOR gate.Two kinds of coding methods expend equal number with door, although the present invention than existing solution multiplex 1 two input XOR gate, the present invention has saved a large amount of registers, is only the 1/a of existing solution.

Existing solution needs 1 a × b position modulo 2 adder, and nodulo-2 addition has been averagely allocated to b (a+1) position modulo 2 adder by the present invention.Conventionally, (a+1) be far smaller than a × b.Visible, adder time delay of the present invention is much smaller than existing solution.

As fully visible, for the complete parallel input coding device of QC-LDPC code in communication system, compared with existing solution, the present invention has kept identical coding rate, save a large amount of registers, greatly shorten the time delay of logical circuit, there is the advantages such as power consumption is little, cost is low, operating frequency is high, throughput is large.

The above; it is only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited to this; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; the variation that can expect without creative work or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.

Claims (3)

1. a ring shift left QC-LDPC encoder for complete parallel input, the generator matrix G of QC-LDPC code is divided into the capable and t piece row of a piece, and it is by a × c b × b rank circular matrix G that rear c piece is listed as corresponding part generator matrix _i,jthe array forming, g _i,jcircular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, the corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s, and that rear c piece row are corresponding is verification vector p, taking b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1), verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p _c-1), it is characterized in that, described encoder comprises following parts:

Generator polynomial look-up table L ₀, L ₁..., L _a-1, the QC-LDPC code generator matrix G the 0th, 1 that prestores respectively ..., all circular matrix generator polynomials after a-1 piece is capable in c piece row;

B position binary multiplier M ₀, M ₁..., M _a-1, respectively to message segment s ₀, s ₁..., s _a-1with generator polynomial look-up table L ₀, L ₁..., L _a-1output bit carry out scalar multiplication;

(a+1) position binary adder A ₀, A ₁..., A _b-1, to b position binary multiplier M ₀, M ₁..., M _a-1the content of sum of products shift register R carry out mould 2 and add;

Shift register R, storage (a+1) position binary adder A ₀, A ₁..., A _b-1and be recycled the result that moves to left after 1 and final verification section p ₀, p ₁..., p _c-1.

2. the ring shift left QC-LDPC encoder of a kind of complete parallel input according to claim 1, is characterized in that described generator polynomial look-up table L ₀～L _a-1store respectively 0th～a-1 piece of G capable after all generator polynomials in c piece row, for arbitrary row, store successively a, a+1 ..., t-1 piece is listed as corresponding generator polynomial.Generator polynomial look-up table L ₀～L _a-1the bit of serial output generator polynomial.

3. a ring shift left QC-LDPC coding method for complete parallel input, the generator matrix G of QC-LDPC code is divided into the capable and t piece row of a piece, and it is by a × c b × b rank circular matrix G that rear c piece is listed as corresponding part generator matrix _i,jthe array forming, g _i,jcircular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, the corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s, and that rear c piece row are corresponding is verification vector p, taking b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1), verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p _c-1), it is characterized in that, described coding method comprises the following steps:

The 1st step, entirely parallel input message vector s;

The 2nd step, zero clearing shift register R;

The 3rd step, generator polynomial look-up table L ₀, L ₁..., L _a-1export respectively in generator matrix G j piece row the 0th, 1 ..., the generator polynomial bit that a-1 piece is capable, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁..., M _a-1with message segment s ₀, s ₁..., s _a-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _a-1product by b (a+1) position binary adder A ₀, A ₁..., A _b-1be added with the content of shift register R, (a+1) position binary adder A ₀, A ₁..., A _b-1and be recycled the result moving to left after 1 and deposit shift register R in, wherein, a≤j<t;

The 4th step, repeats the 3rd step b time, now, shift register R storage be verification section p _j-a;

The 5th step, changes the value of j taking 1 as step-length increases progressively, and repeats 2nd～4 step c time, and that shift register R obtains successively is verification section p ₀, p ₁..., p _c-1, they have formed verification vector p=(p ₀, p ₁..., p _c-1).