CN103684463A - FWNN (fuzzy wavelet neural network) based analog-digital conversion system of pipeline structure - Google Patents

Abstract

The invention relates to an FWNN (fuzzy wavelet neural network) based analog-digital conversion system of a pipeline structure. The system comprises an FWNN module, a data synthesis module, two high-speed low-bit AD (analog to digital) chip, a differential amplifier and a DA (digital to analog) chip. The two AD chips form a pipeline, an input analog signal is inputted to the FWNN module after being subjected to first-stage AD conversion to obtain data approaching to the input analog signal at a certain moment after that time, the data are subjected to DA conversion to obtain an analog signal, a difference between the analog signal and the input analog signal is subjected to high-gain amplification prior to secondary AD conversion, and the data subjected to twice AD conversion are processed by the data synthesis module to obtain high-accuracy AD conversion data corresponding to the input analog signal. The high-speed high-accuracy AD conversion system is realized through the two high-speed low-bit AD chips, and can be applied to analog signal conversion with requirements on high speed, high accuracy, large dynamic range and high signal to noise ratio.

Description

The A/D conversion system of the pipeline organization based on FWNN prediction network

Technical field

The present invention relates to a kind of A/D conversion system, can be used for the collection of simulant signal of high speed, great dynamic range, high s/n ratio.

Background technology

Fourier trasform spectroscopy (FTS) technology is a kind of spectral analysis technique that Michelson's interferometer is core of take, the feature of interference signal is that near signal zero optical path difference is very strong, near signal maximum optical path difference very a little less than, more than signal amplitude differs and can reach 100dB.

First Detection Techniques based on FTS become faint current signal interference light through opto-electronic conversion link, then carry out signal condition.Amplifying circuit comprises preposition amplification, and master is put with low-pass filter circuit and has gain adjustable function, is mainly in order to realize, the signal of telecommunication of detector output to be amplified and filter away high frequency noise, to adapt to the sampling dynamic range of ADC.According to the characteristic of signal, for obtaining very high signal to noise ratio, conventionally need reach by high speed over-sampling and digital filtering technique, thus the speed of data acquisition system and precision have been proposed to very high requirement, if sample rate is that 80MHz, number of significant digit are greater than 18 etc.

In FTS technology, dynamic range of signals is very large, signal to noise ratio requires very high.Be subject to the restriction of modulus conversion chip development level, still do not have monolithic ADC can meet this demand, be not more applied to the chip product on aerospace level equipment, limited to a certain extent the detection accuracy of FTS technology.

Summary of the invention

Technology of the present invention is dealt with problems and is: the present invention overcomes the deficiencies in the prior art, a kind of high precision analogue converting system of the pipeline organization based on FWNN prediction network is provided, can under the prerequisite that guarantees high-speed sampling, improve the number of significant digit of AD system, and then improve the conversion accuracy of system.

Technical solution of the present invention is: the A/D conversion system of the pipeline organization based on FWNN prediction network, comprise two AD modular converters, a FWNN prediction network, a DA modular converter, a time delay module, an error amplifier and a data synthesis module, wherein:

The one AD modular converter: bit wide is M1, carries out obtaining digital signal D1 and delivering to FWNN prediction network after digital sample to the analog signal A1 of outside input;

Time delay module: the analog signal A1 of outside input is carried out obtaining time delay analog signal A2 after time delay that duration is T and delivers to the input in the same way of error amplifier; Described duration T is analog-to-digital conversion time, the FWNN prediction predicted time of network and the digital-to-analogue conversion time sum of DA modular converter of an AD modular converter;

FWNN predicts network: utilize digital signal D1, adopt BFGS training algorithm to build FWNN forecast model, and utilize the prediction of FWNN forecast model obtain the digital signal D2 of analog signal A1 correspondence after carrying out the time delay that duration is T and deliver to DA modular converter; Utilize error digital signal Diff_D to proofread and correct the parameter of the FWNN forecast model building, improve the precision of prediction of FWNN forecast model;

DA modular converter: digital signal D2 is carried out to the reverse input end that digital-to-analogue conversion obtains prognosis modelling signal A3 and delivers to error amplifier;

Error amplifier: time delay analog signal A2 and prognosis modelling signal A3 are carried out to error amplification, multiplication factor is G, error simulation signal Diff_A after being amplified also delivers to the 2nd AD modular converter, G<1/ Δ wherein, and Δ is the relative error of FWNN prediction network;

The 2nd AD modular converter: bit wide is M2, carries out analog-to-digital conversion to the error simulation signal Diff_A after amplifying and obtains error digital signal Diff_D and deliver to FWNN prediction network and data synthesis module, wherein N>M1 >=M2 simultaneously;

Data synthesis module: digital signal D2 and error digital signal Diff_D are carried out to signal synthetic, the digital signal that obtains M3 position is exported to outside, wherein M3=M1+[log ₂(G)]-1, wherein symbol [X] represents to get the maximum integer that is not more than X.

The present invention's advantage is compared with prior art: the present invention forms a two-level pipeline structure by the AD chip of two high speed low-bit widths, by FWNN, predict that mixed-media network modules mixed-media predicts the input signal after T constantly, and then minimize the error between input signal and prediction signal, thereby by the differential amplifier of high-gain, after error is amplified, carry out secondary AD conversion, finally the data of two-stage AD conversion are sent into data synthesis module, obtain high-precision AD translation data.The present invention, in conjunction with the speed advantage of monolithic AD chip and the forecast function of FWNN network, adopts the AD transformational structure of two-level pipeline, has formed AD converting system, has realized the analog-digital conversion function of high-speed, high precision.The conversion speed of the AD converting system that the present invention forms depends on the speed of monolithic AD and DA chip, can reach 80MHz～120MHz, system bits is wider than 20, can meet the collection field of the analog signal of many high speeds, great dynamic range, high s/n ratio, especially the data acquisition of the interference signal based on FTS technology.

Accompanying drawing explanation

Fig. 1 is the theory of constitution block diagram of system of the present invention;

Fig. 2 is FWNN prediction mixed-media network modules mixed-media structure chart of the present invention.

Embodiment

As shown in Figure 1, theory diagram for A/D conversion system of the present invention, mainly comprises: a secondary flowing water AD transformational structure, a FWNN prediction mixed-media network modules mixed-media, a DA conversion links, a delay unit, a high-gain error amplifier and a data synthesis module.

The main flow process of digital-to-analogue conversion is: the analog signal of input produces the digital signal D1 that figure place is M1 after first order ADC, digital signal D1 is after FWNN prediction mixed-media network modules mixed-media, produce the digital signal D2 in the time delay T moment after prediction, digital signal D2 is the analog signal A3 constantly of the time delay T after the DAC of N position generation prediction again.Now, after the time delay that is T through duration, analog signal becomes A2, it is the high-gain error amplifier of G that analog signal A2 and analog signal A3 are sent into gain, error simulation signal Diff_A after being amplified, error simulation signal after this is amplified is sent into second level ADC and is carried out AD conversion for the second time, produces error digital signal Diff_D.Error digital signal Diff_D and digital signal D2 all send into data synthesis module, and producing final bit wide is the AD translation data of M3.Wherein, Diff_D sends into and when train for model learning on FWNN prediction mixed-media network modules mixed-media Yi road, determines network parameter.

Below each part is described in detail.

I and II assembly line A/D transformational structure

The secondary streams elementary stream AD transformational structure of two ADC compositions is agent structures of converting system of the present invention.Because the processing speed of FPGA or DSP is higher, therefore the conversion speed of this system depends primarily on the conversion speed of two ADC and a DAC, when choosing this three chips, need to follow the principle of speeds match, though its speeds match of three get up, to improve the efficiency of conversion speed.Conventionally, the switching rate of this system can reach 80MHz～120MHz, but in the application lower than this conversion speed, will more easily realize.

When selecting AD, DA chip bit wide, should follow following principle: 1. M1 is as far as possible large, and M1>=M2, because first ADC is main conversion chip, meet under the prerequisite of conversion speed requirement the ADC of the maximum bit wide that selection can obtain; 2. second level ADC is used for the AD conversion links of the first order to revise, and further improves conversion accuracy, and the selection of M2 will be determined in conjunction with the multiple G of error amplifier, and M2 can be taken as [log conventionally ₂(G)]+1, wherein symbol [X] represents to get the maximum integer that is not more than X.Excessive M2 does not have meaning to improving system accuracy; 3. the selection principle of DAC bit wide is generally N=M1+1, and this is because when D1 is predicted, may derive 1, the data bit width of D1 is broadened, but generally, increase by 1 and can meet required precision.

Two, high-gain error amplifier

High-gain error amplifier can consist of differential amplifier, instrumentation amplifier or subtracter, mainly realizes the error of A2 and A3 signal and amplifies.Its multiplication factor G has determined the precision of converting system, this value is higher, system conversion accuracy is higher, but the selection of G will be chosen in conjunction with the performance of prediction mixed-media network modules mixed-media, do not make error signal be amplified to distortion or saturation condition, therefore G<1/ Δ (Δ, for the relative error of prediction mixed-media network modules mixed-media, can be less than 1% conventionally).Conventionally, according to the performance of prediction mixed-media network modules mixed-media, the conservative G=32 that chooses.

Three, FWNN prediction network

FWNN predicts network, be Fuzzy Wavelet Network (Fuzzy Wavelet Neural Network), its model structure comprises input layer, obscuring layer, fuzzy rule layer, normalization layer, 6 layers of rule weighing output layer and final output layers etc., the detailed content document Fuzzy Wavelet Neural Network Models for Prediction and Identification of Dynamical Systems that sees reference, Sevcan Yilmaz and Yusuf Oysal, IEEE Transactions on Neural Networks, Vol.21, No.10, October2010.

In the present invention:

1, model structure: be illustrated in figure 2 FWNN prediction network model structure chart of the present invention, adopt MISO(multi input single output) structure.According to the complexity of input signal, in input layer, adopt 4 neuron (sampled points, the bit wide of each sampled point is M1) input network configuration, in obscuring layer, each neuron input is to there being 2 memberships (representing with A in figure), every kind of possible combination of membership forms 16 fuzzy rules altogether, fuzzy rule output after normalization with each neuron input of input layer input as Wavelet-Weighted output layer, after 16 output summations of last Wavelet-Weighted output layer as the output of FWNN network.

When selecting more neuron input and more membership, can increase the precision of prediction, but also can make the complexity of algorithm and forecasting efficiency reduce simultaneously.

2, learning training method: adopt BFGS algorithm to train sample sequence, adopt the non-accurate linear search of Wolfe to find iteration step length, after repeatedly training, when worst error meets the demands, deconditioning.The parameter finally training being obtained is fixed in network, then actual signal is predicted.

3, model parameter: in the present invention, model parameter comprises the weights coefficient ω of Center Parameter μ, scale parameter σ in Gauss member function (the expression mode of membership) and the translation parameters b in wavelet function, flexible parameter c and fuzzy rule output.With q, represent these unknown parameters vector, i.e. q=[μ, σ, b, c, ω].In the present invention, network configuration has 4 inputs, and each is inputted there being 2 memberships, so μ and σ have respectively 8.The number of the corresponding fuzzy rule of each x equals 16, therefore [b, c, ω] has respectively 64, the total number of unknown network parameter is 208.

4, initiation parameter is selected: in the present invention, initiation parameter is selected to comprise:

it is 0 to 1 random vector; Initialization training iterative parameter, the coefficient matrix H of the Wolfe direction of search ₀[i] [j]=1, i=1:208, j=1:208; The bound parameter in Wolfe search initialization interval is respectively c ₁=0.0001, c ₂=0.5.

5, learning training signal type: the difference according to input analog signal types, should adopt different sample signals targetedly to carry out learning training.In the present invention, for the characteristic of interference signal, adopt class sinc signal to carry out learning training, learning training number of times is less than 300 times, and predicated error can be less than 1%.Prediction effect to the stronger sine wave of other regularity, triangular wave etc. is better, but it is poor that square wave etc. is had to the prediction effect of very strong mutability signal.The number of times of training requires to be as the criterion to meet worst error, conventionally in hundreds of underrange.

Four, data synthesis module

Data synthesis module is for synthesizing road output, i.e. a final digital output signal y by the result Diff_D of the digital signal of FWNN prediction and second level ADC conversion.According to the theory diagram of Fig. 1, input analog signal

$A_2=A_3+\frac{\mathrm{Diff}\_A}{G}$

And then,

$A_2=k_1\&CenterDot;D_2+\frac{\mathrm{Diff}\_D}{G\&CenterDot;k_2}$

Wherein, K ₁for the conversion coefficient of DAC chip from digital signal to analog signal, unit is: V/DN value, K ₂for the conversion coefficient of second level ADC from analog signal to digital signal, unit is: DN value/V.K ₁, K ₂, G can obtain coarse value by handbook and the design load of DAC, ADC, also can obtain its exact value by calibration.The conversion coefficient of second level ADC of take is benchmark, has

A ₂=y/k ₂

Thereby, have

$y=k_1\&CenterDot;k_2\&CenterDot;D_2+\frac{\mathrm{Diff}\_D}{G}$

Conventionally, K ₁k ₂the long-pending precision that approaches 1, y depends primarily on G value, and G is larger, and conversion accuracy is higher.The number of significant digit of D2 is M1, and the equivalent figure place of G is log ₂(G) (round numerical value downwards).In theory, the number of significant digit of y is M1+[log ₂(G)], but consider the synthetic certain error that exists of data, the number of significant digit of final y can reach M3=M1+[log conventionally ₂(G)]-1.

The content not being described in detail in specification of the present invention belongs to those skilled in the art's known technology.

Claims (1)

1. based on FWNN, predict the A/D conversion system of the pipeline organization of network, it is characterized in that: comprise two AD modular converters, a FWNN prediction network, a DA modular converter, a time delay module, an error amplifier and a data synthesis module, wherein:

The one AD modular converter: bit wide is M1, carries out obtaining digital signal D1 and delivering to FWNN prediction network after digital sample to the analog signal A1 of outside input;

Time delay module: the analog signal A1 of outside input is carried out obtaining time delay analog signal A2 after time delay that duration is T and delivers to the input in the same way of error amplifier; Described duration T is analog-to-digital conversion time, the FWNN prediction predicted time of network and the digital-to-analogue conversion time sum of DA modular converter of an AD modular converter;

FWNN predicts network: utilize digital signal D1, adopt BFGS training algorithm to build FWNN forecast model, and utilize the prediction of FWNN forecast model obtain the digital signal D2 of analog signal A1 correspondence after carrying out the time delay that duration is T and deliver to DA modular converter; Utilize error digital signal Diff_D to proofread and correct the parameter of the FWNN forecast model building, improve the precision of prediction of FWNN forecast model;

DA modular converter: digital signal D2 is carried out to the reverse input end that digital-to-analogue conversion obtains prognosis modelling signal A3 and delivers to error amplifier;

Error amplifier: time delay analog signal A2 and prognosis modelling signal A3 are carried out to error amplification, multiplication factor is G, error simulation signal Diff_A after being amplified also delivers to the 2nd AD modular converter, G<1/ Δ wherein, and Δ is the relative error of FWNN prediction network;

The 2nd AD modular converter: bit wide is M2, carries out analog-to-digital conversion to the error simulation signal Diff_A after amplifying and obtains error digital signal Diff_D and deliver to FWNN prediction network and data synthesis module, wherein N>M1 >=M2 simultaneously;

Data synthesis module: digital signal D2 and error digital signal Diff_D are carried out to signal synthetic, the digital signal that obtains M3 position is exported to outside, wherein M3=M1+[log ₂(G)]-1, wherein symbol [X] represents to get the maximum integer that is not more than X.

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