CN103490782A - Capacitance type comparator averaging circuit - Google Patents
Capacitance type comparator averaging circuit Download PDFInfo
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- CN103490782A CN103490782A CN201310381503.3A CN201310381503A CN103490782A CN 103490782 A CN103490782 A CN 103490782A CN 201310381503 A CN201310381503 A CN 201310381503A CN 103490782 A CN103490782 A CN 103490782A
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Abstract
The invention discloses a capacitance type comparator averaging circuit. The capacitance type comparator averaging circuit is composed of a first comparator, a second comparator and a third comparator, wherein the first-level p end output of the second comparator is connected with the second-level p end input of the first comparator and the second-level p end input of the third comparator, the second-level p end input of the second comparator is connected with the first-level p end output of the first comparator and the first-level p end output of the third comparator, the first-level n end output of the second comparator is connected with the second-level n end input of the first comparator and the second-level n end input of the third comparator, and the second-level n end input of the second comparator is connected with the first-level n end output of the first comparator and the first-level n end output of the third comparator. According to the capacitance type comparator averaging circuit, averaging is achieved by means of capacitance, interference to the DC bias of the amplification stage of each comparator is avoided, averaging strength and distribution can be achieved through adjustment of the capacitance of the comparators on the same layer, the capacitance connected to an upper layer and the capacitance connected to a lower layer, and then influence of thermal noise is reduced on the whole.
Description
Technical field
The present invention relates to a kind of average circuit, relate in particular to a kind of comparator capacitor averaging circuit.
Background technology
Analog to digital conversion circuit refers to the circuit that analog signal is compared and quantizes according to reference voltage, and wherein, core devices is comparator circuit.
Described comparator circuit refers to the circuit that applied signal voltage and reference voltage are compared, and is output as height, shows that input signal is higher than reference voltage.Vice versa.Main consideration index is the input direct-current drift, input noise, bandwidth etc.The input direct-current drift, input noise has determined the precision quantized, and has determined analog-to-digital figure place together with reference voltage, as 8 analog-to-digital conversion.The bandwidth of comparator has determined analog-to-digital speed.Described input direct-current drift is mainly to refer to the threshold voltage of input in the CMOS device, due to various physical factors, refers to the threshold voltage difference of input in two different CMOS devices that cause.Certainly, in triode and other techniques, not equal other factors of current amplification factor also cause the input direct-current drift.And input noise is to be mainly thermal noise and the flicker noise of device at CMOS device middle finger.
In order to reduce the impact of thermal noise and input direct-current drift, people have designed the flash analog-to-digital conversion, its inner comparator circuit as shown in Figure 1, form comparator array by a plurality of comparators, in order to reduce input direct-current drift and the input noise of afterbody latch circuit, the main multilevel hierarchy that adopts, under the condition that guarantees bandwidth, progressively amplify input differential signal; In Fig. 1, adopt two-stage pre1 and pre2 to amplify, but amplifying circuit itself just have own noise and input direct-current drift; In order to reduce the input direct-current drift of amplifying circuit, the general employing exported auto zero, or the input auto zero; The error of output auto zero and the gain switching of amplifying circuit are smaller, generally in high-speed comparator, adopts often, or the amplifying circuit gain that the input auto zero need to be large, generally in the low speed comparator, use often.
When auto zero, the own input direct-current drift through amplifying of output will be stored in electric capacity; When normal operation, the error that the voltage difference at electric capacity two ends will be brought with the input direct-current drift automatically deducts, thereby realizes the effect without the amplification of input direct-current drift.
In Fig. 1, amplifying stage pre1 has been adopted to this technology, can certainly adopt this technology to pre2.But adopt this technology can affect bandwidth and comparator area, whether adopt, adopt how many levels, by the requirement decision of design.
The flicker noise of above-mentioned technology to the low speed of amplifier, play the effect that is similar to the input direct-current drift equally.But, for the thermal noise of high frequency, particularly the noise of sample frequency odd-multiple, often can not play inhibition, even plays amplification.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of and can reduce the thermal noise impact and realize the comparator capacitor averaging circuit without the input direct-current drift.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions: a kind of comparator capacitor averaging circuit, by the first comparator, the second comparator and the 3rd comparator form, each comparator is by the first amplifying stage Pre1, the second amplifying stage Pre2 and latch circuit Latch are in series, be provided with the output of first order p end and the output of first order n end on described the first amplifying stage Pre1, the output of described first order p end and the output of first order n end respectively be arranged on the second amplifying stage Pre2 on the input of second level p end and second level n hold to input and be connected, and respectively be in series with an electric capacity between the output of first order p end and the input of second level p end and the output of first order n end and the input of second level n end, first order p end output on described the second comparator is connected with the second level p end input on the 3rd comparator with the first comparator respectively, second level p end input on the second comparator is connected with the first order p end output on the 3rd comparator with the first comparator respectively, first order n end output on the second comparator is connected with the second level n end input on the 3rd comparator with the first comparator respectively, and on the second comparator, the input of second level n end is connected with the first order n end output on the 3rd comparator with the first comparator respectively.
Preferably, between first order p end output on described the second comparator and the second level p end input on the first comparator and the 3rd comparator, and second between second level p end input on comparator exports with the first order p end on the first comparator and the 3rd comparator, and second between second level n end input on first order n end output on comparator and the first comparator and the 3rd comparator, and the input of the second comparator second level n end and first order n on the first comparator and the 3rd comparator hold between exporting and respectively are in series with an electric capacity.
Compared with prior art, usefulness of the present invention is: this comparator capacitor averaging circuit adopts electric capacity average, can not produce and disturb the direct current biasing of the amplifying stage of comparator, average intensity and distribution, can realize by the size of regulating the electric capacity on this layer of comparator and receiving respectively the electric capacity of upper strata, lower floor, reduce on the whole the impact of thermal noise.
the accompanying drawing explanation:
Below in conjunction with accompanying drawing, the present invention is further described.
Fig. 1 is the comparator circuit structural representation of existing flash analog to digital conversion circuit;
Fig. 2 is this comparator capacitor averaging electrical block diagram.
In figure: 1, the first comparator; 2, the second comparator; 3, the 3rd comparator; 11,21,31, first order p holds output; 12,22,32, second level p holds input; 13,23,33, first order n holds output; 14,24,34, second level n holds input.
embodiment:
Below in conjunction with the drawings and the specific embodiments, describe the present invention:
A kind of comparator capacitor averaging circuit shown in Fig. 2, by the first comparator 1, the second comparator 2 and the 3rd comparator 3 form, each comparator is by the first amplifying stage Pre1, the second amplifying stage Pre2 and latch circuit Latch are in series, be provided with the output of first order p end and the output of first order n end on described the first amplifying stage Pre1, the output of described first order p end and the output of first order n end respectively be arranged on the second amplifying stage Pre2 on the input of second level p end and second level n hold to input and be connected, and respectively be in series with an electric capacity between the output of first order p end and the input of second level p end and the output of first order n end and the input of second level n end, it is characterized in that: first order p on described the second comparator 2 end output 21 respectively with the first comparator 1 and the 3rd comparator 3 on second level p end input 12, 32 connect, second level p on the second comparator 2 end input 22 respectively with the first comparator 1 and the 3rd comparator 3 on first order p end output 11, 31 connect, first order n end output 23 on the second comparator 2 is connected with the second level n end input 14,34 on the 3rd comparator 3 with the first comparator 1 respectively, and on the second comparator 2, second level n end input 24 is connected with the first order n end output 13,33 on the 3rd comparator 3 with the first comparator 1 respectively.
First order p end output the 21 and first comparator 1 on described the second comparator 2 and the second level p end input 12 on the 3rd comparator 3, between 32, and second second level p end input the 22 and first comparator 1 on comparator 2 and the first order p end on the 3rd comparator 3 export 11, between 31, and second first order n end output the 23 and first comparator 1 on comparator 2 and the second level n end on the 3rd comparator 3 input 14, between 34, and second first order n end on comparator 2 second level n end input the 24 and first comparators 1 and the 3rd comparator 3 export 13, respectively be in series with an electric capacity between 33.
This comparator capacitor averaging circuit adopts electric capacity average, can not produce and disturb the direct current biasing of the amplifying stage of comparator, average intensity and distribution, can realize by the size of regulating the electric capacity on this layer of comparator and receiving respectively the electric capacity of upper strata, lower floor, reduce on the whole the impact of thermal noise.
It is emphasized that: above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, any simple modification, equivalent variations and modification that every foundation technical spirit of the present invention is done above embodiment, all still belong in the scope of technical solution of the present invention.
Claims (2)
1. a comparator capacitor averaging circuit, by the first comparator (1), the second comparator (2) and the 3rd comparator (3) form, each comparator is by the first amplifying stage (Pre1), the second amplifying stage (Pre2) and latch circuit (Latch) are in series, be provided with the output of first order p end and the output of first order n end on described the first amplifying stage (Pre1), the output of described first order p end and the output of first order n end respectively be arranged on the second amplifying stage (Pre2) on the input of second level p end and second level n hold to input and be connected, and respectively be in series with an electric capacity between the output of first order p end and the input of second level p end and the output of first order n end and the input of second level n end, it is characterized in that: first order p on described the second comparator (2) end output (21) respectively with the first comparator (1) and the 3rd comparator (3) on second level p end input (12, 32) connect, second level p on the second comparator (2) end input (22) respectively with the first comparator (1) and the 3rd comparator (3) on first order p end export (11, 31) connect, first order n end output (23) on the second comparator (2) is connected with the second level n end input (14,34) on the 3rd comparator (3) with the first comparator (1) respectively, and the upper second level n end input of the second comparator (2) (24) is connected with the first order n end output (13,33) on the 3rd comparator (3) with the first comparator (1) respectively.
2. comparator capacitor averaging circuit according to claim 1, it is characterized in that, first order p end output (21) on described the second comparator (2) inputs (12 with the second level p end on the first comparator (1) and the 3rd comparator (3), 32) between, and second second level p end input (22) on comparator (2) export (11 with the first order p end on the first comparator (1) and the 3rd comparator (3), 31) between, and second first order n end output (23) on comparator (2) input (14 with the second level n end on the first comparator (1) and the 3rd comparator (3), 34) between, and second comparator (2) second level n end input (24) export (13 with the first order n end on the first comparator (1) and the 3rd comparator (3), 33) respectively be in series with an electric capacity between.
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| CN201310381503.3A CN103490782B (en) | 2013-08-29 | 2013-08-29 | Capacitance type comparator averaging circuit |
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| CN201310381503.3A CN103490782B (en) | 2013-08-29 | 2013-08-29 | Capacitance type comparator averaging circuit |
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| CN103490782A true CN103490782A (en) | 2014-01-01 |
| CN103490782B CN103490782B (en) | 2017-01-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10203807B2 (en) | 2017-03-20 | 2019-02-12 | Microsoft Technology Licensing, Llc | Method for sampling output from a grid based digitizer sensor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617093A (en) * | 1994-09-30 | 1997-04-01 | Imp, Inc. | Switched capacitor analog circuits with low input capacitance |
| CN1734385A (en) * | 2004-07-26 | 2006-02-15 | 英特赛尔美国股份有限公司 | Current averaging circuit for a PWM power converter |
| CN102931992A (en) * | 2011-08-11 | 2013-02-13 | 原相科技股份有限公司 | Systems, devices and methods for capacitor mismatch error averaging in pipeline analog-to-digital converters |
| CN203406857U (en) * | 2013-08-29 | 2014-01-22 | 苏州苏尔达信息科技有限公司 | Comparator capacitance average circuit |
-
2013
- 2013-08-29 CN CN201310381503.3A patent/CN103490782B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617093A (en) * | 1994-09-30 | 1997-04-01 | Imp, Inc. | Switched capacitor analog circuits with low input capacitance |
| CN1734385A (en) * | 2004-07-26 | 2006-02-15 | 英特赛尔美国股份有限公司 | Current averaging circuit for a PWM power converter |
| CN102931992A (en) * | 2011-08-11 | 2013-02-13 | 原相科技股份有限公司 | Systems, devices and methods for capacitor mismatch error averaging in pipeline analog-to-digital converters |
| CN203406857U (en) * | 2013-08-29 | 2014-01-22 | 苏州苏尔达信息科技有限公司 | Comparator capacitance average circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10203807B2 (en) | 2017-03-20 | 2019-02-12 | Microsoft Technology Licensing, Llc | Method for sampling output from a grid based digitizer sensor |
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