CN103259405A - Direct-current-to-direct-current (DCDC) converter - Google Patents
Direct-current-to-direct-current (DCDC) converter Download PDFInfo
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- CN103259405A CN103259405A CN2012100386807A CN201210038680A CN103259405A CN 103259405 A CN103259405 A CN 103259405A CN 2012100386807 A CN2012100386807 A CN 2012100386807A CN 201210038680 A CN201210038680 A CN 201210038680A CN 103259405 A CN103259405 A CN 103259405A
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Abstract
The invention provides a direct-current-to-direct-current (DCDC) converter which can restrain overshoot voltage generated when the DCDC converter is converted from a current-limiting mode to a normal working mode. The DCDC converter comprises a sampling feedback unit, a differential input grade amplification unit and an output grade amplification unit, wherein one end of the sampling feedback unit outputs output voltage of the DCDC converter, the other end of the sampling feedback unit is connected with the ground, a first input end of the differential input grade amplification unit is connected in the sampling feedback unit to sample the output voltage of the DCDC converter, a second input end of the differential input grade amplification unit inputs standard voltage, the differential input grade amplification unit conducts comparison and amplification on a difference of sampling voltage of the output voltage of the DCDC converter and the standard voltage of the DCDC converter, amplification voltage signals of the difference are output, the output grade amplification unit is provided with a first switching circuit and a second switching circuit, the first switching circuit and the second switching circuit are connected when overcurrent occurs in the DCDC converter, and the first switching circuit and the second switching circuit are disconnected when the DCDC converter normally works, namely no overcurrent occurs.
Description
Technical field
The present invention relates to a kind of DCDC transducer, relate to a kind of DCDC transducer that can suppress its overshoot voltage that when current-limit mode enters normal mode of operation, occurs more specifically.
Background technology
The DCDC transducer refers to utilize the characteristic of the energy storage of electric capacity, inductance, and (MOSFET etc.) carry out the action of HF switch by gate-controlled switch, and with the electrical power storage of input in electric capacity (sense), discharge to load by electric capacity again, energy is provided.The power of its output or the ability of voltage and duty ratio (by the ratio in cycle of switch conduction time and whole switch) are relevant.The DCDC transducer can be used for boosting and step-down.
Fig. 1 is that the summary of DCDC transducer of the prior art constitutes block diagram.Fig. 2 is the relevant circuit structure diagram in the DCDC transducer of the prior art.In the circuit of DCDC transducer shown in Figure 2, VCC represents the power supply of the portions of electronics element of this DCDC transducer, simultaneously also as the input voltage of this DCDC transducer, VOUT represents the output voltage of DCDC transducer, and this DCDC transducer 1 carries out direct current, and to change to the basic principle of direct current as follows:
Block diagram 11 for example is the resistor voltage divider network with two series resistance R1, R2 for the sampling feedback unit, an end ground connection of this sampling feedback unit 11, the output voltage VO UT of another termination DCDC transducer 1.Block diagram 12 is that difference amplifies the input stage unit, has image current to pipe P1, P2, and the difference input is to pipe N1, N2, and as the metal-oxide-semiconductor N3 of constant-current source.Wherein, the source electrode of P1 and P2 is connected and inserts power supply VCC, their grid is connected, the drain and gate of P1 links to each other, and be connected with the drain electrode of N1, the grid of N1 is connected with the R2 common ground with R1, receive the sampling feedback voltage Vfb of VOUT, the source electrode of N2 is connected with the source electrode of N1, N2 grid input reference voltage Vref, and the drain electrode of N2 is connected with the drain electrode of P2, and this tie point amplifies the output of input stage unit 12 for this difference, the grid input offset voltage Vbias of N3, the drain electrode of N3 is connected with the source electrode of N1, the source ground of N3.This difference is amplified input stage unit 12 relatively and is amplified poor between Vfb and Vref, and output voltage signal Verror1.Block diagram 13 is the output stage amplifying unit, comprises P3 and N4.Wherein, the source electrode of P3 inserts power supply VCC, and the grid of P3 receives Verror1, and the drain electrode of P3 is the output of output stage amplifying unit 13, and Verror1 is further amplified back output voltage signal Verror2.The drain electrode of N4 is connected with the drain electrode of P3, the grid input offset voltage Vbias of N4, the source ground of N4.The first input end of pulse-width modulation comparator 14 receives the voltage signal Verror2 of output stage amplifying unit 13 outputs, the signal that the continuous cycle of its second input input changes, and in one-period in office, interval between crossing 2 of the signal that described cycle changes and arbitrary level changes with the variation of level size, the signal that 14 couples of Verror2 of pulse-width modulation comparator and this change in cycle compares, and output and Verror2 duty ratio corresponding and with the pulse-width signal Vpwm in corresponding cycle of signal of this periodic transformation.The first input end of pulse-width modulation logical block 15 receives pulse-width signal Vpwm, its second input input overcurrent pulse train Vlimit, pulse-width signal Vpwm and overcurrent pulse train Vlimit carry out logical process in pulse-width modulation logical block 15 after, output control signal CS.Switch element 16 receives the control signal CS of pulse-width modulation logical block 15 outputs.18 pairs of electric currents by switch element 16 of over-current detection unit carry out current detecting, when this overcurrent, also are when overcurrent occurring in the DCDC transducer 1, and over-current detection unit 18 produces and export this overcurrent pulse train Vlimit.The output of energy-storage units 17 receiving key unit 16, through output voltage VO UT after the energy storage, its output is the output of DCDC transducer.
In DCDC transducer 1 operate as normal, when namely overcurrent not occurring, over-current detection unit 18 does not produce overcurrent pulse train Vlimit, and the output of pulse-width modulation logical block 15 is only by the Vpwm signal deciding.But when overcurrent detecting unit 18 detected overcurrent by switch element 17, DCDC transducer 1 entered current-limit mode.Below, illustrate that in conjunction with Fig. 2 and Fig. 3 DCDC transducer 1 produces the reason of overshoot overshoot when entering normal mode of operation by current-limit mode.DCDC transducer 1 is under current-limit mode, and the output of pulse-width modulation logical block 15 only determines that by overcurrent pulse train Vlimit namely DCDC transducer 1 was under the stream mode, and pulse-width signal Vpwm is inoperative for DCDC transducer 1.The overcurrent here is to occur overcurrent in the DCDC transducer 1 to refer to that electric current by switch element 17 is greater than the electric current of the tolerance range of this switch element 17.When this overcurrent occurred, the output voltage VO UT of DCDC transducer 1 descended, and along with the decline of VOUT, its sampling feedback voltage Vfb diminishes, and makes the output voltage V error2 of output stage amplifying unit 13 increase.When DCDC transducer 1 entered operate as normal from current-limit mode, the Vpwm signal restarted to control the output voltage VO UT of DCDC transducer.And in the DCDC of prior art transducer 1, the Vpwm signal returns to normal operating conditions and has certain delay, this main cause that postpone to produce is to remove current-limit mode moment at DCDC transducer 1, Verror2 will reduce along with the discharge of output stage amplifying unit, but difference is amplified the velocity of discharge of the N4 of the N3 of input stage unit 12 and output stage amplifying unit 13 and all is biased voltage Vbias and limits, and causes speed that the output voltage signal Verror2 of output stage amplifying unit 13 reduces (referring to the slow speed among Fig. 3) slowly.And at this section in time of delay, energy-storage travelling wave tube 17 continues energy storage, thereby has produced the overshoot overshoot of VOUT.This overshoot overshoot may damage this DCDC transducer 1 and the components and parts of being correlated with on every side.
Therefore, suppress the overshoot that the DCDC transducer occurs when current-limit mode enters normal mode of operation and become the problem that presses for solution.
Summary of the invention
Propose the present invention in order to overcome the above-mentioned problems in the prior art, the purpose of this invention is to provide a kind of DCDC transducer that can suppress its overshoot voltage that when current-limit mode is converted to normal mode of operation, occurs.
DCDC transducer involved in the present invention has: the sampling feedback unit, and the one end connects the voltage output end of described DCDC transducer, and its other end is connected with ground; Difference is amplified the input stage unit, its first input end inserts described sampling feedback unit, output voltage to described DCDC transducer is taken a sample, its second input input reference voltage, described difference is amplified the input stage unit and is used for relatively and amplifies poor between the sampling voltage of output voltage of described DCDC transducer and reference voltage, and the output that described difference is amplified the input stage unit is exported the amplification voltage signal of described difference; The output stage amplifying unit, its input receive described difference amplification voltage signal and and the feeder ear of described output stage amplifying unit between be connected with first switching circuit, described first switching circuit with described DCDC transducer in conducting under the effect of the rp pulse of relevant overcurrent pulse with overcurrent that occurs, when namely having overcurrent pulse control, described DCDC transducer operate as normal do not disconnect, be connected with the second switch circuit between the output of described output stage amplifying unit and the ground, the conducting under the control of described overcurrent pulse of described second switch circuit, disconnect when described DCDC transducer operate as normal namely has overcurrent pulse control, described output stage amplifying unit is according to conducting or the disconnection output corresponding voltage signal of described first switching circuit and described second switch circuit.
Again, the DCDC transducer that the present invention relates to also has: the pulse-width modulation comparator, its first input end receives the voltage signal of the described output of described output stage amplifying unit, the signal that the continuous cycle of its second input input changes, and in one-period in office, interval between crossing 2 of the signal that described cycle changes and arbitrary level changes with the variation of level size, described pulse-width modulation comparator is for the voltage signal of the described output of more described output stage amplifying unit and the signal of variation of described cycle, with the output pulse width modulation signal; Switch unit, its first input end receives the pulse-width signal of described pulse width modulator output, its second input was imported signal pulse stream, when described switch unit overcurrent occurs in described DCDC transducer, export the described signal pulse stream of crossing, when described DCDC transducer operate as normal, export described pulse-width signal; The pulse-width modulation logical block, its first input end receives described signal pulse stream or the described pulse-width signal crossed of described switch unit output, its second input input overcurrent pulse train, described pulse-width modulation logical block is according to output signal or the described overcurrent pulse train output control signal of described switch unit.
Again, the DCDC transducer that the present invention relates to further has: switch element, receive the control signal of described pulse-width modulation logical block output, and select the mode of operation of described DCDC transducer according to described control signal, and export the signal corresponding with its selected mode of operation; Over-current detection unit detects the electric current by described switch element, and when this overcurrent, described current detecting unit produces and export described overcurrent pulse train; Energy-storage units receives the described signal of described switch element output, and will export the output of described DCDC transducer by the voltage signal after the described energy-storage units energy storage to.
Again, described first switching circuit is the PMOS pipe, its source electrode is connected with the feeder ear of described output stage amplifying unit, and its drain electrode receives the amplification voltage signal that described difference is amplified the described difference of input stage unit output, the described inversion signal of crossing signal pulse stream of its grid input; Described second switch circuit is the NMOS pipe, and its drain electrode receives the described voltage signal of described output stage amplifying unit output, its source ground, the described signal pulse stream of crossing of its grid input.
Again, described switch unit has: OR-NOT circuit, and its first end is connected with the first input end of described switch unit, and its two input receives the described signal pulse stream of crossing; First inverter, its input is connected with the output of described OR-NOT circuit, and its output is connected with the output of described switch unit.
Again, the width of described overcurrent pulse equates with the width of described overcurrent pulse train.
Again, DCDC transducer involved in the present invention also comprises the pulse generator of the described overcurrent pulse that a generation is associated with described overcurrent pulse train.
Again, described pulse generator has: second inverter, its input are imported described overcurrent pulse train; Electric capacity is connected between the output and ground of described second inverter; The 3rd inverter, its input receive the signal of described second inverter output, and export the described signal pulse stream of crossing.
Be connected with constant-current source between the output of described output stage amplifying unit and the ground again.
Be connected with resistance between the output of described output stage amplifying unit and the ground again.
According to DCDC transducer involved in the present invention, suppressed its overshoot voltage that when current-limit mode is converted to normal mode of operation, occurs effectively.
Description of drawings
The general structure that realizes each feature of the present invention is hereinafter described with reference to the accompanying drawings.The accompanying drawing that provides and associated description are used for the explanation embodiments of the invention, but are not limited to the present invention.
Fig. 1 is that the summary of DCDC transducer of the prior art constitutes block diagram.
Fig. 2 is the partial circuit structure chart in the DCDC transducer of the prior art.
Fig. 3 is the oscillogram of part of nodes in the circuit structure of DCDC transducer of the prior art.
Fig. 4 is that the summary of the DCDC transducer of embodiments of the present invention constitutes block diagram.
Fig. 5 improves relevant circuit structure diagram in the present invention in the DCDC transducer of embodiments of the present invention.
Fig. 6 is the oscillogram of part of nodes in the circuit structure of DCDC transducer of embodiments of the present invention.
Fig. 7 is the physical circuit legend of the pulse generator of embodiments of the present invention.
Describe embodiments of the present invention in detail below in conjunction with accompanying drawing, part same as the prior art is marked with identical label in the accompanying drawing, and omits its detailed description.
Embodiment
Execution mode about DCDC transducer involved in the present invention describes with reference to accompanying drawing.
Fig. 5 is the circuit structure diagram of the DCDC transducer of embodiments of the present invention.As shown in Figure 5, the DCDC transducer 2 of embodiments of the present invention has: sampling feedback unit 11, for example be the resistor voltage divider network with two series resistance R1, R2, the one end connects the voltage output end VOUT of described DCDC transducer 2, and its other end is connected with ground; Difference is amplified input stage unit 12, its first input end inserts described sampling feedback unit 11, output voltage VO UT to DCDC transducer 2 takes a sample, its second input input reference voltage Vref, difference input amplifying stage unit 12 is used for relatively and amplifies poor between the sampling voltage Vfb of output voltage VO UT of DCDC transducer 2 and reference voltage V ref, and the output of difference input amplifying stage unit 12 is exported the amplification voltage signal Verror1 of described difference; Output stage amplifying unit 33, its input receive difference amplification voltage signal Verror1 and and the feeder ear VCC of output stage amplifying unit 33 between be connected with the first switching circuit M1, the first switching circuit M1 with DCDC transducer 2 in conducting under the effect of the rp pulse VLimit_delayB of relevant overcurrent pulse VLimit_delay with overcurrent that occurs, when namely having overcurrent pulse VLimit_delay control, DCDC transducer 2 operate as normal do not disconnect, be connected with second switch circuit M2 between the output of output stage amplifying unit 33 and the ground, second switch circuit M2 conducting under the control of overcurrent pulse Limit_delay, disconnect when DCDC transducer 2 operate as normal namely have overcurrent pulse VLimit_delay control, output stage amplifying unit 33 is according to conducting or the disconnection output corresponding voltage signal Verror2 ' of the first switching circuit M1 and second switch circuit M2.
DCDC transducer 2 of the present invention further has: pulse-width modulation comparator 14, its first input end receives the voltage signal Verror2 ' of the output of output stage amplifying unit 33, the signal that the continuous continuous cycle of its second input input changes, and in one-period in office, interval between crossing 2 of the signal that described cycle changes and arbitrary level changes with the variation of level size, here, the signal that changes of this continuous cycle for example is continuous triangular signal, continuous sawtooth signal or continuous dextrorotation ripple signal etc.Pulse-width modulation comparator 14 is used for the voltage signal Verror2 ' of the relatively output of output stage amplifying unit 33 and the signal of this cycle variation, with output pulse width modulation signal Vpwm; Switch unit 39, its first input end receives the pulse-width signal Vpwm of pulse width modulator 14 outputs, its second input was imported signal pulse stream VLimit_delay, when switch unit 39 overcurrent occurs in DCDC transducer 2, output overcurrent pulse signal VLimit_delay, when DCDC transducer 2 operate as normal, output pulse width modulation signal Vpwm; Pulse-width modulation logical block 15, its first input end receives signal pulse stream VLimit_delay or the pulse-width signal Vpwm excessively of switch unit 39 outputs, its second input input overcurrent pulse train Vlimit, pulse-width modulation logical block 15 is according to output signal or the overcurrent pulse train Vlimit output control signal CS of switch unit 39.
DCDC transducer 2 of the present invention further has: switch element 16, receive the control signal CS of pulse-width modulation logical block 15 outputs, and according to control signal CS select DCDC transducer 2 mode of operation (boost mode or decompression mode) (mode of operation not only inner just can determine, and the output voltage signal corresponding with its selected mode of operation but outer device architecture); Over-current detection unit 18 detects the electric current by switch element 16, and when this overcurrent, current detection circuit 18 produces and output overcurrent pulse train Vlimit; Energy-storage units 17, the signal of receiving key unit 16 outputs, and will export the output of described DCDC transducer 2 by the voltage signal VOUT after energy-storage units 17 energy storage to.
In the embodiment of DCDC transducer 2 of the present invention, the first switching circuit M1 for example is PMOS pipe P4, the feeder ear VCC of its source electrode and output stage amplifying unit 33 is connected, its drain electrode receives states the amplification voltage signal Verror1 that difference is amplified the difference of input stage unit 12 outputs, and its grid was imported the inversion signal VLimit_delayB of signal pulse stream; Second switch circuit M2 for example is NMOS pipe N5, and its drain electrode receives the voltage signal Verror2 ' of the output of output stage amplifying unit 33, its source ground, and its grid was imported signal pulse stream VLimit_delay.
In the embodiment of DCDC transducer 2 of the present invention, a physical circuit example as switch unit 39, it constitutes and comprises: OR-NOT circuit G, and its first end is connected with the first input end of switch unit 39, and its two input received signal pulse stream VLimit_delay; The first inverter INV1, the output of its input AND circuit G connects, and its output is connected with the output of switch unit 39.
In the embodiment of DCDC transducer 2 of the present invention, also comprise the pulse generator 5 of the described overcurrent pulse that a generation is associated with described overcurrent pulse train in the DCDC transducer 2.As a physical circuit example of pulse generator 5, as shown in Figure 7, it constitutes and comprises: the second inverter INV2, its input import described overcurrent pulse train Vlimit; Capacitor C is connected between the output and ground of the second inverter INV2; The 3rd inverter INV3, its input receive the signal of second inverter INV2 output, and output overcurrent pulse signal Vlimit.
In the embodiment of DCDC transducer 2 of the present invention, be connected with the very big resistance of constant-current source metal-oxide-semiconductor N4 or resistance (not shown) between the output of output stage amplifying unit 33 and the ground.
In the embodiment of DCDC transducer 2 of the present invention, as shown in Figure 6, the width of overcurrent pulse VLimit_delay equates with the width of overcurrent pulse train Vlimit.
In specific embodiments of the invention, DCDC transducer 2 is identical with the operation principle of DCDC transducer 1 of the prior art, is not described in detail here.Below, in conjunction with Fig. 4-Fig. 7, the process that the DCDC transducer 2 of embodiments of the present invention is suppressed its overshoot voltages that occur when current-limit mode enters normal mode of operation is elaborated.
When overcurrent detecting unit 18 detects electric current by switch element 17 greater than predetermined value, produce overcurrent pulse train Vlimit, at this moment, pulse generator 5 produces the overcurrent pulse VLimit_delay that triggers simultaneously with overcurrent pulse train Vlimit, for example VLimit_delay is high level, then P4 is at the inversion signal VLimit_delayB of VLimit_delay, it is conducting under the low level control, make P3 end, simultaneously, N5 conducting under the control of VLimit_delay high level, the voltage signal Verror2 ' of the output of output stage amplifying unit 33 is dragged down rapidly, at this moment, pulse-width modulation comparator 14 output has the pulse-width signal Vpwm in the corresponding cycle of signal that changes with Verror2 ' duty ratio corresponding and with this cycle, and this Vpwm can export pulse-width modulation logical block 15 to, again, pulse-width modulation logical block 15 is during overcurrent, its output is only determined by overcurrent pulse train Vlimit, for fear of Vpwm signal during overcurrent to the influence of pulse-width modulation logical block 15, the DCDC transducer 2 of embodiments of the present invention has increased commutation circuit 39, be Vpwm and VLimit_delay through behind OR-NOT circuit G and the first inverter INV1, output fixedly high level signal to pulse-width modulation logical block 15.When DCDC transducer 2 entered normal mode of operation by current-limit mode, VLimit_delay became low level, and N5 ends, simultaneously, P4 namely also ends under the control of high level at the inversion signal VLimit_delayB of VLimit_delay, the P3 conducting, Verror2 ' rises rapidly.In conjunction with Fig. 3 and Fig. 7 as seen, the time that the time ratio Verror2 that Verror2 ' rises descends is fast, thereby the delay of pulse-width signal Vpwm reduces, corresponding therewith, the energy storage time of energy-storage travelling wave tube 17 reduces, the output voltage VO UT overshoot of DCDC transducer 2 obviously reduces, thus the overshoot phenomenon when having suppressed that this DCDC transducer 2 enters normal mode of operation from current-limit mode.
In addition; for each selected in embodiments of the present invention device; those skilled in the art are based on the common practise of this area; PMOS can be managed the corresponding NMOS of replacing with pipe; NMOS is managed the corresponding PMOS of replacing with pipe; also can select for use other devices that can realize identical function to substitute each selected in the above-described embodiments device, the perhaps connected mode between each device of corresponding change, these do not break away from protection scope of the present invention.
Though specific implementations of the present invention is described, this execution mode is just explained by the mode of example, and be not intended to limit the scope of the invention.In fact, reference voltage generating circuit described herein can be implemented by various other forms; In addition, also can carry out to reference voltage generating circuit described herein various omissions, substitute and change and do not deviate from spirit of the present invention.Attached claim and the purpose of equivalents thereof are to contain such various forms or the modification that falls in the scope and spirit of the present invention.
Claims (10)
1. DCDC transducer is characterized in that having:
The sampling feedback unit, the one end connects the voltage output end of described DCDC transducer, and its other end is connected with ground;
Difference is amplified the input stage unit, its first input end inserts described sampling feedback unit, output voltage to described DCDC transducer is taken a sample, its second input input reference voltage, described difference is amplified the input stage unit and is used for relatively and amplifies poor between the sampling voltage of output voltage of described DCDC transducer and reference voltage, and the output that described difference is amplified the input stage unit is exported the amplification voltage signal of described difference;
The output stage amplifying unit, its input receive described difference amplification voltage signal and and the feeder ear of described output stage amplifying unit between be connected with first switching circuit, the conducting under the effect of the rp pulse of the overcurrent pulse relevant with the overcurrent that occurs in the described DCDC transducer of described first switching circuit, when namely having overcurrent pulse control, described DCDC transducer operate as normal do not disconnect, be connected with the second switch circuit between the output of described output stage amplifying unit and the ground, the conducting under the control of described overcurrent pulse of described second switch circuit, disconnect when described DCDC transducer operate as normal namely has overcurrent pulse control, described output stage amplifying unit is according to conducting or the disconnection output corresponding voltage signal of described first switching circuit and described second switch circuit.
2. DCDC transducer according to claim 1 is characterized in that, described DCDC transducer also has:
The pulse-width modulation comparator, its first input end receives the voltage signal of the described output of described output stage amplifying unit, the signal that the continuous cycle of its second input input changes, and in one-period in office, interval between crossing 2 of the signal that described cycle changes and arbitrary level changes with the variation of level size, described pulse-width modulation comparator is for the voltage signal of the described output of more described output stage amplifying unit and the signal of variation of described cycle, with the output pulse width modulation signal;
Switch unit, its first input end receives the pulse-width signal of described pulse width modulator output, its second input was imported signal pulse stream, when described switch unit overcurrent occurs in described DCDC transducer, export the described signal pulse stream of crossing, when described DCDC transducer operate as normal, export described pulse-width signal;
The pulse-width modulation logical block, its first input end receives described signal pulse stream or the described pulse-width signal crossed of described switch unit output, its second input input overcurrent pulse train, described pulse-width modulation logical block is according to output signal or the described overcurrent pulse train output control signal of described switch unit.
3. DCDC transducer according to claim 1 and 2 is characterized in that, described DCDC transducer further has:
Switch element receives the control signal that described pulse-width modulation logical block is exported, and selects the mode of operation of described DCDC transducer according to described control signal, and exports the signal corresponding with its selected mode of operation;
Over-current detection unit detects the electric current by described switch element, and when this overcurrent, described current detecting unit produces and export described overcurrent pulse train;
Energy-storage units receives the described signal of described switch element output, and will export the output of described DCDC transducer by the voltage signal after the described energy-storage units energy storage to.
4. DCDC transducer according to claim 3 is characterized in that,
Described first switching circuit is the PMOS pipe, its source electrode is connected with the feeder ear of described output stage amplifying unit, its drain electrode receives the amplification voltage signal that described difference is amplified the described difference of input stage unit output, the described inversion signal of crossing signal pulse stream of its grid input;
Described second switch circuit is the NMOS pipe, and its drain electrode receives the described voltage signal of described output stage amplifying unit output, its source ground, the described signal pulse stream of crossing of its grid input.
5. DCDC transducer according to claim 4 is characterized in that, described switch unit has:
OR-NOT circuit, its first end is connected with the first input end of described switch unit, and its two input receives the described signal pulse stream of crossing;
First inverter, its input is connected with the output of described OR-NOT circuit, and its output is connected with the output of described switch unit.
6. DCDC transducer according to claim 5 is characterized in that, the width of described overcurrent pulse equates with the width of described overcurrent pulse train.
7. DCDC transducer according to claim 6 is characterized in that, described DCDC transducer also comprises the pulse generator of the described overcurrent pulse that a generation is associated with described overcurrent pulse train.
8. DCDC transducer according to claim 7 is characterized in that, described pulse generator has:
Second inverter, its input are imported described overcurrent pulse train;
Electric capacity is connected between the output and ground of described second inverter;
The 3rd inverter, its input receives the output signal of described second inverter, and exports the described signal pulse stream of crossing.
9. according to claim 7 or 8 described DCDC transducers, it is characterized in that, be connected with constant-current source between the output of described output stage amplifying unit and the ground.
10. according to claim 7 or 8 described DCDC transducers, it is characterized in that, be connected with resistance between the output of described output stage amplifying unit and the ground.
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| CN109936224A (en) * | 2014-03-11 | 2019-06-25 | Lg伊诺特有限公司 | Use the method and radio energy transmitter of magnetic induction transmission radio energy |
| CN109936224B (en) * | 2014-03-11 | 2023-02-28 | Lg伊诺特有限公司 | Method for transmitting wireless power using magnetic induction and wireless power transmitter |
| CN109861511A (en) * | 2018-12-30 | 2019-06-07 | 惠州华科电器有限公司 | Current foldback circuit and Over Current Protection System |
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| CN103259405B (en) | 2015-10-07 |
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