CN103219299A - 集成电路封装组件及其形成方法 - Google Patents
集成电路封装组件及其形成方法 Download PDFInfo
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- CN103219299A CN103219299A CN2012102586780A CN201210258678A CN103219299A CN 103219299 A CN103219299 A CN 103219299A CN 2012102586780 A CN2012102586780 A CN 2012102586780A CN 201210258678 A CN201210258678 A CN 201210258678A CN 103219299 A CN103219299 A CN 103219299A
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Abstract
一种集成电路封装组件包括:第一集成电路封装件和设置在第一集成电路封装件下方的第二集成电路封装件。焊料凸块设置在第一集成电路封装件和第二集成电路封装件之间,在第一集成电路封装件和第二集成电路封装件之间提供电信号连接。至少一个支撑结构设置在第一集成电路封装件和第二集成电路封装件之间,以促进第一集成电路封装件和第二集成电路封装件之间的热传导而不提供电信号连接。本发明提供了集成电路封装组件及其形成方法。
Description
技术领域
本发明大体上涉及集成电路封装件,更具体而言,涉及堆叠封装件(POP)。
背景技术
堆叠封装件(POP)是允许垂直结合多个封装件(例如离散逻辑和存储器球栅阵列(BGA)封装件)的集成电路封装技术。两个或多个封装件以相互堆叠的方式安装,即,堆叠,在它们之间具有按路线发送电信号的电接口。这允许在移动设备(例如移动电话或个人数字助理(PDA))中使用更高密度的集成电路芯片。然而,由于在组合的多个封装件中所用的材料不同,POP结构可能具有诸如散热或不匹配的热膨胀系数的热(热量)相关问题。
发明内容
一方面,本发明提供了一种集成电路封装组件,包括:第一集成电路封装件;第二集成电路封装件,设置在所述第一集成电路封装件下方;焊料凸块,设置在所述第一集成电路封装件和所述第二集成电路封装件之间,在所述第一集成电路封装件和所述第二集成电路封装件之间提供电信号连接;以及至少一个第一支撑结构,设置在所述第一集成电路封装件和所述第二集成电路封装件之间以促进所述第一集成电路封装件和所述第二集成电路封装件之间的热传导而不提供电信号连接。
在所述的集成电路封装组件中,所述第一集成电路封装件包括安装在第一基板上的第一集成电路管芯;所述第二集成电路封装件包括安装在第二基板上的第二集成电路管芯;并且,所述至少一个第一支撑结构包括设置在所述第一基板和所述第二集成电路管芯之间的缓冲层。
在所述的集成电路封装组件中,所述缓冲层包含热导率为至少1.0W/℃·m的聚合物。
在所述的集成电路封装组件中,所述第一基板和所述第二基板包含有机材料或硅。
在所述的集成电路封装组件中,所述第二基板包括中介层。
在所述的集成电路封装组件中,所述至少一个第一支撑结构包括在没有焊料凸块的位置中设置的短块。
在所述的集成电路封装组件中,所述短块包含与所述焊料凸块相同的材料。
在所述的集成电路封装组件中,所述短块包含比所述焊料凸块具有更高熔化温度的材料。
在所述的集成电路封装组件中,所述短块具有为至少227℃的熔化温度。
所述的集成电路封装组件还包括:为焊料凸块提供电接触表面的焊盘,其中,所述焊盘设置在所述第一集成电路封装件面向所述焊料凸块的第一面上和所述第二集成电路封装件面向所述焊料凸块的第二面上。
所述的集成电路封装组件还包括:印刷电路板,所述印刷电路板设置在所述第二集成电路封装件下方,通过设置在所述第二集成电路封装件和所述印刷电路板之间的焊料凸块电连接至所述第二集成电路封装件。
所述的集成电路封装组件还包括:至少一个第二支撑结构,所述至少一个第二支撑结构设置在所述第二集成电路封装件和所述印刷电路板之间,以促进所述第二集成电路封装件和所述印刷电路板之间的热传导而不提供电信号连接。
另一方面,本发明提供了一种制造集成电路封装组件的方法,包括:在第一集成电路封装件下方形成焊料凸块;在所述第一集成电路封装件下方或者在所述第二集成电路封装件上方形成至少一个第一支撑结构,其中,所述至少一个第一支撑结构不提供电信号连接;以及在第二集成电路封装件上方安装所述第一集成电路封装件。
在所述的方法中,所述至少一个第一支撑结构包括缓冲层,所述缓冲层形成在所述第二集成电路封装件中的管芯上方。
在所述的方法中,所述缓冲层包含热导率为至少1.0W/℃·m的聚合物。
在所述的方法中,所述至少一个第一支撑结构包括在没有焊料凸块的位置中设置的短块。
在所述的方法中,所述短块与所述焊料凸块同时形成。
所述的方法还包括:在所述第二集成电路封装件下方或者在印刷电路板上方形成至少一个第二支撑结构,其中,所述至少一个第二支撑结构不提供电信号连接。
所述的方法还包括:在所述印刷电路板上方安装所述第二集成电路封装件。
又一方面,本发明还提供了一种集成电路封装组件,包括:第一集成电路封装件,包括安装在第一基板上的第一集成电路管芯;第二集成电路封装件,包括安装在第二基板上的第二集成电路管芯,所述第二集成电路封装件设置在所述第一集成电路封装件下方;焊料凸块,设置在所述第一集成电路封装件和所述第二集成电路封装件之间,在所述第一集成电路封装件和所述第二集成电路封装件之间提供电信号连接;以及缓冲层,设置在所述第一基板和所述第二集成电路管芯之间,以促进所述第一集成电路封装件和所述第二集成电路封装件之间的热传导;以及短块,设置在所述第一集成电路封装件和所述第二集成电路封装件之间,以促进所述第一集成电路封装件和所述第二集成电路封装件之间的热传导而不提供电信号连接。
附图说明
现在将结合附图所进行的以下描述作为参考,其中:
图1是根据一些实施例的示例性堆叠封装件(POP)组件的示意图;
图2是根据一些实施例的另一示例性POP组件的示意图;
图3是根据一些实施例的又一示例性POP组件的示意图;
图4是根据一些实施例的又一示例性POP组件的示意图;
图5是根据一些实施例的又一示例性POP组件的示意图;
图6是根据一些实施例的示例性POP组件的布局;以及
图7是根据一些实施例制造POP组件的示例性方法的流程图。
具体实施方式
在下面详细地论述本发明各个实施例的制造和使用。然而,应当理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅是制造和使用的示例性具体方式,而不是用于限制本发明的范围。
另外,本发明可能在各个实例中重复参考数字和/或字母。这种重复只是为了简明和清楚的目的且其本身并不指定所论述的各个实施例和/或结构之间的关系。而且,在随后的本发明中在另一个部件上、连接和/或偶联至另一个部件的一个部件的形成可以包括其中部件以直接接触形成的实施例,并且也可以包括其中可以形成介入部件中的额外的部件,从而使部件可以不直接接触的实施例。另外,空间相对位置的术语,例如“下”、“上”、“水平”、“垂直”、“在...上方”、“在...下方”、“向上”、“向下”、“顶部”、“底部”等及其派生词(例如,“水平地”、“向下地”、“向上地”等)用于简化本发明中一个部件和另一个部件的关系。这些空间相对术语预期用于涵盖包括这些部件的器件的不同方位。
图1是根据一些实施例的示例性堆叠封装件(POP)组件100的示意图。POP组件100包括顶部集成电路封装件(“顶部封装件”)102、底部集成电路封装件(“底部封装件”)104、用于球栅阵列(BGA)封装的焊料凸块(焊球)106和110、缓冲层108、和印刷电路板(PCB)112。(焊料凸块106和110被视为不是底部封装件104的一部分。)顶部封装件102包括顶部集成电路管芯(“顶部管芯”)116(在该实例中为倒装芯片封装件)、使用位于顶部基板114上的一些焊盘120将顶部管芯116电连接至顶部基板114的接合线118。模塑料130封装顶部管芯116和接合线118。接合线118和焊盘120可以包括铝、铜、金、或者任何其他合适的导电材料。
底部封装件104包括通过用于电连接的微凸块(诸如可控塌陷芯片连接凸块或者有时也被称为C4凸块)126安装在底部基板122上的底部管芯124。底部填充物128(例如环氧树脂混合物)填充底部管芯124和底部基板122之间的间隙。底部基板122通过用于电连接的焊料凸块110安装在PCB 112上。一些焊盘120提供用于焊料凸块106和110的电接触表面。
焊料凸块106和110提供顶部封装件102和底部封装件104之间、或者底部封装件104和PCB 112之间的电信号连接。焊料凸块106和110可以包含SAC405(Sn/4.0Ag/0.5Cu)、SAC105(Sn/1.0Ag/0.5Cu)、其他基于SnCu的材料、或者任何其他合适的材料。顶部基板114和底部基板122可以包含有机材料、Si中介层、或者任何其他合适的材料。
可以在底部管芯124上方形成缓冲层108以吸收顶部封装件102和底部封装件104之间的应力,该应力是由于封装组件的各个部分(尤其是例如顶部基板114、底部管芯124、和焊料凸块106)之间的热膨胀系数(CTE)不匹配引起的。缓冲层108可以包含具有用于散热的良好导热率(例如为至少1.0W/℃·m)的聚合物材料。可以通过在底部管芯124上旋转涂布形成缓冲层108。在一些实施例中,在管芯切割之前,在底部管芯124的底部集成电路晶圆上形成缓冲层108。在一些实施例中,在顶部封装件102的底部下方形成缓冲层108。
在一个实例中,顶部封装件102的厚度为约500μm,其大小为约12×12mm,顶部基板114的厚度为约175μm(其大小为约12×12mm),底部基板122的厚度为约250μm(其大小为约12×12mm),底部管芯124和底部填充物128具有约190μm的合并厚度,并且焊料凸块(BGA球)106和110的厚度为约190μm,其大小为约240μm。缓冲层108具有与底部管芯124相似的尺寸,并且缓冲层108的厚度(例如,约80μm)与底部管芯124和顶部封装件102之间的间隙相同。POP组件100中的元件的尺寸和大小根据集成电路设计而进行改变。
与一些其他的封装方法相比,POP组件100由于较短的电气路径导致相对较低的IR降而具有相对低型、更好的信号完整性。并且POP组件100由于缓冲层108提供的更大的传热面积还具有更高的热导率。尽管在PCB112上安装了POP组件100中的两个封装件(顶部封装件102和底部封装件104),但是在PCB 112上可以安装不同数量的封装件,并且可以在多个平面上使用缓冲层108。
图2是根据一些实施例的另一示例性POP组件的示意图。POP组件200包括短块(stub block)202而不包括图1中的缓冲层108。可以通过模板控制(stencil control)在底部封装件104的表面(底部基板122)上放置短块202,其类似于落在相同的平面中的BGA球。短块202设置在没有焊料凸块106的位置处。
短块202可以包括与焊料凸块106和110(BGA球)相同的焊料材料或者比焊料凸块106和110具有更高熔化温度的不同材料。在一些实施例中,短块202具有比焊料凸块106和110高10℃的熔化温度(Tm)。例如,使用SAC405的焊料凸块106或者110的熔化温度是217℃,而使用SAC105的短块202的熔化温度是230℃,以及使用Sn-0.7Cu(Sn 99.3%和Cu 0.7%)的短块202的熔化温度是227℃。
虽然焊料凸块106和110被设计用于电信号连接(集成电路功能),但是短块202被设计用于加强POP组件200的机械强度并且有利于其的热管理。而且,顶部封装件102和底部封装件104的底部管芯124之间的短块202有助于控制POP组件200中CTE诱导的翘曲。在一些实施例中,短块202具有约100μm至300μm的宽度和长度。根据位置和/或应用,短块202可以具有不同的形状(诸如圆形、正方形、矩形等等)和各种尺寸。
因为短块202提供了更大的传热面积,POP组件200与传统结构相比具有更高的热导率。虽然在PCB 112上安装了POP组件200中的两个封装件(顶部封装件102和底部封装件104),但是在PCB 112上可以安装不同数量的封装件,并且在多个平面中可以使用短块202。
图3是根据一些实施例的又一示例性POP组件的示意图。POP组件300包括位于底部封装件104和PCB 112之间而不是位于图2中的顶部封装件102和底部封装件104之间的短块302。可以通过模板控制在PCB 112的表面上放置短块302(在没有焊料凸块110的位置处),其类似于落在相同的平面中的BGA球。
图4是根据一些实施例的又一示例性POP组件的示意图。POP组件400包括缓冲层108、位于顶部封装件102和底部封装件104之间的短块402、以及位于底部封装件104和PCB 112之间的短块404。
图5是根据一些实施例的又一示例性POP组件的示意图。POP组件500中的底部封装件104包括使用微凸块126安装在底部基板122上的多个底部管芯124。缓冲层108、顶部封装件102和底部封装件104之间的短块502、以及底部封装件104和PCB 112之间的短块504有利于加强POP组件500的机械强度及其热管理。而且,短块502和504有利于控制POP组件500中CTE诱导的翘曲。
图6是根据一些实施例的示例性POP组件的布局。布局600包括位于整个布局区域606的多个底部管芯602和设置在各种位置的用于加强POP组件布局600的机械强度并且有助于POP组件布局600的热管理的短块604。根据允许的设计规则和不同应用的其他要求,可以在各种位置中放置短块604。
图7是根据一些实施例的制造示例性POP组件的方法的流程图。在步骤702中,在第一集成电路封装件下方形成焊料凸块。焊料凸块可以是例如BGA焊球。在步骤704中,在第一集成电路封装件下方或者在第二集成电路封装件上方形成至少一个第一支撑结构,其中至少一个第一支撑结构在第一集成电路封装件和第二集成电路封装件的电气元件之间不提供电信号连接。第一支撑结构可以是例如图1中的缓冲层108或者图2中的短块202。在步骤706中,在第二集成电路封装件上方例如通过BGA安装技术安装第一集成电路封装件。在步骤708中,在印刷电路板上方例如通过表面安装技术(SMT)安装第二集成电路封装件。
在各个实施例中,至少一个第一支撑结构包括在第二集成电路封装件中的管芯上方形成的缓冲层。在其他实施例中,缓冲层包含热导率为至少1.0W/℃·m的聚合物。
在各个实施例中,至少一个第一支撑结构包括在没有焊料凸块的位置中设置的短块。在一些实例中,短块与焊料凸块同时形成。在第二集成电路封装件下方或者在印刷电路板上方形成至少一个第二支撑结构,其中至少一个第二支撑结构不提供电信号连接。第二支撑结构可以是例如图3中的短块302。缓冲层108和短块202和302的详情如上所述。
根据一些实施例,一种堆叠封装(POP)组件包括第一集成电路封装件和设置在第一集成电路封装件下方的第二集成电路封装件。焊料凸块设置在第一集成电路封装件和第二集成电路封装件之间,在第一集成电路封装件和第二集成电路封装件之间提供电信号连接。至少一个支撑结构设置在第一集成电路封装件和第二集成电路封装件之间以促进第一集成电路封装件和第二集成电路封装件之间的热传导而不提供电信号连接。
根据一些实施例,一种制造堆叠封装(POP)组件的方法包括:在第一集成电路封装件下方形成焊料凸块。在第一集成电路封装件下方或者在第二集成电路封装件上方形成至少一个支撑结构,其中至少一个支撑结构不提供电信号连接。在第二集成电路封装件上方安装第一集成电路封装件。
本领域技术人员将了解本发明可以具有许多的实施例变化。尽管已经详细地描述了实施例及其部件,但应该理解,可以在不背离实施例的主旨和范围的情况下,在其中做各种改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据所公开的实施例将很容易地理解,根据本发明可以应用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。
以上方法实施例示出了示例性步骤,但是它们不一定需要按照所示出的顺序实施。根据本发明的实施例的主旨和范围,适当时可以添加、替换、改变顺序、和/或清除步骤。合并不同的权利要求和/或不同的实施例的实施例在本发明的范围内并且在回顾本发明之后对本领域技术人员来说是显而易见的。
Claims (10)
1.一种集成电路封装组件,包括:
第一集成电路封装件;
第二集成电路封装件,设置在所述第一集成电路封装件下方;
焊料凸块,设置在所述第一集成电路封装件和所述第二集成电路封装件之间,在所述第一集成电路封装件和所述第二集成电路封装件之间提供电信号连接;以及
至少一个第一支撑结构,设置在所述第一集成电路封装件和所述第二集成电路封装件之间以促进所述第一集成电路封装件和所述第二集成电路封装件之间的热传导而不提供电信号连接。
2.根据权利要求1所述的集成电路封装组件,其中,所述第一集成电路封装件包括安装在第一基板上的第一集成电路管芯;所述第二集成电路封装件包括安装在第二基板上的第二集成电路管芯;并且,所述至少一个第一支撑结构包括设置在所述第一基板和所述第二集成电路管芯之间的缓冲层。
3.根据权利要求1所述的集成电路封装组件,其中,所述至少一个第一支撑结构包括在没有焊料凸块的位置中设置的短块。
4.根据权利要求1所述的集成电路封装组件,还包括为焊料凸块提供电接触表面的焊盘,其中,所述焊盘设置在所述第一集成电路封装件面向所述焊料凸块的第一面上和所述第二集成电路封装件面向所述焊料凸块的第二面上。
5.根据权利要求1所述的集成电路封装组件,还包括印刷电路板,所述印刷电路板设置在所述第二集成电路封装件下方,通过设置在所述第二集成电路封装件和所述印刷电路板之间的焊料凸块电连接至所述第二集成电路封装件。
6.根据权利要求5所述的集成电路封装组件,还包括至少一个第二支撑结构,所述至少一个第二支撑结构设置在所述第二集成电路封装件和所述印刷电路板之间,以促进所述第二集成电路封装件和所述印刷电路板之间的热传导而不提供电信号连接。
7.一种制造集成电路封装组件的方法,包括:
在第一集成电路封装件下方形成焊料凸块;
在所述第一集成电路封装件下方或者在所述第二集成电路封装件上方形成至少一个第一支撑结构,其中,所述至少一个第一支撑结构不提供电信号连接;以及
在第二集成电路封装件上方安装所述第一集成电路封装件。
8.根据权利要求7所述的方法,其中,所述至少一个第一支撑结构包括在没有焊料凸块的位置中设置的短块。
9.根据权利要求7所述的方法,还包括:在所述第二集成电路封装件下方或者在印刷电路板上方形成至少一个第二支撑结构,其中,所述至少一个第二支撑结构不提供电信号连接。
10.一种集成电路封装组件,包括:
第一集成电路封装件,包括安装在第一基板上的第一集成电路管芯;
第二集成电路封装件,包括安装在第二基板上的第二集成电路管芯,所述第二集成电路封装件设置在所述第一集成电路封装件下方;
焊料凸块,设置在所述第一集成电路封装件和所述第二集成电路封装件之间,在所述第一集成电路封装件和所述第二集成电路封装件之间提供电信号连接;以及
缓冲层,设置在所述第一基板和所述第二集成电路管芯之间,以促进所述第一集成电路封装件和所述第二集成电路封装件之间的热传导;以及
短块,设置在所述第一集成电路封装件和所述第二集成电路封装件之间,以促进所述第一集成电路封装件和所述第二集成电路封装件之间的热传导而不提供电信号连接。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104900597A (zh) * | 2014-03-07 | 2015-09-09 | 台湾积体电路制造股份有限公司 | 半导体封装件及方法 |
CN106449551A (zh) * | 2016-11-24 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | 半导体结构及其形成方法、封装结构及其形成方法 |
CN107924899A (zh) * | 2015-08-27 | 2018-04-17 | 英特尔公司 | 多管芯封装 |
CN108987370A (zh) * | 2017-05-31 | 2018-12-11 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN109698168A (zh) * | 2017-10-20 | 2019-04-30 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN110797321A (zh) * | 2018-08-01 | 2020-02-14 | 三星电子株式会社 | 半导体封装件 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8749043B2 (en) | 2012-03-01 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package structure |
US8896094B2 (en) * | 2013-01-23 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for inductors and transformers in packages |
US9627325B2 (en) * | 2013-03-06 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package alignment structure and method of forming same |
US9449945B2 (en) | 2013-03-08 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Filter and capacitor using redistribution layer and micro bump layer |
US9524956B2 (en) * | 2014-10-31 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure and method |
US9595494B2 (en) * | 2015-05-04 | 2017-03-14 | Qualcomm Incorporated | Semiconductor package with high density die to die connection and method of making the same |
TWI550814B (zh) * | 2015-07-31 | 2016-09-21 | 矽品精密工業股份有限公司 | 承載體、封裝基板、電子封裝件及其製法 |
US9896330B2 (en) | 2016-01-13 | 2018-02-20 | Texas Instruments Incorporated | Structure and method for packaging stress-sensitive micro-electro-mechanical system stacked onto electronic circuit chip |
US10950568B2 (en) * | 2017-05-23 | 2021-03-16 | Micron Technology, Inc. | Semiconductor device assembly with surface-mount die support structures |
US10923447B2 (en) | 2017-05-23 | 2021-02-16 | Micron Technology, Inc. | Semiconductor device assembly with die support structures |
US11978727B2 (en) | 2017-09-28 | 2024-05-07 | Intel Corporation | Package on active silicon semiconductor packages |
US10861741B2 (en) | 2017-11-27 | 2020-12-08 | Texas Instruments Incorporated | Electronic package for integrated circuits and related methods |
US11538767B2 (en) * | 2017-12-29 | 2022-12-27 | Texas Instruments Incorporated | Integrated circuit package with partitioning based on environmental sensitivity |
TWI723492B (zh) * | 2019-08-14 | 2021-04-01 | 錼創顯示科技股份有限公司 | 黏取元件、微型發光二極體光學檢修設備及光學檢修方法 |
TWI705549B (zh) * | 2019-12-31 | 2020-09-21 | 矽品精密工業股份有限公司 | 電子封裝件 |
JP7484340B2 (ja) | 2020-03-31 | 2024-05-16 | ブラザー工業株式会社 | 端末装置のためのコンピュータプログラムと端末装置と通信装置 |
KR20220076894A (ko) | 2020-12-01 | 2022-06-08 | 삼성전자주식회사 | 지지 부재를 갖는 반도체 패키지 |
US11791319B2 (en) * | 2021-02-01 | 2023-10-17 | Nvidia Corporation | Edge-connected semiconductor systems |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030020151A1 (en) * | 2001-06-04 | 2003-01-30 | Siliconware Precision Industries Co., Ltd | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US20080036050A1 (en) * | 2006-08-08 | 2008-02-14 | Lin Paul T | Package with solder-filled via holes in molding layers |
US20090057864A1 (en) * | 2007-08-31 | 2009-03-05 | Daesik Choi | Integrated circuit package system employing an offset stacked configuration |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6847105B2 (en) * | 2001-09-21 | 2005-01-25 | Micron Technology, Inc. | Bumping technology in stacked die configurations |
JP2003318361A (ja) * | 2002-04-19 | 2003-11-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6998703B2 (en) * | 2003-12-04 | 2006-02-14 | Palo Alto Research Center Inc. | Thin package for stacking integrated circuits |
KR100585227B1 (ko) * | 2004-03-12 | 2006-06-01 | 삼성전자주식회사 | 열 방출 특성이 개선된 반도체 적층 패키지 및 이를이용한 메모리 모듈 |
TWI263256B (en) * | 2005-05-03 | 2006-10-01 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor device |
US20060267173A1 (en) * | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
US8643163B2 (en) * | 2005-08-08 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit package-on-package stacking system and method of manufacture thereof |
KR100712549B1 (ko) * | 2006-01-31 | 2007-05-02 | 삼성전자주식회사 | 패키지 리드를 포함하는 멀티 스택 패키지 |
IL175011A (en) * | 2006-04-20 | 2011-09-27 | Amitech Ltd | Coreless cavity substrates for chip packaging and their fabrication |
US8541872B2 (en) * | 2010-06-02 | 2013-09-24 | Stats Chippac Ltd. | Integrated circuit package system with package stacking and method of manufacture thereof |
US8659169B2 (en) * | 2010-09-27 | 2014-02-25 | Xilinx, Inc. | Corner structure for IC die |
KR101712043B1 (ko) * | 2010-10-14 | 2017-03-03 | 삼성전자주식회사 | 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법 |
US8619431B2 (en) * | 2010-12-22 | 2013-12-31 | ADL Engineering Inc. | Three-dimensional system-in-package package-on-package structure |
US8535981B2 (en) * | 2011-03-10 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit package-on-package system with underfilling structures and method of manufacture thereof |
TW201244051A (en) * | 2011-04-20 | 2012-11-01 | Universal Scient Ind Shanghai | Stacked-substrate structure |
-
2012
- 2012-01-19 US US13/353,644 patent/US8907469B2/en active Active
- 2012-07-24 CN CN201210258678.0A patent/CN103219299B/zh active Active
-
2014
- 2014-11-06 US US14/534,838 patent/US9123824B2/en active Active
-
2015
- 2015-08-05 US US14/818,877 patent/US9786635B2/en active Active
-
2017
- 2017-09-27 US US15/716,959 patent/US10163865B2/en active Active
-
2018
- 2018-12-14 US US16/220,268 patent/US10546838B2/en active Active
-
2020
- 2020-01-03 US US16/733,341 patent/US11171120B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030020151A1 (en) * | 2001-06-04 | 2003-01-30 | Siliconware Precision Industries Co., Ltd | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US20080036050A1 (en) * | 2006-08-08 | 2008-02-14 | Lin Paul T | Package with solder-filled via holes in molding layers |
US20090057864A1 (en) * | 2007-08-31 | 2009-03-05 | Daesik Choi | Integrated circuit package system employing an offset stacked configuration |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104900597A (zh) * | 2014-03-07 | 2015-09-09 | 台湾积体电路制造股份有限公司 | 半导体封装件及方法 |
CN104900597B (zh) * | 2014-03-07 | 2018-06-08 | 台湾积体电路制造股份有限公司 | 半导体封装件及方法 |
CN107924899A (zh) * | 2015-08-27 | 2018-04-17 | 英特尔公司 | 多管芯封装 |
CN107924899B (zh) * | 2015-08-27 | 2023-05-02 | 英特尔公司 | 多管芯封装 |
CN106449551A (zh) * | 2016-11-24 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | 半导体结构及其形成方法、封装结构及其形成方法 |
CN106449551B (zh) * | 2016-11-24 | 2020-06-19 | 苏州晶方半导体科技股份有限公司 | 半导体结构及其形成方法、封装结构及其形成方法 |
CN108987370A (zh) * | 2017-05-31 | 2018-12-11 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN109698168A (zh) * | 2017-10-20 | 2019-04-30 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN110797321A (zh) * | 2018-08-01 | 2020-02-14 | 三星电子株式会社 | 半导体封装件 |
CN110797321B (zh) * | 2018-08-01 | 2024-04-16 | 三星电子株式会社 | 半导体封装件 |
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US9786635B2 (en) | 2017-10-10 |
US9123824B2 (en) | 2015-09-01 |
US20130187266A1 (en) | 2013-07-25 |
US11171120B2 (en) | 2021-11-09 |
US20150064845A1 (en) | 2015-03-05 |
US20190123025A1 (en) | 2019-04-25 |
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