CN102636926A - 液晶显示面板及其制造方法 - Google Patents

液晶显示面板及其制造方法 Download PDF

Info

Publication number
CN102636926A
CN102636926A CN2011103411539A CN201110341153A CN102636926A CN 102636926 A CN102636926 A CN 102636926A CN 2011103411539 A CN2011103411539 A CN 2011103411539A CN 201110341153 A CN201110341153 A CN 201110341153A CN 102636926 A CN102636926 A CN 102636926A
Authority
CN
China
Prior art keywords
data line
tft
thin film
film transistor
display panels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011103411539A
Other languages
English (en)
Inventor
陈虹瑞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN2011103411539A priority Critical patent/CN102636926A/zh
Priority to US13/379,568 priority patent/US20130106679A1/en
Priority to PCT/CN2011/081845 priority patent/WO2013063814A1/zh
Publication of CN102636926A publication Critical patent/CN102636926A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133345Insulating layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50Protective arrangements
    • G02F2201/501Blocking layers, e.g. against migration of ions
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/10Materials and properties semiconductor
    • G02F2202/103Materials and properties semiconductor a-Si

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明公开一种液晶显示面板和其制造方法,于数据线与扫描线的重合区域,除了于数据线与扫描线之间利用一绝缘层来绝缘,还在所述绝缘层与数据线之间另建置一非晶硅层来加强数据线与扫描线之间的绝缘效果,进而降低漏电的状况。此外,本发明可以在不增加掩膜制程的条件下,达成前述的结构,因此,本发明液晶显示面板和其制造方法无须增加额外的成本,便可有效减少数据线与扫描线漏电的情况。

Description

液晶显示面板及其制造方法
技术领域
本发明是有关一种液晶显示面板及其制造方法,特别是指一种在数据线与扫描线之间另建置一非晶硅层,以增强数据线与扫描线之间的绝缘效果,进而避免数据线与扫描线之间漏电情况的液晶显示面板及其制造方法。
背景技术
传统液晶显示器的液晶显示面板包含数个像素(pixel),而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元构成。当栅极驱动器输出的扫描信号通过扫描线输入,使得每一行的像素单元的薄膜晶体管依序开启,同时源极驱动器则输出对应的数据信号,通过数据线输入至薄膜晶体管,而薄膜晶体管则将数据信号传递至像素电极,使其充电到各自所需的电压,进而使像素显示出不同的灰阶。栅极驱动器会一行接一行地输出扫描信号以将每一行的像素单元的薄膜晶体管打开,再由源极驱动器对每一行的像素电极进行充放电。如此依序下去,便可完成液晶显示面板的完整显示。
然而,传统液晶显示面板的制程上,每个数据线与扫描线的交接处(crossover)都会设置一绝缘层(insulating layer)以隔绝数据线与扫描线之间的电性连接。但是,由于绝缘层容易出现绝缘不佳的问题,使得数据线与扫描线之间产生漏电的现象,如此会使数据线与扫描线传递的信号不稳定,因此影响液晶显示面板的显示效果。
因此,业界须提出解决方式,以提升液晶显示面板的效能。
发明内容
有鉴于此,本发明提供一种液晶显示面板及其制造方法,其于数据线与扫描线的重合区域,除了于数据线与扫描线之间利用一绝缘层来绝缘,并于所述绝缘层与数据线之间另建置一非晶硅层来加强数据线与扫描线之间的绝缘效果,进而降低漏电的状况。
依据本发明的实施例,本发明提供一种液晶显示面板,所述液晶显示面板包括一玻璃基板以及一薄膜晶体管,所述薄膜晶体管包含一栅极、一源极以及一漏极;所述液晶显示面板另包含:一扫描线,位于所述玻璃基板上,所述扫描线耦接至所述薄膜晶体管的所述栅极;一绝缘层,位于所述扫描线之上;一数据线,位于所述绝缘层之上,耦接于所述薄膜晶体管的所述源极,其中所述数据线与所述扫描线重叠于一重合区域;以及一半导体层,位于所述栅极绝缘层以及所述数据线之间,所述半导体层之位置对应所述重合区域,且所述半导体层之面积之大于所述重合区域,以通过所述半导体层来加强所述数据线与扫描线之间的绝缘效果。
依据本发明的一实施例,本发明另提供一种液晶显示面板的制作方法,其包括下列步骤:提供一玻璃基板;形成一第一金属层于所述玻璃基板上;蚀刻所述第一金属层,以形成一薄膜晶体管的栅极以及一扫描线;在所述第一薄膜晶体管的栅极以及所述扫描在线形成一绝缘层;形成一半导体层于所述绝缘层上;蚀刻所述半导体层,以形成所述薄膜晶体管的通道区域以及一第一区域;以及形成一第二金属层,并蚀刻所述第二金属层,以形成所述薄膜晶体管的源极和漏极、以及一数据线;其中所述数据线与所述扫描线重叠于一重合区域,所述重合区域与所述第一区域的位置对应,且所述第一区域的面积大于所述重合区域。
依据本发明的实施例,所述半导体层为一非晶硅层。
依据本发明的实施例,所述第一区域之一边与所述数据线与所述扫描线的距离大于1.5微米((μm)。
相较于现有技术,本发明的液晶显示面板和其制造方法于数据线与扫描线的重合区域,除了于数据线与扫描线之间利用一栅极绝缘层来绝缘,并于所述栅极绝缘层与数据线之间另建置一非晶硅层来加强数据线与扫描线之间的绝缘效果,进而降低漏电的状况。此外,本发明可以在不增加掩膜制程的条件下,达成前述的结构,因此,本发明液晶显示面板和其制造方法无须增加额外的成本,便可有效减少数据线与扫描线漏电的情况。
为让本发明的上述内容能更明显易懂,下文特举一较佳实施例,并配合所附图式,作详细说明如下:
附图说明
图1是本发明液晶显示面板的简易示意图。
图2是图1的液晶显示面板的结构示意图。
图3至图6为本发明液晶显示面板的制程方式示意图。
具体实施方式
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语,例如“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“水平”、“垂直”等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。
请参阅图1,图1是本发明液晶显示面板100的简易示意图。液晶显示面板100包含数条数据线、数条扫描线、数条公共电压线(Common line)、数个薄膜晶体管和数个像素电极。每一薄膜晶体管电性连接一扫描线和一数据线。为简化图式,在以下实施例中,仅绘示数据线101、扫描线111、公共电压线105及薄膜晶体管120。薄膜晶体管120的栅极耦接到扫描线111,薄膜晶体管120的源极则耦接至数据线101。此外,薄膜晶体管120的漏极耦接至像素电极130。公共电压线105用来提供一公共电压信号。
液晶显示面板100的驱动方式如下所述:栅极驱动器(图未示)输出的扫描信号通过扫描线111输入,使得连接扫描线111的薄膜晶体管120依序开启,同时源极驱动器(未图示)则输出对应的数据信号,通过数据线101输入至薄膜晶体管120,而薄膜晶体管120则将数据信号传递至像素电极130,使其充电到所需的电压。而像素电极130上方的液晶就是依据该数据信号以及公共电压线105提供的公共电压信号间的电压差扭转(twist),进而显示出不同的灰阶。栅极驱动器会通过数条扫描线一行接一行地输出扫描信号以将每一行的薄膜晶体管120打开,再由源极驱动器对每一行的像素电极130进行充放电。如此依序下去,便可完成液晶显示面板100的完整显示。
请一并参阅图1和图2,图2是图1的液晶显示面板100的结构示意图。图2所绘示的是图1的液晶显示面板100沿A-A’和B-B’的截面图。图2于液晶显示面板100中,除了于数据线101与扫描线111的重合区域220本已建置的绝缘层510之外,本发明另于绝缘层510与数据线101之间建置一半导体层512。半导体层512覆盖的第一区域513大于数据线101与扫描线111重合区域。通过半导体层512的建置,可以增强数据线101与扫描线111间的绝缘效果,进而防止数据线101与扫描线111间漏电的发生。
第一区域513的面积比重合区域220更大。以图1右上角的第一区域513为例,重合区域220的边缘与第一区域513的边缘之间的距离D1大于1.5微米(μm),且距离数据线101的距离D2为1.5μm。基本上为了确保第一区域513的半导体层512能够确实地隔开扫描线111以及数据线101,第一区域513的面积必须大于重合区域。此外,根据实验结果,第一区域513与扫描线111以及数据线101的距离,较佳地必须大于1.5μm,如此方能确实降低扫描线111与数据线101的漏电效应。
在以下的揭露中,将说明本发明液晶显示面板100的制程方式。
请参阅图3,首先提供一个玻璃基板500当作下基板,接着进行一金属薄膜沉积制程,以于玻璃基板500表面形成一层第一金属层(未显示),并利用一第一掩膜来进行第一微影蚀刻(Photo Etching Process,PEP),以蚀刻得到薄膜晶体管120的栅极501以及扫描线111。
接着请参阅图4,接着沉积以氮化硅(SiNx)为材质的绝缘层510而覆盖栅极501以及扫描线111。于绝缘层510上连续沉积非晶硅(a-Si,Amorphous Si)层以及一高电子掺杂浓度的N+非晶硅层。利用第二掩膜来进行第二微影蚀刻以构成半导体层511、512。半导体层511包含作为薄膜晶体管120通道的非晶硅层511a以及用来降低阻抗的欧姆接触层(Ohmic contact layer)511b。半导体层512包含非晶硅层512a以及N+非晶硅层512b。半导体层512是位于第一区域513,而其功效如前述,用来辅助绝缘层510,以加强数据线101与扫描线111的绝缘效果。
请参阅图5,接着在绝缘层510上形成一全面覆盖的第二金属层(未绘示于图中),并利用第三掩膜来进行第三微影蚀刻以分别定义出薄膜晶体管120的源极521及漏极522以及数据线101。如图4亦可知,数据线与扫描线重叠于一重合区域220,而第一区域513的面积比重合区域220更大。较佳地,第一区域513的边界需大于数据线101(或扫描线111)的边界,其距离D2(或D1)大于1.5μm。
请参阅图6,如图6所示,接着沉积以氮化硅(SiNx)为材质的保护层(passivation layer)530,并覆盖源极521、及漏极522和绝缘层510,再利用第四掩膜来进行第四微影蚀刻用以去除漏极522上方的部份保护层530,直至漏极522表面,以于漏极522上方形成连接孔(Via)531。
请再参阅图2,图2也是图1所示的液晶显示面板100在第一区域513和薄膜晶体管120的结构示意图。在保护层530上形成以氧化铟锡物(Indiμmtin oxide,ITO)为材质的透明导电层,接着利用一第五掩膜蚀刻所述透明导电层以形成透明导电层130。透明电极层130通过预先形成的连接孔531与薄膜晶体管120的漏极522电性连接且连接至像素电容,以作为像素电极使用。至此,便完成本发明所述液晶显示面板100。
如图2所示,薄膜晶体管120的栅极501以一第一金属层作成,其源极521与漏极522以一第二金属层制成,而其通道则以一非晶硅层511作成。
此外,扫描线111亦以所述第一金属层作成,用来传递自栅极驱动器传递过来的扫描信号,而数据线101亦以所述第二金属层作成,用来传递自源极驱动器传递过来的数据信号。
在此请注意,扫描线111与数据线101之间,除了传统液晶显示面板便会建置的绝缘层510之外,另形成了半导体层512。半导体层512使扫描线111与数据线101之间的距离加大,亦增强了扫描线111与数据线101间的绝缘效果,进而避免数据线101与扫描线111间的漏电。
此外,半导体层512的面积必须大于扫描线111与数据线101重叠的重合区域220,如图2所示,半导体层512所在的第一区域513大于重合区域220,且其距离大于1.5μm,如此便可半导体层512确实隔开数据线101与扫描线111,避免数据线101与扫描线111间的漏电。
在此请注意,由于在传统的液晶屏幕制程之中,便已经有非晶硅层的沉积与微影蚀刻,但是,在传统的制程之中,非晶硅层仅仅作为薄膜晶体管120的通道使用,而并未有其他用途。因此,本发明利用原本的五道掩膜制程,将非晶硅层另形成于所述第一区域513,如此一来,本发明无须增加额外的成本与掩膜制程,便可将数据线101与扫描线111的距离拉大,以加强数据线101与扫描线111之间的绝缘效果,进而避免数据线101与扫描线111之间的漏电产生。
请继续参阅图1。在此请注意,虽然于前述的实施例中,本发明另建置的非晶硅层512是用来防止数据线101与扫描线111间的漏电状况,然而,如此的应用并非本发明的限制。在实际应用中,由于公共电压线105与扫描线111均是由第一金属层制成,且公共电压线105与数据线101亦会相互重叠。因此,半导体层512也可用设置于公共电压线105与数据线101之间,也就是说半导体层512另外覆盖的第二区域514,是大致上符合数据线101与公共电压线105的重合区域。因此半导体层512也可以加强公共电压线105与数据线101间的绝缘效果,如此的相对应变化,亦不违背本发明的精神。
综上所述,虽然本发明已以较佳实施例揭露如上,但该较佳实施例并非用以限制本发明,该领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种液晶显示面板,所述液晶显示面板包括一玻璃基板以及一薄膜晶体管,所述薄膜晶体管包含一栅极、一源极以及一漏极;其特征在于:所述液晶显示面板另包含:
一扫描线,位于所述玻璃基板上,所述扫描线耦接至所述薄膜晶体管的所述栅极;
一绝缘层,位于所述扫描线之上;
一数据线,位于所述绝缘层之上,耦接于所述薄膜晶体管的所述源极,其中所述数据线与所述扫描线重叠于一重合区域;以及
一半导体层,位于所述栅极绝缘层以及所述数据线之间,所述半导体层的位置对应所述重合区域,且所述半导体层的面积大于所述重合区域,以通过所述半导体层来加强所述数据线与所述扫描线之间的绝缘效果。
2.根据权利要求1所述的液晶显示面板,其特征在于:所述半导体层为一非晶硅层。
3.根据权利要求2所述的液晶显示面板,其特征在于:所述非晶硅层距的边缘与所述重合区域的边缘之间的距离大于1.5微米。
4.一种液晶显示面板,所述液晶显示面板包括一玻璃基板以及一薄膜晶体管,所述薄膜晶体管包含一栅极、一源极以及一漏极;其特征在于:所述液晶显示面板另包含:
一公共电压线,位于所述玻璃基板上,用来传递一公共电压至所述液晶显示面板;
一绝缘层,位于所述公共电压线之上;
一数据线,位于所述绝缘层之上,耦接于所述薄膜晶体管的所述源极,所述数据线与所述公共电压线重叠于一重合区域;以及 
一半导体层,位于所述栅极绝缘层以及所述数据线之间,所述半导体层的位置对应所述重合区域,且所述半导体层的面积大于所述重合区域,以通过所述半导体层来加强所述数据线与所述公共电压线之间的绝缘效果。
5.根据权利要求4所述的液晶显示面板,其特征在于:所述半导体层为一非晶硅层。
6.一种液晶显示面板的制造方法,其特征在于,所述制造方法包含:
提供一玻璃基板;
形成一第一金属层于所述玻璃基板上;
蚀刻所述第一金属层,以形成一薄膜晶体管的栅极以及一扫描线;
在所述第一薄膜晶体管的栅极以及所述扫描线上形成一绝缘层;
形成一半导体层于所述绝缘层上;
蚀刻所述半导体层,以形成所述薄膜晶体管的通道区域以及一第一区域;以及
形成一第二金属层,并蚀刻所述第二金属层,以形成所述薄膜晶体管的源极和漏极以及一数据线,其中所述数据线与所述扫描线重叠于一重合区域,所述重合区域与所述第一区域的位置对应,且所述第一区域的面积大于所述重合区域。
7.根据权利要求6所述的制造方法,其特征在于:所述半导体层为一非晶硅层。
8.根据权利要求8所述的液晶显示面板,其特征在于:所述第一区域的边缘与所述重合区域的边缘之间的距离大于1.5微米。
9.一种液晶显示面板的制造方法,其特征在于:所述方法包含: 
提供一玻璃基板;
形成一第一金属层于所述玻璃基板上;
蚀刻所述第一金属层,以形成一薄膜晶体管的栅极以及一公共电压线;
在所述第一薄膜晶体管的栅极以及所述扫描在线形成一绝缘层;
形成一半导体层于所述绝缘层上;
蚀刻所述半导体层,以形成所述薄膜晶体管的通道区域以及一第一区域;以及
形成一第二金属层,并蚀刻所述第二金属层,以形成所述薄膜晶体管的源极和漏极、以及一数据线;
其中所述数据线与所述公共电压线重叠于一重合区域,所述重合区域与所述第一区域的位置对应,且所述第一区域的面积大于所述重合区域。
10.根据权利要求9所述的制造方法,其特征在于:所述半导体层为一非晶硅层。 
CN2011103411539A 2011-11-02 2011-11-02 液晶显示面板及其制造方法 Pending CN102636926A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2011103411539A CN102636926A (zh) 2011-11-02 2011-11-02 液晶显示面板及其制造方法
US13/379,568 US20130106679A1 (en) 2011-11-02 2011-11-07 Lcd panel and method of manufacturing the same
PCT/CN2011/081845 WO2013063814A1 (zh) 2011-11-02 2011-11-07 液晶显示面板及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011103411539A CN102636926A (zh) 2011-11-02 2011-11-02 液晶显示面板及其制造方法

Publications (1)

Publication Number Publication Date
CN102636926A true CN102636926A (zh) 2012-08-15

Family

ID=46621366

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103411539A Pending CN102636926A (zh) 2011-11-02 2011-11-02 液晶显示面板及其制造方法

Country Status (2)

Country Link
CN (1) CN102636926A (zh)
WO (1) WO2013063814A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299972A (zh) * 2014-09-12 2015-01-21 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、液晶显示器
US20230178564A1 (en) * 2021-12-08 2023-06-08 Wuhan China Star Optoelectronics Technology Co., Ltd. Display panel and display device
WO2023102980A1 (zh) * 2021-12-08 2023-06-15 武汉华星光电技术有限公司 显示面板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05341313A (ja) * 1992-06-05 1993-12-24 Toshiba Corp アクティブマトリクス型液晶表示素子
CN102053435A (zh) * 2009-11-10 2011-05-11 乐金显示有限公司 液晶显示设备及其制造方法
CN102184966A (zh) * 2011-04-15 2011-09-14 福州华映视讯有限公司 晶体管数组基板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675582B2 (en) * 2004-12-03 2010-03-09 Au Optronics Corporation Stacked storage capacitor structure for a thin film transistor liquid crystal display
CN101140938B (zh) * 2006-09-07 2010-05-12 中华映管股份有限公司 薄膜晶体管阵列基板及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05341313A (ja) * 1992-06-05 1993-12-24 Toshiba Corp アクティブマトリクス型液晶表示素子
CN102053435A (zh) * 2009-11-10 2011-05-11 乐金显示有限公司 液晶显示设备及其制造方法
CN102184966A (zh) * 2011-04-15 2011-09-14 福州华映视讯有限公司 晶体管数组基板

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299972A (zh) * 2014-09-12 2015-01-21 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、液晶显示器
US20230178564A1 (en) * 2021-12-08 2023-06-08 Wuhan China Star Optoelectronics Technology Co., Ltd. Display panel and display device
WO2023102980A1 (zh) * 2021-12-08 2023-06-15 武汉华星光电技术有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
WO2013063814A1 (zh) 2013-05-10

Similar Documents

Publication Publication Date Title
CN104880871B (zh) 显示面板和显示装置
CN102135691B (zh) 阵列基板及其制造方法和液晶显示器
CN101401030B (zh) 有源矩阵基板、显示装置、电视接收机
CN105629612B (zh) 薄膜晶体管阵列基板及其制作方法
US8107029B2 (en) Thin film transistor substrate
CN202404339U (zh) 阵列基板及包括该阵列基板的显示装置
CN105470269A (zh) Tft阵列基板及其制作方法
CN106483728B (zh) 像素结构、阵列基板和显示装置
CN102403320A (zh) 阵列基板及其制作方法、液晶显示面板
CN106324924A (zh) 一种阵列基板及其制备方法、显示面板、显示装置
US8115215B2 (en) Array substrate and method for manufacturing the same
JP2010170057A (ja) 薄膜トランジスタアレイ基板及びその製造方法並びに液晶表示装置
TW200536125A (en) Display device
CN102566168A (zh) 阵列基板及其制作方法、液晶显示装置
JP2001343669A (ja) 液晶表示装置
WO2020107594A1 (zh) 显示面板及其修复方法
CN102508384A (zh) 平面显示面板及其修复方法
CN104460160B (zh) 像素结构
US20030227580A1 (en) Liquid crystal display device
US20100315569A1 (en) Pixel designs of improving the aperture ratio in an lcd
CN102088025A (zh) 薄膜晶体管基板及其制造方法
CN102364390A (zh) 液晶显示面板及形成液晶显示面板的方法
CN103488012A (zh) 像素结构、像素结构的制作方法以及有源元件阵列基板
CN102495504A (zh) 平面显示面板及其形成方法
CN106449652A (zh) 阵列基板及其制造方法、显示面板和显示设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120815