CN102237942A - Clock regulation method and device for multi-channel transmission platform (MCTP) - Google Patents
Clock regulation method and device for multi-channel transmission platform (MCTP) Download PDFInfo
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Abstract
The invention relates to a clock regulation method and a lock regulation device for a multi-channel transmission platform (MCTP). The clock regulation method comprises the following steps of: acquiring a line clock from a data frame transmitted by an upstream MCTP node in a network; writing data in the data frame into a first in first out (FIFO) cache by utilizing the line clock, and reading the data from the FIFO cache by utilizing a local clock; calculating a clock frequency difference between the line clock and the local clock according to the speed of writing the data into the FIFO cache and the speed of reading the data; determining the length of invalid data required to be added into or deleted from the data frame according to the clock frequency difference; and setting a local transmission data frame according to the length of the invalid data required to be added or deleted. By the technical scheme provided by the invention, the process of performing clock synchronization based on a reference clock by the MCTP node can be avoided, and the problems of limitations, caused by accumulated clock errors generated by the clock synchronization of each node, to the number of the nodes in the network can be solved; and the technical scheme is applicable and practical.
Description
Technical field
The present invention relates to the clock adjustment technology, particularly relate to the clock adjusting method and the device of Multi-Channel Transmission Platform (multichannel transmission platform).
Background technology
The clock adjustment technology is a kind of technology commonly used in the communication network, and clock synchronization is a kind of technology commonly used in the clock adjustment technology.
Clock synchronization also is " to clock ", and clock synchronization can be the clock alignment that is distributed in each node (synchronously promptly).Clock synchronization method the most intuitively is exactly a clock transportation, a concrete example: use a standard time clock (being reference clock) to make clock transportation, the clock of each node is all aimed at standard time clock; The example that another is concrete: clock transportation is at first aimed at the standard time clock of system, then, made the comparison of other hour hands in the system and clock transportation, thereby make standard time clock unified in other clocks in the system and the system synchronous.
The inventor finds in realizing process of the present invention: in the clock synchronization implementation procedure based on standard time clock, each node is consistent the clock of this node and the clock of a last node by utilizing Phase Lock Technique, like this, the clock of each node in the whole system can be consistent with reference clock.Yet,, may cause the paralysis of whole network if the reference clock in the network breaks down.In addition,, therefore, there is the frequency deviation of clock accumulation phenomenon in the network, makes that thus the number of nodes in the network can be restricted owing to can not there be certain deviation in the clock of each node with the clock of a last node is identical.
Because the defective that above-mentioned existing Clock Synchronization Technology exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, clock adjusting device in the hope of the MCTP of the clock adjusting method of founding a kind of new MCTP and new structure, can overcome the problem that existing Clock Synchronization Technology exists, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
The objective of the invention is to, overcome the defective that existing Clock Synchronization Technology exists, and provide the clock adjusting device of the MCTP of the clock adjusting method of a kind of MCTP and new structure, technical problem to be solved is, avoid taking place the phenomenon of the whole network paralysis that the reference clock fault causes, and avoid taking place the phenomenon that number of nodes in the network is subjected to the restriction of the frequency deviation of clock accumulation in the clock synchronization process, be very suitable for practicality.
Purpose of the present invention and solve its technical problem and can adopt following technical scheme to realize.
The clock adjusting method of a kind of MCTP that proposes according to the present invention, described method comprises: obtain line clock in the Frame that the upstream MCTP node from network sends; Utilize described line clock in the first in first out buffer, to write data in the described Frame, and utilize local clock reading of data from described first in first out buffer; Clock frequency according to the described line clock of speed calculation of the speed that writes data of described first in first out buffer and reading of data and described local clock is poor; Determine the length of the invalid data that described Frame should increase/delete according to described clock frequency difference; Length according to the invalid data of described increase/deletion is provided with the local Frame that sends.
Purpose of the present invention and solve its technical problem and can also be further achieved by the following technical measures.
Preferable, the clock adjusting method of aforesaid MCTP, wherein said network comprises: the gigabit ethernet ring network.
Preferable, the clock adjusting method of aforesaid MCTP, the wherein said data of utilizing described line clock to write in the described Frame in the first in first out buffer comprise: utilize described line clock to write valid data in the described Frame in described first in first out buffer.
Preferable, the clock adjusting method of aforesaid MCTP, the length of the valid data of each the MCTP node in the wherein said network in the Frame that its downstream MCTP node sends is identical, and the length of described valid data is set according to the clock accuracy of the local clock of the MCTP node of network permission.
Preferable, the clock adjusting method of aforesaid MCTP, the wherein said local clock reading of data from described first in first out buffer of utilizing comprises: after utilizing line clock to write the data of predetermined bite in the first in first out buffer, utilize local clock reading of data from described first in first out buffer.
Preferable, the clock adjusting method of aforesaid MCTP, wherein the clock accuracy of the local clock of the MCTP node that allows at described network is under the situation of 125M ± 50ppm, and the length of described valid data is 15256bit, and described predetermined bite comprises: 6 bytes.
Preferable, the clock adjusting method of aforesaid MCTP, wherein said method also comprises: writing in the first in first out buffer in the process of the data in the described Frame, when described first in first out buffer is read sky, in described first in first out buffer, insert invalid data, in described first in first out buffer, include the data of predetermined bite.
Purpose of the present invention and solve its technical problem and can adopt following technical scheme to realize.
The clock adjusting device of a kind of MCTP that proposes according to the present invention, comprising: the line clock acquisition module is used for obtaining line clock from the Frame that the upstream MCTP node of network sends; The first in first out buffer; Module for reading and writing is used for utilizing described line clock to write data in the described Frame to the first in first out buffer, and utilizes local clock reading of data from described first in first out buffer; Clock frequency differential mode piece, it is poor to be used for according to the clock frequency of the described line clock of speed calculation of the speed that writes data of described first in first out buffer and reading of data and described local clock; Invalid data length module is used for determining according to described clock frequency difference the length of the invalid data that described Frame should increase/delete; Frame is provided with module, is used for according to the length of the invalid data of described increase/deletion the local Frame that sends being set.
Preferable, the clock adjusting device of aforesaid MCTP, wherein said module for reading and writing comprises: write submodule, be used for utilizing described line clock to write data in the described Frame to the first in first out buffer; Read submodule, be used for after judging described first in first out buffer and including the data of predetermined bite, utilizing local clock reading of data from described first in first out buffer.
Preferable, the clock adjusting device of aforesaid MCTP, wherein said module for reading and writing also comprises: insert submodule, be used for writing in the process of the data in the described Frame to the first in first out buffer writing submodule, at described first in first out buffer by described when reading submodule and reading sky, in described first in first out buffer, insert invalid data, in described first in first out buffer, include the data of predetermined bite.
By technique scheme, the clock adjusting method of MCTP of the present invention and device have following advantage and beneficial effect at least: the present invention is poor by the clock frequency that writing rate and reading rate according to FIFO calculate between line clock and the local clock, and the local included invalid data in the Frame that sends is set according to this clock frequency difference, the MCTP node in the network can be sent the Frame that upstream MCTP node sends in its unit interval according to its local clock in its unit interval; Clock in the network of the present invention thus forms a kind of structure of distributed clock, not only avoided the MCTP node need carry out the process of clock synchronization with reference clock, also having avoided each node is to carry out the limited problem of number of nodes in the network that clocking error accumulation that clock synchronization produces caused, thereby the present invention can effectively improve the robustness of network, and the expandability of raising network, be very suitable for practicality.
In sum, the present invention is realizing technical obvious improvement being arranged, and has tangible good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the clock adjusting method schematic diagram of MCTP of the present invention;
Fig. 2 is the clock adjustment process schematic diagram of MCTP of the present invention;
Fig. 3 is a Frame schematic diagram of the present invention;
Fig. 4 is the clock adjusting method operational flowchart of MCTP of the present invention;
Fig. 5 is the clock adjusting device schematic diagram of MCTP of the present invention;
Fig. 6 is the clock adjusting device schematic diagram of MCTP of the present invention.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, clock adjusting method and its embodiment of device, structure, feature, step and the effect of the MCTP that foundation the present invention is proposed, describe in detail as after.
The clock adjusting method of embodiment one, MCTP.The flow process of this method as shown in Figure 1.
In the clock adjusting method schematic diagram of the MCTP of Fig. 1, obtain line clock in the Frame that S100, the upstream MCTP node from network send.
Concrete, the network among the present invention can be the gigabit ethernet ring network, promptly makes up the gigabit ethernet ring network that forms by a plurality of MCTP nodes.The present invention is applied to the gigabit ethernet ring network in the industrial control data transmission technique field.
Arbitrary MCTP node in the network after receiving the Frame that upstream MCTP node sends (for ease of describing, in following description, the MCTP node that receives the Frame that upstream MCTP node sends is called local MCTP node), can adopt existing clock extraction method to recover line clock (line clock is the local clock of upstream MCTP node) from this Frame, the present invention does not limit the specific implementation that local MCTP node obtains line clock.
In looped network of the present invention, arbitrary MCTP node all can comprise to the Frame that its downstream MCTP node sends: valid data and invalid data, and the length of the valid data of each MCTP node in the Frame that its downstream MCTP node sends is identical, but, the length of the invalid data in the Frame can be inequality, thereby the length of the Frame of the MCTP node transmission downstream of all the MCTP nodes in the network can be inequality.Each MCTP node can allow the clock accuracy of the local clock of MCTP node to set according to network to the length of the valid data of the Frame of its downstream MCTP node transmission.It is the local clock of the MCTP node that allows of network and the frequency deviation of clock maximum between the default clock that network allows the clock accuracy of the local clock of MCTP node.Thereby have certain precision (local clock and the frequency deviation of clock between the default clock that are the MCTP node are no more than this frequency deviation of clock maximum) as long as guarantee the local clock of each the MCTP node in the network, then the valid data in the Frame just can obtain correct transmission fully in network.A concrete example, under the situation of precision in 125M ± 50ppm scope of the clock frequency of the local clock of each MCTP node that network allowed, can preestablish the valid data length of each MCTP node in the Frame that its downstream MCTP node sends is 15256bit.
S110, utilize this line clock in FIFO (first in first out buffer), to write data in this Frame, and utilize local clock reading of data from FIFO.
Concrete, local MCTP node can utilize its line clock that recovers to write valid data in its Frame that receives in FIFO, and certainly, the valid data and the invalid data that write in FIFO in its Frame that receives also are feasible.For avoiding invalid read operation, local MCTP node can utilize local clock reading of data from FIFO again after utilizing its line clock that recovers to write the data of predetermined bite in FIFO.The local clock here is the local clock of local MCTP node.
Above-mentioned predetermined bite can be set according to the precision of the clock frequency of the local clock of each MCTP node that network allowed, concrete example: under the situation of precision in 125M ± 50ppm scope of the clock frequency of the local clock of each MCTP node that network allowed, frame length is that the invalid data that 1920 bytes then increase/delete is that 1 byte gets final product, and actually can the invalid data predetermined bite be set to 12 bytes.
Because local MCTP node is to utilize line clock to write valid data in FIFO, and utilize local clock from FIFO, to read valid data, after writing 6 byte valid data among the FIFO, begin to read, after running through this frame valid data, insert invalid data and in FIFO, write 6 byte valid data up to next frame, and the local clock of line clock and MCTP node and inequality, therefore, if under the situation of the reading speed of FIFO greater than the writing speed of FIFO, the invalid data that inserts is many, if instead under the situation of the reading speed of FIFO less than the writing speed of FIFO, the invalid data of insertion is just few.
S120, poor according to the clock frequency of the speed calculation line clock of the speed that writes data of FIFO and reading of data and local clock.
Concrete, local MCTP node can be according to the speed that writes data that data conditions obtains FIFO that writes of FIFO, and local MCTP node can obtain the speed of the sense data of FIFO according to the situation of the sense data of FIFO, thus, local MCTP node can be on the basis based on the speed of the speed that writes data of FIFO and sense data, and the clock frequency that adopts existing certain account form to calculate line clock and local clock is poor.
S130, determine the length of the invalid data that above-mentioned Frame should increase/delete, and the local Frame that sends is set according to the length of the invalid data of increase/deletion according to above-mentioned clock frequency difference.
Concrete, local MCTP node can determine to increase respective numbers according to the clock frequency difference on the basis of the Frame that receives invalid data still is the invalid data of minimizing respective numbers, to guarantee that Frame that upstream MCTP node sends is after local MCTP node place is through the processing of increases/deletion invalid data in its unit interval, can in its unit interval, be sent by local MCTP node equally, thereby make local MCTP node and upstream MCTP nodal clock synchronous.
The clock adjusting method of embodiment two, MCTP.Describe below in conjunction with accompanying drawing 2 to 4 pairs of present embodiments of accompanying drawing.
In the gigabit ethernet ring network, be under the situation of 8bit at data bit width, if the local clock of website A (being MCTP node A) is 125M, then website A can send 125 * 10 in its unit interval
6* 8=1000,000, the data of 000bit; If the local clock of website B (being the MCTP Node B) is 125M+10ppm, then website B can send 125 * 10 in its unit interval
6* (1+10 * 10
-6) * 8=1000,010, the data of 000bit; If the local clock of website C (being MCTP node C) is 125M-20ppm, then website C can send 125 * 10 in its unit interval
6* (1-20 * 10
-6) * 8=999,980, the data of 000bit.
Under above-mentioned application scenarios, 1000,000, the data of 000bit when process website B and website C return website A respectively, can be lost a part of data after website A sends out.For avoiding losing of valid data, carry a part of invalid data in the data that website A can send in its unit interval.The precision of the clock frequency that allows at network is that a concrete example of the clock adjustment in 125M ± 50ppm scope is: website A in the unit interval, send 1000,000, include 999 in the data of 000bit, 900, the valid data of 000bit and 100, the invalid data of 000bit, like this, after website B receives the data that website A sends, because the local clock of website B is faster than receive clock (being line clock) frequency, therefore, the data that website B sent in the unit interval are 999,900, the valid data of 000bit and 110, the invalid data of 000bit; After website C received the data that website B sends, because the local clock of website C is slower than receive clock frequency, therefore, the data that website C sent in the unit interval were 999,900, the valid data of 000bit and 80, the invalid data of 000bit; Thus, the data that website A receives are 999,900, the valid data of 000bit and 80, the invalid data of 000bit.
By above-mentioned concrete example as can be known: no matter the data that website A sends are through how many websites, as long as the local clock accuracy guarantee of each website is in 125M ± 50ppm scope, then the valid data that sent in its unit interval separately of each website can not change, thereby have guaranteed the correct transmission of valid data.
The clock adjustment process schematic diagram of the MCTP of Fig. 2 has illustrated website n uplink and downlink two processing procedures to its data that receive in the unit interval.At first, extract line clock n-1 the Frame (valid data and IGPn-1 invalid data of comprising predetermined length) that website n sends from website n-1; Afterwards, website n utilizes the significant figure in this line clock n-1 sends website n-1 in the unit interval the Frame to write among the FIFO, and this FIFO is an asynchronous FIFO; Website n utilizes its local clock reading of data from FIFO, and the data that website n will be read out carry out being sent to the downlink data bus after the descending time slot control and treatment, thereby the data that are read out are in website n internal transmission.Website n carries out the ascending time slot control and treatment to the data in the upstream data bus, afterwards, the Frame that website n buffer memory ascending time slot control and treatment produces is to continue to send this Frame downstream, include the valid data and the individual invalid data of IGPn (invalid data) of predetermined length in the data in buffer frame, the line clock n of this Frame is the local clock of website n.Above-mentioned IGPn and IGPn-1 can the (IGPn-1＞IGPn shown in Fig. 2 inequality, be the clock frequency that the clock frequency of the local clock of website n-1 is higher than the local clock of website n), thus, the frame length of the Frame that the frame length of the Frame that website n-1 sends and website n send is inequality, and the bandwidth that each bit carried in the Frame of the bandwidth that each bit carried in the Frame that website n-1 sends and website n transmission equates, and then has realized the clock synchronization of website n and website n-1.
Fig. 3 is the Frame schematic diagram that certain website among the present invention sends.The frame length of the Frame shown in the figure is that 15360bit, valid data are that 15256 bits, invalid data are 104bit.
Fig. 4 is that above-mentioned website n carries out MCTP clock adjusting method operational flowchart.In the drawings, at first judge whether to receive correct frame structure,, then initiate a reference frame structure if do not receive correct frame structure, if receive correct frame structure, then use time receiving clock (being line clock) to begin the valid data in the Frame are write among the FIFO; Afterwards, judge that whether the byte number that has write among the FIFO is greater than 6 bytes, if greater than 6 bytes, then begin to read and be divided into two-way after valid data among the FIFO form new frame structure with local clock, one the tunnel offers local cache and distributes to corresponding user's plate data by time slot, the local data that will upload are inserted by corresponding time slot in another road, and send into transmit port.
The clock adjusting device of embodiment three, MCTP.This device is arranged in the MCTP node, and Fig. 5 is this schematic representation of apparatus.
Device shown in Fig. 5 comprises: line clock acquisition module 1, first in first out buffer 2, module for reading and writing 3, clock frequency differential mode piece 4, invalid data length module 5, Frame are provided with module 6.
Line clock acquisition module 1 is mainly used in the Frame that the upstream MCTP node from network (as the gigabit ethernet ring network) sends and obtains line clock.
Line clock acquisition module 1 can adopt existing clock extraction method to recover line clock (line clock is the local clock of upstream MCTP node) from this Frame after local MCTP node receives the Frame that upstream MCTP node sends, and the present invention does not limit the specific implementation that line clock acquisition module 1 obtains line clock.
The Frame that the upstream MCTP node that local MCTP node receives sends comprises: valid data and invalid data.The length of valid data wherein can allow the clock accuracy of the local clock of MCTP node to set according to network.It is the local clock of the MCTP node that allows of network and the frequency deviation of clock maximum between the default clock that network allows the clock accuracy of the local clock of MCTP node.Thereby have certain precision as long as guarantee the local clock of each the MCTP node in the network, then the valid data in the Frame just can obtain correct transmission in network.
First in first out buffer 2 among the present invention is an asynchronous FIFO.
Module for reading and writing 3 is mainly used in and utilizes line clock to write data in the Frame in first in first out buffer 2, and utilizes local clock reading of data from first in first out buffer 2.
Concrete, the line clock that module for reading and writing 3 can utilize line clock acquisition module 1 to recover writes the valid data in its Frame that receives in FIFO, certainly, valid data and the invalid data that writes in FIFO in its Frame that receives also is feasible.For avoiding invalid read operation, module for reading and writing 3 can utilize local clock reading of data from FIFO again after utilizing its line clock that recovers to write the data of predetermined bite in FIFO.The local clock here is the local clock of module for reading and writing 3 place MCTP nodes.
Above-mentioned predetermined bite can be set according to the precision of the clock frequency of the local clock of each MCTP node that network allowed, concrete example: under the situation of precision in 125M ± 50ppm scope of the clock frequency of the local clock of each MCTP node that network allowed, frame length is that the invalid data that 1920 bytes then increase/delete is that 1 byte gets final product, and actually can the invalid data predetermined bite be set to 12 bytes.
Because module for reading and writing 3 is to utilize line clock to write valid data in first in first out buffer 2, and utilize local clock from first in first out buffer 2, to read valid data, after writing 6 byte valid data in the first in first out buffer 2, begin to read, after module for reading and writing 3 runs through this frame valid data, insert invalid data and in first in first out buffer 2, write 6 byte valid data up to next frame, and the local clock of line clock and MCTP node and inequality, therefore, if under the situation of the reading speed of first in first out buffer 2 greater than the writing speed of first in first out buffer 2, the invalid data that module for reading and writing 3 inserts is many, if instead under the situation of the reading speed of first in first out buffer 2 less than the writing speed of first in first out buffer 2, the invalid data that module for reading and writing 3 inserts is just few.
It is poor that clock frequency differential mode piece 4 is mainly used in according to the clock frequency of the speed calculation line clock of the speed that writes data of first in first out buffer 2 and reading of data and local clock.
Concrete, clock frequency differential mode piece 4 can be according to the speed that writes data that data conditions obtains FIFO that writes of FIFO, and clock frequency differential mode piece 4 can obtain the speed of the sense data of FIFO according to the situation of the sense data of FIFO, thus, clock frequency differential mode piece 4 can be on the basis based on the speed of the speed that writes data of FIFO and sense data, and the clock frequency that adopts existing certain account form to calculate line clock and local clock is poor.
Invalid data length module 5 is mainly used in the length of the invalid data that should increase/delete according to clock frequency difference specified data frame.
Concrete, invalid data length module 5 can determine to increase respective numbers according to the clock frequency difference on the basis of the Frame that receives invalid data still is the invalid data that reduces respective numbers, to guarantee that Frame that upstream MCTP node sends is after local MCTP node place is through the processing of increases/deletion invalid data in its unit interval, can in its unit interval, be sent by local MCTP node equally, thereby make local MCTP node and upstream MCTP nodal clock synchronous.
Frame is provided with the length that module 6 is mainly used in according to the invalid data of increase/deletion the local Frame that sends is set.
Above-mentioned module for reading and writing 3 can specifically comprise: write submodule 31, read submodule 32 and insert submodule 33.
Writing submodule 31 is mainly used in and utilizes line clock to write data in the Frame in the first in first out buffer.
After reading submodule 32 and being mainly used in the data that in judging the first in first out buffer, include predetermined bite, utilize local clock reading of data from described first in first out buffer.
Inserting submodule 33 is mainly used in and writes in the process of the data in the Frame in first in first out buffer 2 writing submodule 31, when first in first out buffer 2 is read submodule and is read sky, in first in first out buffer 2, insert invalid data, in first in first out buffer 2, include the data of predetermined bite.
Fig. 6 is the clock adjustment technology schematic diagram of device of MCTP of the present invention, the transceiving integrated module of optical fiber adopts the OCM3821 device to realize among the figure, gigabit ethernet ring network gateway end adopts the BCM5464 chip to realize, utilizes fpga chip EP2S3QF4184 and 125MHz crystal oscillator and has realized MCTP clock adjusting device function according to the Control Software of Fig. 3, Fig. 4, Fig. 5 establishment.
The above only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art are not in breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1. the clock adjusting method of a MCTP is characterized in that, this method comprises:
Obtain line clock in the Frame that upstream MCTP node from network sends;
Utilize described line clock in the first in first out buffer, to write data in the described Frame, and utilize local clock reading of data from described first in first out buffer;
Clock frequency according to the described line clock of speed calculation of the speed that writes data of described first in first out buffer and reading of data and described local clock is poor;
Determine the length of the invalid data that described Frame should increase/delete according to described clock frequency difference;
Length according to the invalid data of described increase/deletion is provided with the local Frame that sends.
2. the clock adjusting method of MCTP as claimed in claim 1 is characterized in that, described network comprises: the gigabit ethernet ring network.
3. the clock adjusting method of MCTP as claimed in claim 1 is characterized in that, the described data of utilizing described line clock to write in the described Frame in the first in first out buffer comprise:
Utilize described line clock in described first in first out buffer, to write valid data in the described Frame.
4. as the clock adjusting method of claim 1 or 2 or 3 described MCTP, it is characterized in that, the length of the valid data of each the MCTP node in the described network in the Frame that its downstream MCTP node sends is identical, and the length of described valid data is set according to the clock accuracy of the local clock of the MCTP node of network permission.
5. the clock adjusting method of MCTP as claimed in claim 4 is characterized in that, the described local clock reading of data from described first in first out buffer of utilizing comprises:
After utilizing described line clock in the first in first out buffer, to write the data of predetermined bite, utilize local clock reading of data from described first in first out buffer.
6. the clock adjusting method of MCTP as claimed in claim 5, it is characterized in that, the clock accuracy of the local clock of the MCTP node that allows at described network is under the situation of 125M ± 50ppm, and the length of described valid data is 15256bit, and described predetermined bite comprises: 6 bytes.
7. the clock adjusting method of MCTP as claimed in claim 5 is characterized in that, described method also comprises:
In the first in first out buffer, writing in the process of the data in the described Frame, when described first in first out buffer is read sky, in described first in first out buffer, insert invalid data, in described first in first out buffer, include the data of predetermined bite.
8. the clock adjusting device of a MCTP is characterized in that, comprising:
The line clock acquisition module is used for obtaining line clock from the Frame that the upstream MCTP node of network sends;
The first in first out buffer;
Module for reading and writing is used for utilizing described line clock to write data in the described Frame to the first in first out buffer, and utilizes local clock reading of data from described first in first out buffer;
Clock frequency differential mode piece, it is poor to be used for according to the clock frequency of the described line clock of speed calculation of the speed that writes data of described first in first out buffer and reading of data and described local clock;
Invalid data length module is used for determining according to described clock frequency difference the length of the invalid data that described Frame should increase/delete;
Frame is provided with module, is used for according to the length of the invalid data of described increase/deletion the local Frame that sends being set.
9. the clock adjusting device of MCTP as claimed in claim 8 is characterized in that, described module for reading and writing comprises:
Write submodule, be used for utilizing described line clock to write data in the described Frame to the first in first out buffer;
Read submodule, be used for after judging described first in first out buffer and including the data of predetermined bite, utilizing local clock reading of data from described first in first out buffer.
10. the clock adjusting device of MCTP as claimed in claim 9 is characterized in that, described module for reading and writing also comprises:
Insert submodule, be used for writing in the process of the data in the described Frame to the first in first out buffer writing submodule, at described first in first out buffer by described when reading submodule and reading sky, in described first in first out buffer, insert invalid data, in described first in first out buffer, include the data of predetermined bite.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108811050A (en) * | 2017-04-28 | 2018-11-13 | 联芯科技有限公司 | Wake-up synchronous method, device and the computer-readable medium of wireless terminal |
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| CN102237942B (en) | 2014-11-19 |
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