CN102237850B - Motor control circuit applied to multiple control modes - Google Patents
Motor control circuit applied to multiple control modes Download PDFInfo
- Publication number
- CN102237850B CN102237850B CN2010101657046A CN201010165704A CN102237850B CN 102237850 B CN102237850 B CN 102237850B CN 2010101657046 A CN2010101657046 A CN 2010101657046A CN 201010165704 A CN201010165704 A CN 201010165704A CN 102237850 B CN102237850 B CN 102237850B
- Authority
- CN
- China
- Prior art keywords
- coupled
- metal oxide
- oxide semiconductor
- type mos
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Control Of Direct Current Motors (AREA)
Abstract
The invention provides a motor control circuit applied to multiple control modes. The motor control circuit comprises a motor driving module, a logical control circuit, a plurality of switch modules and an operational amplifier, wherein the motor driving module is used for driving a motor; the logical control circuit is coupled to the motor driving module and is used for controlling an operation mode of the motor driving module; the plurality of switch modules are coupled between the motor driving module and the logical control circuit; the logical control circuit is used for controlling the operation mode of the motor driving module through the plurality of switch modules; and the operational amplifier is coupled between the plurality of switch modules and the motor driving module and is used for amplifying voltage or current output by the plurality of switch modules. According to the motor control circuit provided by the invention, an ordinary motor can perform operations including forward operation, reverse operation, closing operation and braking operation in a constant-current mode, a constant-voltage manner and a full-swing manner, a plurality of operational amplifiers are avoided by using a simple circuit design, and errors caused by the use of the plurality of operational amplifiers are avoided.
Description
Technical field
The present invention discloses a kind of motor control circuit, refers to a kind of motor control circuit that is applied to the various control pattern especially.
Background technology
General motor drive circuit need be realized the computing of motor under constant current mode, constant voltage mode and full swing (Full Swing) pattern simultaneously, but also therefore needs to use more operational amplifier (Operational Amplifier) and power MOS transistor (Power MOS).With the motor drive circuit of generally knowing, need four operational amplifiers and two groups of power MOS transistors at least, therefore in the design of circuit, understand more complicated, and cause the increase of motor drive circuit on chip area and cost.In addition, because general motor drive circuit uses the operational amplifier more than two, if on specification or ornaments position, difference occurs between the operational amplifier, when then motor operates under (Forward) pattern of advancing or under counter-rotating (Reverse) pattern also error can appear, can build up small running error and cause motor under forward operation and reverse turn operation, constantly to pull over when operating, and then significantly have influence on the performance of motor.In addition, because general motor drive circuit can not design at braking (Brake) pattern of motor, therefore motor can be braked rapidly.
Summary of the invention
The present invention discloses a kind of motor control circuit that is applied to the various control pattern.This motor control circuit comprises a motor driving module, a logic control circuit, a plurality of switch module and an operational amplifier.This motor driving module is in order to drive a motor.This logic control circuit is coupled to this motor driving module, and in order to control an operator scheme of this motor driving module.Described a plurality of switch module is coupled between this motor driving module and this logic control circuit.This logic control circuit is controlled the operator scheme of this motor driving module by described a plurality of switch modules.This operational amplifier is coupled between described a plurality of switch module and this motor driving module, and is used for amplifying voltage or the electric current of exporting from described a plurality of switch module.The operator scheme of this motor driving module comprises a constant current mode, certain voltage pattern and a full swing pattern.
The motor control circuit that is applied to the various control pattern of the present invention, described a plurality of switch module comprises: one first switch module, one first end of this first switch module is coupled to the certain voltage reference power source, one second end of this first switch module is coupled to a negative input end of this operational amplifier, and one the 3rd end of this first switch module is coupled to a voltage sampling end of this motor driving module; One second switch module, one first end of this second switch module is coupled to certain current reference power supply, one second end of this second switch module is coupled to a positive input terminal of this operational amplifier, one the 3rd end of this second switch module is coupled to one first drive end of this motor driving module, and one the 4th end of this second switch module is coupled to one second drive end of this motor driving module; One the 3rd switch module, one first end of the 3rd switch module is coupled to an output of this operational amplifier, one second end of the 3rd switch module is coupled to a first transistor control end of this motor driving module, and one the 3rd end of the 3rd switch module is coupled to a transistor seconds control end of this motor driving module; And one the 4th switch module, one first end of the 4th switch module is coupled to this output of this operational amplifier, one second end of the 4th switch module is coupled to one the 3rd transistor controls end of this motor driving module, and one the 3rd end of the 4th switch module is coupled to one the 4th transistor controls end of this motor driving module; Wherein one first end of this motor is coupled to this first drive end of this motor driving module, one second end of this motor is coupled to this second drive end of this motor driving module, and this motor driving module drives this motor with the potential difference between this first drive end and this second drive end; Wherein one first control end of this logic control circuit is coupled to this first transistor control end of this motor driving module, one second control end of this logic control circuit is coupled to this transistor seconds control end of this motor driving module, one the 3rd control end of this logic control circuit is coupled to the 3rd transistor controls end of this motor driving module, and one the 4th control end of this logic control circuit is coupled to the 4th transistor controls end of this motor driving module; Wherein one first switch terminals of this logic control circuit is coupled to a switch control end of this first switch module, one second switch end of this logic control circuit is coupled to a switch control end of this second switch module, one the 3rd switch terminals of this logic control circuit is coupled to a switch control end of the 3rd switch module, and one the 4th switch terminals of this logic control circuit is coupled to a switch control end of the 4th switch module.
The motor control circuit that is applied to the various control pattern of the present invention, one first end of a sample resistance are coupled to the 3rd end of this first switch module and this voltage sampling end of this motor driving module, and one second end ground connection of this sample resistance.
The motor control circuit that is applied to the various control pattern of the present invention, this motor driving module also comprises: one first P-type mos transistor, the transistorized grid of this first P-type mos is coupled to this first transistor control end of this motor driving module, the transistorized source electrode of this first P-type mos is coupled to a motor driven power supply, and this first P-type mos transistor drain is coupled to this first drive end of this motor driving module; One the one N type metal oxide semiconductor transistor, the transistorized grid of the one N type metal oxide semiconductor is coupled to this transistor seconds control end of this motor driving module, the one N type metal oxide semiconductor transistor drain is coupled to this first P-type mos transistor drain, and the transistorized source electrode of a N type metal oxide semiconductor is coupled to this voltage sampling end of this motor driving module; One second P-type mos transistor, the transistorized grid of this second P-type mos is coupled to the 3rd transistor controls end of this motor driving module, the transistorized source electrode of this second P-type mos is coupled to the transistorized source electrode of this first P-type mos, and this second P-type mos transistor drain is coupled to this second drive end of this motor driving module; And one the 2nd N type metal oxide semiconductor transistor, the transistorized grid of the 2nd N type metal oxide semiconductor is coupled to the 4th transistor controls end of this motor driving module, the 2nd N type metal oxide semiconductor transistor drain is coupled to this second P-type mos transistor drain, and the transistorized source electrode of the 2nd N type metal oxide semiconductor is coupled to the transistorized source electrode of a N type metal oxide semiconductor.
The motor control circuit that is applied to the various control pattern of the present invention, this first switch module comprises: one first switch, one first end of this first switch is coupled to this and decides the Voltage Reference power supply, and one second end of this first switch is coupled to this negative input end of this operational amplifier; And a second switch, one first end of this second switch is coupled to this second end of this first switch, and one second end of this second switch is coupled to this voltage sampling end of this motor driving module.
The motor control circuit that is applied to the various control pattern of the present invention, this second switch module comprises: one the 3rd switch, one first end of the 3rd switch is coupled to this and decides the current reference power supply, and one second end of the 3rd switch is coupled to this positive input terminal of this operational amplifier; One the 4th switch, one first end of the 4th switch is coupled to this second end of the 3rd switch, and one second end of the 4th switch is coupled to this first drive end of this motor driving module; And one the 5th switch, one first end of the 5th switch is coupled to this second end of the 3rd switch, and one second end of the 5th switch is coupled to this second drive end of this motor driving module.
The motor control circuit that is applied to the various control pattern of the present invention, the 3rd switch module comprises: one the 6th switch, one first end of the 6th switch is coupled to this output of this operational amplifier, and one second end of the 6th switch is coupled to this first transistor control end of this motor driving module; And minion pass, one first end that this minion is closed is coupled to this first end of the 6th switch, and one second end of this minion pass is coupled to this transistor seconds control end of this motor driving module.
The motor control circuit that is applied to the various control pattern of the present invention, the 4th switch module comprises: an octavo is closed, one first end that this octavo is closed is coupled to this output of this operational amplifier, and one second end of this octavo pass is coupled to the 3rd transistor controls end of this motor driving module; And one the 9th switch, one first end of the 9th switch is coupled to this first end that this octavo is closed, and one second end of the 9th switch is coupled to the 4th transistor controls end of this motor driving module.
The motor control circuit that is applied to the various control pattern of the present invention, also comprise: one first resistance, one first end of this first resistance is coupled to the 3rd end of this second switch module, and one second end of this first resistance is coupled to this first drive end of this motor driving module; One first electric capacity is parallel to this first resistance; And one second resistance, one first end of this second resistance is coupled to this first end of this first resistance, and one second end ground connection of this second resistance.
The motor control circuit that is applied to the various control pattern of the present invention, also comprise: one the 3rd resistance, one first end of the 3rd resistance is coupled to the 4th end of this second switch module, and one second end of the 3rd resistance is coupled to this second drive end of this motor driving module; One second electric capacity is parallel to the 3rd resistance; And one the 4th resistance, one first end of the 4th resistance is coupled to this first end of the 3rd resistance, and one second end ground connection of the 4th resistance.
The motor control circuit that is applied to the various control pattern of the present invention, this operational amplifier comprises: one first differential pair module, one first input end of this first differential pair module is coupled to this positive input terminal of this operational amplifier, and one second input of this first differential pair module is coupled to this negative input end of this operational amplifier; One second differential pair module, a first input end of this second differential pair module is coupled to this first input end of this first differential pair module, and one second input of this second differential pair module is coupled to this second input of this first differential pair module; One shift module; And a current mirror module, be used for the electric current that the electric current that produced according to this first differential pair module and this second differential pair module produced to regulate the electric current that this shift module produces; Wherein this first differential pair module and this second differential pair module are all powered with a common mode power supply, and this shift module is powered with a motor driven power supply.
The motor control circuit that is applied to the various control pattern of the present invention, this first differential pair module comprises: one first P-type mos transistor, the transistorized grid of this first P-type mos is coupled to this positive input terminal of this operational amplifier, and the transistorized source electrode of this first P-type mos is coupled to a bias current source that is powered by this common mode power supply; And one second P-type mos transistor, the transistorized grid of this second P-type mos is coupled to this negative input end of this operational amplifier, and the transistorized source electrode of this second P-type mos is coupled to the transistorized source electrode of this first P-type mos; This second differential pair module comprises: one the 3rd P-type mos transistor, the transistorized grid of the 3rd P-type mos is coupled to this negative input end of this operational amplifier, and the transistorized source electrode of the 3rd P-type mos is coupled to this bias current source that is powered by this common mode power supply; And one the 4th P-type mos transistor, the transistorized grid of the 4th P-type mos is coupled to this positive input terminal of this operational amplifier, and the transistorized source electrode of the 4th P-type mos is coupled to the transistorized source electrode of the 3rd P-type mos; This current mirror module comprises: one the one N type metal oxide semiconductor transistor, the one N type metal oxide semiconductor transistor drain is coupled to this common mode power supply, and the transistorized grid of a N type metal oxide semiconductor is coupled to a N type metal oxide semiconductor transistor drain; One the 2nd N type metal oxide semiconductor transistor, the 2nd N type metal oxide semiconductor transistor drain is coupled to the transistorized source electrode of a N type metal oxide semiconductor, and the transistorized grid of the 2nd N type metal oxide semiconductor is coupled to the 2nd N type metal oxide semiconductor transistor drain; One the 3rd N type metal oxide semiconductor transistor, the 3rd N type metal oxide semiconductor transistor drain is coupled to this second P-type mos transistor drain, the transistorized grid of the 3rd N type metal oxide semiconductor is coupled to the 3rd N type metal oxide semiconductor transistor drain, and the transistorized source electrode of the 3rd N type metal oxide semiconductor is coupled to this first P-type mos transistor drain and the transistorized source electrode of the 2nd N type metal oxide semiconductor; One the 4th N type metal oxide semiconductor transistor, the transistorized grid of the 4th N type metal oxide semiconductor is coupled to the transistorized grid of the 3rd N type metal oxide semiconductor, and the transistorized source electrode of the 4th N type metal oxide semiconductor is coupled to the transistorized source electrode of the 3rd N type metal oxide semiconductor; One the 5th N type metal oxide semiconductor transistor, the transistorized grid of the 5th N type metal oxide semiconductor is coupled to the transistorized grid of the 3rd N type metal oxide semiconductor, and the transistorized source electrode of the 5th N type metal oxide semiconductor is coupled to transistorized source electrode of the 3rd N type metal oxide semiconductor and the 3rd P-type mos transistor drain; One the 6th N type metal oxide semiconductor transistor, the 6th N type metal oxide semiconductor transistor drain is coupled to the 4th P-type mos transistor drain, the transistorized grid of the 6th N type metal oxide semiconductor is coupled to the 6th N type metal oxide semiconductor transistor drain, and the transistorized source electrode of the 6th N type metal oxide semiconductor is coupled to the transistorized source electrode of the 3rd N type metal oxide semiconductor; One the 7th N type metal oxide semiconductor transistor, the transistorized grid of the 7th N type metal oxide semiconductor is coupled to the 6th N type metal oxide semiconductor transistor drain, and the transistorized source electrode of the 7th N type metal oxide semiconductor is coupled to the transistorized source electrode of the 6th N type metal oxide semiconductor; And one the 8th N type metal oxide semiconductor transistor, the transistorized grid of the 8th N type metal oxide semiconductor is coupled to the transistorized grid of a N type metal oxide semiconductor, and the transistorized source electrode of the 8th N type metal oxide semiconductor is coupled to the 7th N type metal oxide semiconductor transistor drain; This shift module comprises: one the 5th P-type mos transistor, the 5th P-type mos transistor drain is coupled to the 4th N type metal oxide semiconductor transistor drain, the transistorized grid of the 5th P-type mos is coupled to the 5th P-type mos transistor drain, and the transistorized source electrode of the 5th P-type mos is coupled to this motor driven power supply; One the 6th P-type mos transistor, the transistorized source electrode of the 6th P-type mos is coupled to the transistorized source electrode of the 5th P-type mos, and the transistorized grid of the 6th P-type mos is coupled to the 5th N type metal oxide semiconductor transistor drain; One the 7th P-type mos transistor, the transistorized source electrode of the 7th P-type mos is coupled to the transistorized source electrode of the 6th P-type mos, and the transistorized grid of the 7th P-type mos is coupled to the transistorized grid of the 6th P-type mos; One the 8th P-type mos transistor, the transistorized source electrode of the 8th P-type mos is coupled to the 6th P-type mos transistor drain, the transistorized grid of the 8th P-type mos is coupled to the transistorized grid of the 5th P-type mos, and the 8th P-type mos transistor drain is coupled to the 5th N type metal oxide semiconductor transistor drain; And one the 9th P-type mos transistor, the transistorized source electrode of the 9th P-type mos is coupled to the 7th P-type mos transistor drain, the transistorized grid of the 9th P-type mos is coupled to the transistorized grid of the 8th P-type mos, and the 9th P-type mos transistor drain is coupled to the 8th N type metal oxide semiconductor transistor drain.
The motor control circuit that is applied to the various control pattern of the present invention, the transistorized source electrode of the 2nd N type metal oxide semiconductor are coupled to transistorized base stage of a N type metal oxide semiconductor and the transistorized base stage of the 2nd N type metal oxide semiconductor; The transistorized source electrode of the 3rd N type metal oxide semiconductor is coupled to the transistorized base stage of the 3rd N type metal oxide semiconductor; The transistorized source electrode of the 4th N type metal oxide semiconductor is coupled to the transistorized base stage of the 4th N type metal oxide semiconductor; The transistorized source electrode of the 5th N type metal oxide semiconductor is coupled to the transistorized base stage of the 5th N type metal oxide semiconductor; The transistorized source electrode of the 6th N type metal oxide semiconductor is coupled to the transistorized base stage of the 6th N type metal oxide semiconductor; The transistorized source electrode of the 7th N type metal oxide semiconductor is coupled to transistorized base stage of the 7th N type metal oxide semiconductor and the transistorized base stage of the 8th N type metal oxide semiconductor; The transistorized source electrode of this first P-type mos is coupled to transistorized base stage of this first P-type mos and the transistorized base stage of this second P-type mos; The transistorized source electrode of the 3rd P-type mos is coupled to transistorized base stage of the 3rd P-type mos and the transistorized base stage of the 4th P-type mos; The transistorized source electrode of the 5th P-type mos is coupled to the transistorized base stage of the 5th P-type mos; The transistorized source electrode of the 6th P-type mos is coupled to the transistorized base stage of the 6th P-type mos; The transistorized source electrode of the 7th P-type mos is coupled to the transistorized base stage of the 7th P-type mos; The transistorized source electrode of the 8th P-type mos is coupled to the transistorized base stage of the 8th P-type mos; The transistorized source electrode of the 9th P-type mos is coupled to the transistorized base stage of the 9th P-type mos.
The motor control circuit that is applied to the various control pattern of the present invention, the transistorized source ground of the 3rd N type metal oxide semiconductor.
Motor drive circuit of the present invention except can so that general motor can comprise the running of forward operation, reverse turn operation, shutoff operation and brake operating carrying out under constant current mode, constant voltage mode and the full swing pattern, also avoid using a plurality of operational amplifiers with simple circuit design, and the error that is produced when avoiding using a plurality of operational amplifier.
Description of drawings
Fig. 1 is the schematic diagram according to the disclosed motor drive circuit of one embodiment of the invention.
Fig. 2 is the detailed circuit schematic of disclosed according to a preferred embodiment of the present invention motor drive circuit shown in Figure 1.
Fig. 3 is the detailed maps according to the disclosed operational amplifier shown in Figure 2 of one embodiment of the invention.
Being simply described as follows of symbol in the accompanying drawing:
100: motor drive circuit
Logic_Ctrl: logic control circuit
SW1, SW2, SW3, SW4: switch module
OP_AMP: operational amplifier
Motor_DV: motor driving module
R1, R2, R3, R4: resistance
C1, C2: electric capacity
VM: motor driven power supply
VCC: common mode power supply
M: motor
S0, S1, S2, S3, S4, S5, S6, S7, S8, SR1, SR2: switch
MPA, MPB, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9:P type metal oxide semiconductor transistor
MNA, MNB, MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8:N type metal oxide semiconductor transistor
Ibias1, Ibias2, Ibias3: bias current source
T1, T2: differential pair module
T3: current mirror module
T4: shift module.
Embodiment
The present invention discloses a kind of motor drive circuit that is applied to the various control pattern.The disclosed motor drive circuit of the present invention except general motor at forward operation, the reverse turn operation carried out separately under constant current mode, constant voltage mode and the full swing pattern and close (Off) operation, also can realize brake operating, therefore can be used for driving the motor that comprises as d.c. motor, stepper motor (Stepping Motor) or voice coil motor types such as (Voice Coil Motor).Therefore the disclosed motor drive circuit of the present invention mainly uses single operational amplifier and a plurality of switch to implement, and can avoid in the prior art comparatively complex circuit design, and produces the problem of error when preventing to use a plurality of operational amplifier.
See also Fig. 1, it is the schematic diagram according to the disclosed motor drive circuit 100 of one embodiment of the invention.As shown in Figure 1, motor drive circuit 100 comprises a logic control circuit Logic_Ctrl, an operational amplifier OP_AMP, a motor driving module Motor_DV, one first switch module SW1, a second switch module SW2, one the 3rd switch module SW3 and one the 4th switch module SW4.Motor drive circuit 100 also comprises one first resistance R 1, one second resistance R 2, one the 3rd resistance R 3, one the 4th resistance R 4, one first capacitor C 1 and one second capacitor C 2.Motor drive circuit 100 is mainly used to an included motor M in the drive motor module Motor_DV.Motor drive circuit 100 is external in a sample resistance Rsense and corresponding two switch S R1, SR2, so that a sampling voltage to be provided under the constant current mode of motor drive circuit 100.
The first switch module SW1, the one first end SW11 is coupled to certain voltage reference power source VrefV.The one second end SW12 of the first switch module SW1 is coupled to the negative input end INN of operational amplifier OP_AMP.The one first end SW21 of second switch module SW2 is coupled to certain current reference power supply VrefC.The one second end SW22 of second switch module SW2 is coupled to the positive input terminal INP of operational amplifier OP_AMP.One the 3rd end SW23 of second switch module SW2 is coupled to the one first drive end D1 of motor driving module Motor_DV by resistance R 1.One the 4th end SW24 of second switch module SW2 is coupled to the one second drive end D2 of motor driving module Motor_DV by resistance R 3.The one first end SW31 of the 3rd switch module SW3 is coupled to the output OUT of operational amplifier OP_AMP.The one second end SW32 of the 3rd switch module SW3 is coupled to the first transistor control end G1 of motor driving module Motor_DV.One the 3rd end SW33 of the 3rd switch module SW3 is coupled to the transistor seconds control end G2 of motor driving module Motor_DV.The one first end SW41 of the 4th switch module SW4 is coupled to the output OUT of operational amplifier OP_AMP.The one second end SW42 of the 4th switch module SW4 is coupled to one the 3rd transistor controls end G3 of motor driving module Motor_DV.One the 3rd end SW43 of the 4th switch module SW4 is coupled to one the 4th transistor controls end G4 of motor driving module Motor_DV.One first end of sample resistance Rsense is coupled to one the 3rd end SW13 of the first switch module SW1 and the voltage sampling end RNF of motor driving module Motor_DV.The one second end ground connection of sample resistance Rsense.
One first end of motor M is coupled to the first drive end D1 of motor driving module Motor_DV.One second end of motor M is coupled to the second drive end D2 of motor driving module Motor_DV.Motor driving module Motor_DV comes CD-ROM drive motor M with the potential difference between the first drive end D1 and the second drive end D2.The one first control end DrvPA of logic control circuit Logic_Ctrl is coupled to the first transistor control end G1 of motor driving module Motor_DV.The one second control end DrvNA of logic control circuit Logic_Ctrl is coupled to the transistor seconds control end G2 of motor driving module Motor_DV.One the 3rd control end DrvPB of logic control circuit Logic_Ctrl is coupled to one the 3rd transistor controls end G3 of motor driving module Motor_DV.One the 4th control end DrvNB of logic control circuit Logic_Ctrl is coupled to one the 4th transistor controls end G4 of motor driving module Motor_DV.The one first switch terminals E1 of logic control circuit Logic_Ctrl is coupled to the switch control end A1 of the first switch module SW1.The second switch end E2 of logic control circuit Logic_Ctrl is coupled to the switch control end A2 of second switch module SW2.One the 3rd switch terminals E3 of logic control circuit Logic_Ctrl is coupled to the switch control end A3 of the 3rd switch module SW3.One the 4th switch terminals E4 of logic control circuit Logic_Ctrl is coupled to the switch control end A4 of the 4th switch module SW4.
First end of resistance R 1 is coupled to the 3rd end SW23 of second switch module SW2, and second end of resistance R 1 is coupled to the first drive end D1 of motor driving module Motor_DV.Capacitor C 1 is parallel to resistance R 1.One first end of resistance R 2 is coupled to this first end of resistance R 1, and one second end ground connection of resistance R 2.First end of resistance R 3 is coupled to the 4th end SW24 of second switch module SW2, and second end of resistance R 3 is coupled to the second drive end D2 of motor driving module Motor_DV.Capacitor C 2 is parallel to resistance R 3.One first end of resistance R 4 is coupled to this first end of resistance R 3, and one second end ground connection of resistance R 4.
In Fig. 1, operational amplifier OP_AMP is used for the differential signal between positive input terminal INP and the negative input end INN being amplified comprising under constant current mode or the constant voltage mode isotype, the voltage or the size of current that are received with control motor driving module Motor_DV.Logic control circuit Logic_Ctrl can be in the different control signal of following generation of constant current mode, constant voltage mode and the full swing pattern of motor, open separately or off switch module SW1, SW2, SW3, SW4 with the switching signal of being sent by switch terminals E1, E2, E3, E4, and control the transistorized unlatching that comprises among the motor driving module Motor_DV or close by the control signal that control end DrvPA, DrvNA, DrvPB, DrvNB are sent separately.
In order further clearly to explain the running of motor drive circuit shown in Figure 1 100, in Fig. 2, come further to disclose motor drive circuit 100 shown in Figure 1 according to a preferred embodiment of the present invention, but for simplicity of illustration, so the module end points that had illustrated in the partial graph 1 is omitted.
See also Fig. 2, its by according to a preferred embodiment of the present invention the detailed circuit schematic of exposure motor drive circuit 100 shown in Figure 1.As shown in Figure 2, motor driving module Motor_DV comprises one first P-type mos transistor MPA, one second P-type mos transistor MPB, one the one N type metal oxide semiconductor transistor MNA, one the 2nd N type metal oxide semiconductor transistor MNB.The grid of the first P-type mos transistor MPA is coupled to the first transistor control end G1 of motor driving module Motor_DV.The source electrode of the first P-type mos transistor MPA is coupled to a motor driven power supply VM.The drain electrode of the first P-type mos transistor MPA is coupled to the first drive end D1 of motor driving module Motor_DV.The grid of the one N type metal oxide semiconductor transistor MNA is coupled to the transistor seconds control end G2 of motor driving module Motor_DV.The drain electrode of the one N type metal oxide semiconductor transistor MNA is coupled to the drain electrode of the first P-type mos transistor MPA.The source electrode of the one N type metal oxide semiconductor transistor MNA is coupled to the voltage sampling end RNF of motor driving module Motor_DV.The grid of the second P-type mos transistor MPB is coupled to the 3rd transistor controls end G3 of motor driving module Motor_DV.The source electrode of the second P-type mos transistor MPB is coupled to the source electrode of the first P-type mos transistor MPA.The drain electrode of the second P-type mos transistor MPB is coupled to the second drive end D2 of motor driving module Motor_DV.The grid of the 2nd N type metal oxide semiconductor transistor MNB is coupled to the 4th transistor controls end G4 of motor driving module Motor_DV.The drain electrode of the 2nd N type metal oxide semiconductor transistor MNB is coupled to the drain electrode of the second P-type mos transistor MPB.The source electrode of the 2nd N type metal oxide semiconductor transistor MNB is coupled to the source electrode of a N type metal oxide semiconductor transistor MNA.
The first switch module SW1 comprises one first switch S 1 and a second switch S4.One first end of first switch S 1 is coupled to decides Voltage Reference power supply VrefV.One second end of first switch S 1 is coupled to the negative input end INN of operational amplifier OP_AMP, and one first end of second switch S4 is coupled to this second end of first switch S 1, and one second end of second switch S4 is coupled to the voltage sampling end RNF of motor driving module Motor_DV.Second switch module SW2 comprises one the 3rd switch S 0, one the 4th switch S 5, one the 5th switch S 2.One first end of the 3rd switch S 0 is coupled to decides current reference power supply VrefC, and one second end of the 3rd switch S 0 is coupled to the positive input terminal INP of operational amplifier OP_AMP.One first end of the 4th switch S 5 is coupled to second end of the 3rd switch S 0, and one second end of the 4th switch S 5 is coupled to the first drive end D1 of motor driving module Motor_DV by resistance R 1.One first end of the 5th switch S 2 is coupled to second end of the 3rd switch S 0, and one second end of the 5th switch S 2 is coupled to the second drive end D2 of motor driving module Motor_DV by resistance R 3.The 3rd switch module SW3 comprises one the 6th switch S 3 and minion pass S6.One first end of the 6th switch S 3 is coupled to the output OUT of operational amplifier OP_AMP, and one second end of the 6th switch S 3 is coupled to the first transistor control end G1 of motor driving module Motor_DV.One first end of minion pass S6 is coupled to first end of the 6th switch S 3, and one second end of minion pass S6 is coupled to the transistor seconds control end G2 of motor driving module Motor_DV.The 4th switch module SW4 comprises octavo pass S7 and one the 9th switch S 8.One first end of octavo pass S7 is coupled to the output OUT of operational amplifier OP_AMP, and one second end of octavo pass S7 is coupled to the 3rd transistor controls end G3 of motor driving module Motor_DV.One first end of the 9th switch S 8 is coupled to this first end that octavo is closed S7, and one second end of the 9th switch S 8 is coupled to the 4th transistor controls end G4 of motor driving module Motor_DV.
The type of drive of motor drive circuit 100 shown in Figure 2 divides the forward operation, reverse turn operation, shutoff operation and the brake operating that comprise separately under constant current mode, constant voltage mode, the full swing pattern to be described below.
(1) constant current mode:
Under constant current mode, switch S R1 can switch to open circuit, and switch S R2 can switch to short circuit, and making takes a sample at voltage sampling end RNF will obtain the potential difference of sample resistance Rsense, that is a sampling voltage.
(1-a) forward operation: logic control circuit Logic_Ctrl is with switch S 0, S4, S8 switches to short circuit (Short-circuited), with switch S 1, S2, S3, S5, S6, S7 switches to open circuit (Open-circuited), control end DrvPA and DrvNA are switched to electronegative potential output, control end DrvPB is switched to high potential output, and control end DrvNB is set to floating, make P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB in linear zone work, and make P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA in cut-off region work.Thus, electric current will be by motor driven power supply VM flow through P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB, that is flows to node OUTB by node OUTA shown in Figure 2, and promotes motor M.
(1-b) reverse turn operation: logic control circuit Logic_Ctrl is with switch S 0, S4, S6 switches to short circuit, with switch S 1, S2, S3, S5, S7, S8 switches to open circuit, control end DrvPB and DrvNB are switched to electronegative potential output, control end DrvPA is switched to high potential output, and control end DrvNA is set to floating, make P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA in linear zone work, and make P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB in cut-off region work.Thus, electric current will be by motor driven power supply VM flow through P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA, that is flows to node OUTA by node OUTB, and promotes motor M.
(1-c) shutoff operation: logic control circuit Logic_Ctrl switches to switch S 0, S1, S2, S3, S4, S5, S6, S7, S8 open circuit totally, control end DrvPA and DrvPB is switched to high potential output, control end DrvNA and DrvNB are switched to electronegative potential output, make P-type mos transistor MPA and MPB, N type metal oxide semiconductor transistor MNA and MNB all close.Thus, will not have electric current process motor M and CD-ROM drive motor M.
(1-d) brake operating: logic control circuit Logic_Ctrl switches to open circuit with switch S 0, S1, S2, S3, S4, S5, S6, S7, S8 totally, control end DrvPA, DrvPB, DrvNA, DrvNB are all switched to high potential output, make P-type mos transistor MPA and MPB all close, and make N type metal oxide semiconductor transistor MNA and MNB all open.Thus, the current potential of node OUTA and OUTB all can be pulled to electronegative potential in moment, and makes motor M shut down fast.
(2) constant voltage mode:
Under constant voltage mode, switch S R1 can switch to short circuit, and switch S R2 can switch to open circuit, and makes voltage sampling end RNF ground connection.
(2-a) forward operation: logic control circuit Logic_Ctrl is with switch S 1, S3, S5 switches to short circuit, with switch S 0, S2, S4, S6, S7, S8 switches to open circuit, control end DrvNA is switched to electronegative potential output, control end DrvPB and DrvNB are switched to high potential output, and control end DrvPA is set to floating, make P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB in linear zone work, and make P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA in cut-off region work.Thus, decide the current potential that Voltage Reference power supply VrefV will come control output end OUTA by common voltage stabilizing of P-type mos transistor MPA and resistance R 1, R2 and capacitor C 1 and filter action, make that electric current will be by motor driven power supply VM flow through in regular turn P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB, meaning promptly flows to node OUTB by node OUTA, and promotes motor M.
(2-b) reverse turn operation: logic control circuit Logic_Ctrl is with switch S 1, S2, S7 switches to short circuit, with switch S 0, S3, S4, S5, S6, S8 switches to open circuit, control end DrvNB is switched to electronegative potential output, control end DrvNA and DrvPA are switched to high potential output, and control end DrvPB is set to floating, make P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA in linear zone work, and make P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB in cut-off region work.Thus, decide the current potential that Voltage Reference power supply VrefV will come control output end OUTB by common voltage stabilizing of P-type mos transistor MPB and resistance R 3, R4 and capacitor C 2 and filter action, make that electric current will be by motor driven power supply VM flow through P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA, that is flow to node OUTA by node OUTB, and promote motor M.
(2-c) shutoff operation: this part is no longer added to give unnecessary details with (1-c) described shutoff operation.
(2-d) brake operating: this part is no longer added to give unnecessary details with (1-d) described brake operating.
(3) full swing pattern:
Under the full swing pattern, switch S R1 can switch to short circuit, and switch S R2 can switch to open circuit, and makes voltage sampling end RNF ground connection.
(3-a) forward operation: logic control circuit Logic_Ctrl is with switch S 0, S1, S2, S3, S4, S5, S6, S7 all switches to open circuit, control end DrvPA and DrvNA are switched to electronegative potential output, and control end DrvNB and DrvPB switched to high potential output, make P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB the direct power supply of motor driven power supply VM and and node OUTA between produce under the situation of big voltage difference and make P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB directly in saturation region operation, and P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA are in cut-off region work.Thus, electric current will be by motor driven power supply VM flow through P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB, that is flows to node OUTB by node OUTA, and promotes motor M.
(3-b) reverse turn operation: logic control circuit Logic_Ctrl is with switch S 0, S1, S2, S3, S4, S5, S6, S7 all switches to open circuit, control end DrvNB and DrvPB are switched to electronegative potential output, and control end DrvPA and DrvNA switched to high potential output, make P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA the direct power supply of motor driven power supply VM and and node OUTB between produce under the situation of big voltage difference and make P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA directly in saturation region operation, and P-type mos transistor MPA and N type metal oxide semiconductor transistor MNB are in cut-off region work.Thus, electric current will be by motor driven power supply VM flow through P-type mos transistor MPB and N type metal oxide semiconductor transistor MNA, that is flows to node OUTA by node OUTB, and promotes motor M.
(3-c) shutoff operation: this part is no longer added to give unnecessary details with (1-c) described shutoff operation.
(3-d) brake operating: this part is no longer added to give unnecessary details with (1-d) described brake operating.
See also Fig. 3, it is for disclosing the detailed maps of operational amplifier OP_AMP shown in Figure 2 according to one embodiment of the invention.As shown in Figure 3, operational amplifier OP_AMP comprises one first differential pair module T1, one second differential pair module T2, a shift module T4 and a current mirror module T3.The first differential pair module T1, one first input end is coupled to the positive input terminal INP of operational amplifier OP_AMP, and one second input of the first differential pair module T1 is coupled to the negative input end INN of operational amplifier OP_AMP.The first input end of the second differential pair module T2 is coupled to this first input end of the first differential pair module T1, and one second input of the second differential pair module T2 is coupled to this second input of the first differential pair module T1.Current mirror module T3 is used for the electric current that the electric current that produced according to the first differential pair module T1 and the second differential pair module T2 produced and regulates the electric current that shift module T4 is produced, with the voltage of the electric current that produces corresponding to shift module T4 in the output OUT of the OP_AMP of operational amplifier shown in Fig. 3 output.The first differential pair module T1 and the second differential pair module T2 are all with common mode power supply VCC power supply, and common mode power supply VCC is provided by logic control circuit Logic_Ctrl.Shift module T4 powers with motor driven power supply VM.
The first differential pair module T1 comprises one first P-type mos transistor MP1 and one second P-type mos transistor MP2.The grid of the first P-type mos transistor MP1 is coupled to the positive input terminal INP of operational amplifier OP_AMP.The source electrode of the first P-type mos transistor MP1 is coupled to a bias current source Ibias2 who is powered by common mode power supply VCC.The grid of the second P-type mos transistor MP2 is coupled to the negative input end INN of operational amplifier OP_AMP, and the source electrode of the second P-type mos transistor MP2 is coupled to the source electrode of the first P-type mos transistor MP1.The second differential pair module T2 comprises one the 3rd P-type mos transistor MP3 and one the 4th P-type mos transistor MP4.The grid of the 3rd P-type mos transistor MP3 is coupled to the negative input end INN of operational amplifier OP_AMP, and the source electrode of the 3rd P-type mos transistor MP3 is coupled to a bias current source Ibias3 who is powered by common mode power supply VCC.The grid of the 4th P-type mos transistor MP4 is coupled to the positive input terminal INP of operational amplifier OP_AMP.The source electrode of the 4th P-type mos transistor MP4 is coupled to the source electrode of the 3rd P-type mos transistor MP3.
Current mirror module T3 comprises one the one N type metal oxide semiconductor transistor MN1, one the 2nd N type metal oxide semiconductor transistor MN2, one the 3rd N type metal oxide semiconductor transistor MN3, one the 4th N type metal oxide semiconductor transistor MN4, one the 5th N type metal oxide semiconductor transistor MN5, one the 6th N type metal oxide semiconductor transistor MN6, one the 7th N type metal oxide semiconductor transistor MN7 and one the 8th N type metal oxide semiconductor transistor MN8.The drain electrode of the one N type metal oxide semiconductor transistor MN1 is coupled to a bias current source Ibias1 who is powered by common mode power supply VCC, and the grid of a N type metal oxide semiconductor transistor MN1 is coupled to the drain electrode of a N type metal oxide semiconductor transistor MN1.The drain electrode of the 2nd N type metal oxide semiconductor transistor MN2 is coupled to the source electrode of a N type metal oxide semiconductor transistor MN1, and the grid of the 2nd N type metal oxide semiconductor transistor MN2 is coupled to the drain electrode of the 2nd N type metal oxide semiconductor transistor MN2.The drain electrode of the 3rd N type metal oxide semiconductor transistor MN3 is coupled to the drain electrode of the second P-type mos transistor MP2.The grid of the 3rd N type metal oxide semiconductor transistor MN3 is coupled to the drain electrode of the 3rd N type metal oxide semiconductor transistor MN3.The source electrode of the 3rd N type metal oxide semiconductor transistor MN3 is coupled to the drain electrode of the first P-type mos transistor MP1 and the source electrode of the 2nd N type metal oxide semiconductor transistor MN2, and equal ground connection.The grid of the 4th N type metal oxide semiconductor transistor MN4 is coupled to the grid of the 3rd N type metal oxide semiconductor transistor MN3.The source electrode of the 4th N type metal oxide semiconductor transistor MN4 is coupled to source electrode and the ground connection of the 3rd N type metal oxide semiconductor transistor MN3.The grid of the 5th N type metal oxide semiconductor transistor MN5 is coupled to the grid of the 3rd N type metal oxide semiconductor transistor MN3.The source electrode of the 5th N type metal oxide semiconductor transistor MN5 is coupled to drain electrode and the ground connection of source electrode and the 3rd P-type mos transistor MP3 of the 3rd N type metal oxide semiconductor transistor MN3.The drain electrode of the 6th N type metal oxide semiconductor transistor MN6 is coupled to the drain electrode of the 4th P-type mos transistor MP4.The grid of the 6th N type metal oxide semiconductor transistor MN6 is coupled to the drain electrode of the 6th N type metal oxide semiconductor transistor MN6.The source electrode of the 6th N type metal oxide semiconductor transistor MN6 is coupled to source electrode and the ground connection of the 3rd N type metal oxide semiconductor transistor MN3.The grid of the 7th N type metal oxide semiconductor transistor MN7 is coupled to the drain electrode of the 6th N type metal oxide semiconductor transistor MN6.The source electrode of the 7th N type metal oxide semiconductor transistor MN7 is coupled to source electrode and the ground connection of the 6th N type metal oxide semiconductor transistor MN6.The grid of the 8th N type metal oxide semiconductor transistor MN8 is coupled to the grid of a N type metal oxide semiconductor transistor MN1.The source electrode of the 8th N type metal oxide semiconductor transistor MN8 is coupled to the drain electrode of the 7th N type metal oxide semiconductor transistor MN7.
Shift module T4 comprises one the 5th P-type mos transistor MP5, one the 6th P-type mos transistor MP6, one the 7th P-type mos transistor MP7, one the 8th P-type mos transistor MP8 and one the 9th P-type mos transistor MP9.The drain electrode of the 5th P-type mos transistor MP5 is coupled to the drain electrode of the 4th N type metal oxide semiconductor transistor MN4.The grid of the 5th P-type mos transistor MP5 is coupled to the drain electrode of the 5th P-type mos transistor MP5.The source electrode of the 5th P-type mos transistor MP5 is coupled to motor driven power supply VM.The source electrode of the 6th P-type mos transistor MP6 is coupled to the source electrode of the 5th P-type mos transistor MP5.The grid of the 6th P-type mos transistor MP6 is coupled to the drain electrode of the 5th N type metal oxide semiconductor transistor MN5.The source electrode of the 7th P-type mos transistor MP7 is coupled to the source electrode of the 6th P-type mos transistor MP6.The grid of the 7th P-type mos transistor MP7 is coupled to the grid of the 6th P-type mos transistor MP6.The source electrode of the 8th P-type mos transistor MP8 is coupled to the drain electrode of the 6th P-type mos transistor MP6.The grid of the 8th P-type mos transistor MP8 is coupled to the grid of the 5th P-type mos transistor MP5.The drain electrode of the 8th P-type mos transistor MP8 is coupled to the drain electrode of the 5th N type metal oxide semiconductor transistor MN5.The source electrode of the 9th P-type mos transistor MP9 is coupled to the drain electrode of the 7th P-type mos transistor MP7.The grid of the 9th P-type mos transistor MP9 is coupled to the grid of the 8th P-type mos transistor MP8.The drain electrode of the 9th P-type mos transistor MP9 is coupled to the drain electrode of the 8th N type metal oxide semiconductor transistor MN8.
The source electrode of the 2nd N type metal oxide semiconductor transistor MN2 is coupled to the base stage of a N type metal oxide semiconductor transistor MN1 and the base stage of the 2nd N type metal oxide semiconductor transistor MN2.The source electrode of the 3rd N type metal oxide semiconductor transistor MN3 is coupled to the base stage of the 3rd N type metal oxide semiconductor transistor MN3.The source electrode of the 4th N type metal oxide semiconductor transistor MN4 is coupled to the base stage of the 4th N type metal oxide semiconductor transistor MN4.The source electrode of the 5th N type metal oxide semiconductor transistor MN5 is coupled to the base stage of the 5th N type metal oxide semiconductor transistor MN5.The source electrode of the 6th N type metal oxide semiconductor transistor MN6 is coupled to the base stage of the 6th N type metal oxide semiconductor transistor MN6.The source electrode of the 7th N type metal oxide semiconductor transistor MN7 is coupled to the base stage of the 7th N type metal oxide semiconductor transistor MN7 and the base stage of the 8th N type metal oxide semiconductor transistor MN8.The source electrode of the first P-type mos transistor MP1 is coupled to the base stage of the first P-type mos transistor MP1 and the base stage of the second P-type mos transistor MP2.The source electrode of the 3rd P-type mos transistor MP3 is coupled to the base stage of the 3rd P-type mos transistor MP3 and the base stage of the 4th P-type mos transistor MP4.The source electrode of the 5th P-type mos transistor MP5 is coupled to the base stage of the 5th P-type mos transistor MP5.The source electrode of the 6th P-type mos transistor MP6 is coupled to the base stage of the 6th P-type mos transistor MP6.The source electrode of the 7th P-type mos transistor MP7 is coupled to the base stage of the 7th P-type mos transistor MP7.The source electrode of the 8th P-type mos transistor MP8 is coupled to the base stage of the 8th P-type mos transistor MP8.The source electrode of the 9th P-type mos transistor MP9 is coupled to the base stage of the 9th P-type mos transistor MP9.The source ground of the 3rd N type metal oxide semiconductor transistor MN3.
Among the operational amplifier OP_AMP shown in Figure 3, three equivalent bias current source Ibias1, Ibias2, Ibias3 that produced by common mode power supply VCC are arranged, and it is not solid element that described three equivalent bias current source Ibias1, Ibias2, Ibias3 are only drawn by the bias current among the diagram operational amplifier OP_AMP, so the non-condition that is used for being used as the disclosed operational amplifier OP_AMP of restriction the present invention.
The input of operational amplifier OP_AMP is positive input terminal INP and negative input end INN as shown in Figures 2 and 3.Equivalence bias current source Ibias2 and Ibias3 equate on current strength, and this is identical because of equivalent bias current source Ibias2 pairing P-type mos transistor MP1 and MP2 and equivalent bias current source Ibias3 pairing P-type mos transistor MP3 and MP4 with respect to the formed impedance of common mode power supply VCC.
When the current potential of common-mode voltage VCC hangs down, no matter what person's of positive input terminal INP and negative input end INN current potential is higher, has at least one differential pair in formed one first differential pair of P-type mos transistor MP1 and MP3 and P-type mos transistor MP2 and formed one second differential pair of MP4 and can guarantee in saturation region operation; Thus, even another one does not work in linear zone at the differential pair of saturation region operation, the potential change that the current potential that still can guarantee output OUT can effectively be followed positive input terminal INP and negative input end INN is carried out corresponding amplification and is changed.Included P-type mos transistor MP5, MP6, MP7, MP8, the MP9 of shift module T4 forms the amplifying stage of operational amplifier OP_AMP with higher gain.
The potential difference of mainly carrying out between input INP and the INN with common mode power supply VCC and motor driven power supply VM in operational amplifier OP_AMP is amplified.Suppose to work in the saturation region as P-type mos transistor MP1 and MP3, and when P-type mos transistor MP2 and MP4 worked in linear zone, the current potential that negative input end INN is imported can obtain the first order gain that common mode power supply VCC is provided by P-type mos transistor MP2; Then by bias current source Ibias2, this first order gain meeting is passed to P-type mos transistor MP7 by N type metal oxide semiconductor transistor MN3 and common current mirror and the P-type mos transistor MP6 that forms of MN5; This first order gain at last can be second level gain with this first order gain conversions and export output OUT to respect to the high-aspect-ratio (W/L) of P-type mos transistor MP6 with P-type mos transistor MP7.In like manner, under same condition, the current potential that positive input terminal INP is imported can obtain its first order gain by P-type mos transistor MP4, then and by bias current source Ibias3 and N type metal oxide semiconductor transistor MN6 and the formed current mirror of MN7 obtain its second level gain, wherein N type metal oxide semiconductor transistor MN7 also has high-aspect-ratio with respect to N type metal oxide semiconductor transistor MN6, and also this second level gain is output in output OUT at last.
The output stage of operational amplifier OP_AMP mainly is made up of P-type mos transistor MP7, MP9 and N type metal oxide semiconductor transistor MN7 and MN8, and this output stage can be by recently further increasing output impedance than the length and width that other metal oxide semiconductor transistors are big among the operational amplifier OP_AMP, to improve the gain of operational amplifier OP_AMP.Please note, N type metal oxide semiconductor transistor MN1 and MN2 provide bias current for N type metal oxide semiconductor transistor MN8 in the mode that current mirror shines upon, and N type metal oxide semiconductor transistor MN4 and P-type mos transistor MP5 are that P-type mos transistor MP8, MP9 provide bias current in the mode of current mirror mapping also.
By the disclosed motor drive circuit of Fig. 2, except can so that general motor can comprise the running of forward operation, reverse turn operation, shutoff operation and brake operating carrying out under constant current mode, constant voltage mode and the full swing pattern, also avoiding using a plurality of operational amplifiers than the simple circuit design of prior art, and the error that is produced when avoiding using a plurality of operational amplifier.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Claims (14)
1. a motor control circuit that is applied to the various control pattern is characterized in that, comprising:
One motor driving module is in order to drive a motor;
One logic control circuit is coupled to this motor driving module, in order to control an operator scheme of this motor driving module;
A plurality of switch modules, be coupled between this motor driving module and this logic control circuit, wherein this logic control circuit is controlled this motor driving module by described a plurality of switch modules and is switched between a constant current mode, certain voltage pattern and a full swing pattern; And
One operational amplifier is coupled between described a plurality of switch module and this motor driving module, in order to amplify voltage or the electric current of exporting from described a plurality of switch module.
2. the motor control circuit that is applied to the various control pattern according to claim 1 is characterized in that, described a plurality of switch modules comprise:
One first switch module, one first end of this first switch module is coupled to the certain voltage reference power source, one second end of this first switch module is coupled to a negative input end of this operational amplifier, and one the 3rd end of this first switch module is coupled to a voltage sampling end of this motor driving module;
One second switch module, one first end of this second switch module is coupled to certain current reference power supply, one second end of this second switch module is coupled to a positive input terminal of this operational amplifier, one the 3rd end of this second switch module is coupled to one first drive end of this motor driving module, and one the 4th end of this second switch module is coupled to one second drive end of this motor driving module;
One the 3rd switch module, one first end of the 3rd switch module is coupled to an output of this operational amplifier, one second end of the 3rd switch module is coupled to a first transistor control end of this motor driving module, and one the 3rd end of the 3rd switch module is coupled to a transistor seconds control end of this motor driving module; And
One the 4th switch module, one first end of the 4th switch module is coupled to this output of this operational amplifier, one second end of the 4th switch module is coupled to one the 3rd transistor controls end of this motor driving module, and one the 3rd end of the 4th switch module is coupled to one the 4th transistor controls end of this motor driving module;
Wherein one first end of this motor is coupled to this first drive end of this motor driving module, one second end of this motor is coupled to this second drive end of this motor driving module, and this motor driving module drives this motor with the potential difference between this first drive end and this second drive end;
Wherein one first control end of this logic control circuit is coupled to this first transistor control end of this motor driving module, one second control end of this logic control circuit is coupled to this transistor seconds control end of this motor driving module, one the 3rd control end of this logic control circuit is coupled to the 3rd transistor controls end of this motor driving module, and one the 4th control end of this logic control circuit is coupled to the 4th transistor controls end of this motor driving module;
Wherein one first switch terminals of this logic control circuit is coupled to a switch control end of this first switch module, one second switch end of this logic control circuit is coupled to a switch control end of this second switch module, one the 3rd switch terminals of this logic control circuit is coupled to a switch control end of the 3rd switch module, and one the 4th switch terminals of this logic control circuit is coupled to a switch control end of the 4th switch module.
3. the motor control circuit that is applied to the various control pattern according to claim 2, it is characterized in that, one first end of one sample resistance is coupled to the 3rd end of this first switch module and this voltage sampling end of this motor driving module, and one second end ground connection of this sample resistance.
4. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, this motor driving module also comprises:
One first P-type mos transistor, the transistorized grid of this first P-type mos is coupled to this first transistor control end of this motor driving module, the transistorized source electrode of this first P-type mos is coupled to a motor driven power supply, and this first P-type mos transistor drain is coupled to this first drive end of this motor driving module;
One the one N type metal oxide semiconductor transistor, the transistorized grid of the one N type metal oxide semiconductor is coupled to this transistor seconds control end of this motor driving module, the one N type metal oxide semiconductor transistor drain is coupled to this first P-type mos transistor drain, and the transistorized source electrode of a N type metal oxide semiconductor is coupled to this voltage sampling end of this motor driving module;
One second P-type mos transistor, the transistorized grid of this second P-type mos is coupled to the 3rd transistor controls end of this motor driving module, the transistorized source electrode of this second P-type mos is coupled to the transistorized source electrode of this first P-type mos, and this second P-type mos transistor drain is coupled to this second drive end of this motor driving module; And
One the 2nd N type metal oxide semiconductor transistor, the transistorized grid of the 2nd N type metal oxide semiconductor is coupled to the 4th transistor controls end of this motor driving module, the 2nd N type metal oxide semiconductor transistor drain is coupled to this second P-type mos transistor drain, and the transistorized source electrode of the 2nd N type metal oxide semiconductor is coupled to the transistorized source electrode of a N type metal oxide semiconductor.
5. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, this first switch module comprises:
One first switch, one first end of this first switch is coupled to this and decides the Voltage Reference power supply, and one second end of this first switch is coupled to this negative input end of this operational amplifier; And
One second switch, one first end of this second switch is coupled to this second end of this first switch, and one second end of this second switch is coupled to this voltage sampling end of this motor driving module.
6. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, this second switch module comprises:
One the 3rd switch, one first end of the 3rd switch is coupled to this and decides the current reference power supply, and one second end of the 3rd switch is coupled to this positive input terminal of this operational amplifier;
One the 4th switch, one first end of the 4th switch is coupled to this second end of the 3rd switch, and one second end of the 4th switch is coupled to this first drive end of this motor driving module; And
One the 5th switch, one first end of the 5th switch is coupled to this second end of the 3rd switch, and one second end of the 5th switch is coupled to this second drive end of this motor driving module.
7. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, the 3rd switch module comprises:
One the 6th switch, one first end of the 6th switch is coupled to this output of this operational amplifier, and one second end of the 6th switch is coupled to this first transistor control end of this motor driving module; And
One minion is closed, and one first end that this minion is closed is coupled to this first end of the 6th switch, and one second end of this minion pass is coupled to this transistor seconds control end of this motor driving module.
8. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, the 4th switch module comprises:
One octavo is closed, and one first end that this octavo is closed is coupled to this output of this operational amplifier, and one second end of this octavo pass is coupled to the 3rd transistor controls end of this motor driving module; And
One the 9th switch, one first end of the 9th switch are coupled to this first end that this octavo is closed, and one second end of the 9th switch is coupled to the 4th transistor controls end of this motor driving module.
9. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, also comprises:
One first resistance, one first end of this first resistance is coupled to the 3rd end of this second switch module, and one second end of this first resistance is coupled to this first drive end of this motor driving module;
One first electric capacity is parallel to this first resistance; And
One second resistance, one first end of this second resistance is coupled to this first end of this first resistance, and one second end ground connection of this second resistance.
10. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, also comprises:
One the 3rd resistance, one first end of the 3rd resistance is coupled to the 4th end of this second switch module, and one second end of the 3rd resistance is coupled to this second drive end of this motor driving module;
One second electric capacity is parallel to the 3rd resistance; And
One the 4th resistance, one first end of the 4th resistance is coupled to this first end of the 3rd resistance, and one second end ground connection of the 4th resistance.
11. the motor control circuit that is applied to the various control pattern according to claim 2 is characterized in that, this operational amplifier comprises:
One first differential pair module, a first input end of this first differential pair module is coupled to this positive input terminal of this operational amplifier, and one second input of this first differential pair module is coupled to this negative input end of this operational amplifier;
One second differential pair module, a first input end of this second differential pair module is coupled to this first input end of this first differential pair module, and one second input of this second differential pair module is coupled to this second input of this first differential pair module;
One shift module; And
One current mirror module is used for the electric current that the electric current that produced according to this first differential pair module and this second differential pair module produced to regulate the electric current that this shift module produces;
Wherein this first differential pair module and this second differential pair module are all powered with a common mode power supply, and this shift module is powered with a motor driven power supply.
12. the motor control circuit that is applied to the various control pattern according to claim 11 is characterized in that,
This first differential pair module comprises:
One first P-type mos transistor, the transistorized grid of this first P-type mos is coupled to this positive input terminal of this operational amplifier, and the transistorized source electrode of this first P-type mos is coupled to a bias current source that is powered by this common mode power supply; And
One second P-type mos transistor, the transistorized grid of this second P-type mos is coupled to this negative input end of this operational amplifier, and the transistorized source electrode of this second P-type mos is coupled to the transistorized source electrode of this first P-type mos;
This second differential pair module comprises:
One the 3rd P-type mos transistor, the transistorized grid of the 3rd P-type mos is coupled to this negative input end of this operational amplifier, and the transistorized source electrode of the 3rd P-type mos is coupled to this bias current source that is powered by this common mode power supply; And
One the 4th P-type mos transistor, the transistorized grid of the 4th P-type mos is coupled to this positive input terminal of this operational amplifier, and the transistorized source electrode of the 4th P-type mos is coupled to the transistorized source electrode of the 3rd P-type mos;
This current mirror module comprises:
One the one N type metal oxide semiconductor transistor, the one N type metal oxide semiconductor transistor drain is coupled to this common mode power supply, and the transistorized grid of a N type metal oxide semiconductor is coupled to a N type metal oxide semiconductor transistor drain;
One the 2nd N type metal oxide semiconductor transistor, the 2nd N type metal oxide semiconductor transistor drain is coupled to the transistorized source electrode of a N type metal oxide semiconductor, and the transistorized grid of the 2nd N type metal oxide semiconductor is coupled to the 2nd N type metal oxide semiconductor transistor drain;
One the 3rd N type metal oxide semiconductor transistor, the 3rd N type metal oxide semiconductor transistor drain is coupled to this second P-type mos transistor drain, the transistorized grid of the 3rd N type metal oxide semiconductor is coupled to the 3rd N type metal oxide semiconductor transistor drain, and the transistorized source electrode of the 3rd N type metal oxide semiconductor is coupled to this first P-type mos transistor drain and the transistorized source electrode of the 2nd N type metal oxide semiconductor;
One the 4th N type metal oxide semiconductor transistor, the transistorized grid of the 4th N type metal oxide semiconductor is coupled to the transistorized grid of the 3rd N type metal oxide semiconductor, and the transistorized source electrode of the 4th N type metal oxide semiconductor is coupled to the transistorized source electrode of the 3rd N type metal oxide semiconductor;
One the 5th N type metal oxide semiconductor transistor, the transistorized grid of the 5th N type metal oxide semiconductor is coupled to the transistorized grid of the 3rd N type metal oxide semiconductor, and the transistorized source electrode of the 5th N type metal oxide semiconductor is coupled to transistorized source electrode of the 3rd N type metal oxide semiconductor and the 3rd P-type mos transistor drain;
One the 6th N type metal oxide semiconductor transistor, the 6th N type metal oxide semiconductor transistor drain is coupled to the 4th P-type mos transistor drain, the transistorized grid of the 6th N type metal oxide semiconductor is coupled to the 6th N type metal oxide semiconductor transistor drain, and the transistorized source electrode of the 6th N type metal oxide semiconductor is coupled to the transistorized source electrode of the 3rd N type metal oxide semiconductor;
One the 7th N type metal oxide semiconductor transistor, the transistorized grid of the 7th N type metal oxide semiconductor is coupled to the 6th N type metal oxide semiconductor transistor drain, and the transistorized source electrode of the 7th N type metal oxide semiconductor is coupled to the transistorized source electrode of the 6th N type metal oxide semiconductor; And
One the 8th N type metal oxide semiconductor transistor, the transistorized grid of the 8th N type metal oxide semiconductor is coupled to the transistorized grid of a N type metal oxide semiconductor, and the transistorized source electrode of the 8th N type metal oxide semiconductor is coupled to the 7th N type metal oxide semiconductor transistor drain;
This shift module comprises:
One the 5th P-type mos transistor, the 5th P-type mos transistor drain is coupled to the 4th N type metal oxide semiconductor transistor drain, the transistorized grid of the 5th P-type mos is coupled to the 5th P-type mos transistor drain, and the transistorized source electrode of the 5th P-type mos is coupled to this motor driven power supply;
One the 6th P-type mos transistor, the transistorized source electrode of the 6th P-type mos is coupled to the transistorized source electrode of the 5th P-type mos, and the transistorized grid of the 6th P-type mos is coupled to the 5th N type metal oxide semiconductor transistor drain;
One the 7th P-type mos transistor, the transistorized source electrode of the 7th P-type mos is coupled to the transistorized source electrode of the 6th P-type mos, and the transistorized grid of the 7th P-type mos is coupled to the transistorized grid of the 6th P-type mos;
One the 8th P-type mos transistor, the transistorized source electrode of the 8th P-type mos is coupled to the 6th P-type mos transistor drain, the transistorized grid of the 8th P-type mos is coupled to the transistorized grid of the 5th P-type mos, and the 8th P-type mos transistor drain is coupled to the 5th N type metal oxide semiconductor transistor drain; And
One the 9th P-type mos transistor, the transistorized source electrode of the 9th P-type mos is coupled to the 7th P-type mos transistor drain, the transistorized grid of the 9th P-type mos is coupled to the transistorized grid of the 8th P-type mos, and the 9th P-type mos transistor drain is coupled to the 8th N type metal oxide semiconductor transistor drain.
13. the motor control circuit that is applied to the various control pattern according to claim 12 is characterized in that,
The transistorized source electrode of the 2nd N type metal oxide semiconductor is coupled to transistorized base stage of a N type metal oxide semiconductor and the transistorized base stage of the 2nd N type metal oxide semiconductor;
The transistorized source electrode of the 3rd N type metal oxide semiconductor is coupled to the transistorized base stage of the 3rd N type metal oxide semiconductor;
The transistorized source electrode of the 4th N type metal oxide semiconductor is coupled to the transistorized base stage of the 4th N type metal oxide semiconductor;
The transistorized source electrode of the 5th N type metal oxide semiconductor is coupled to the transistorized base stage of the 5th N type metal oxide semiconductor;
The transistorized source electrode of the 6th N type metal oxide semiconductor is coupled to the transistorized base stage of the 6th N type metal oxide semiconductor;
The transistorized source electrode of the 7th N type metal oxide semiconductor is coupled to transistorized base stage of the 7th N type metal oxide semiconductor and the transistorized base stage of the 8th N type metal oxide semiconductor;
The transistorized source electrode of this first P-type mos is coupled to transistorized base stage of this first P-type mos and the transistorized base stage of this second P-type mos;
The transistorized source electrode of the 3rd P-type mos is coupled to transistorized base stage of the 3rd P-type mos and the transistorized base stage of the 4th P-type mos;
The transistorized source electrode of the 5th P-type mos is coupled to the transistorized base stage of the 5th P-type mos;
The transistorized source electrode of the 6th P-type mos is coupled to the transistorized base stage of the 6th P-type mos;
The transistorized source electrode of the 7th P-type mos is coupled to the transistorized base stage of the 7th P-type mos;
The transistorized source electrode of the 8th P-type mos is coupled to the transistorized base stage of the 8th P-type mos;
The transistorized source electrode of the 9th P-type mos is coupled to the transistorized base stage of the 9th P-type mos.
14. the motor control circuit that is applied to the various control pattern according to claim 12 is characterized in that, the transistorized source ground of the 3rd N type metal oxide semiconductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010101657046A CN102237850B (en) | 2010-05-05 | 2010-05-05 | Motor control circuit applied to multiple control modes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010101657046A CN102237850B (en) | 2010-05-05 | 2010-05-05 | Motor control circuit applied to multiple control modes |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102237850A CN102237850A (en) | 2011-11-09 |
CN102237850B true CN102237850B (en) | 2013-07-31 |
Family
ID=44888156
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010101657046A Expired - Fee Related CN102237850B (en) | 2010-05-05 | 2010-05-05 | Motor control circuit applied to multiple control modes |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102237850B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105222900B (en) * | 2015-09-15 | 2018-09-28 | 工业和信息化部电子第五研究所 | Infrared focal plane array reading circuit |
JP6505062B2 (en) * | 2016-10-12 | 2019-04-24 | 本田技研工業株式会社 | Voltage conversion device and device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3546482B2 (en) * | 1994-09-20 | 2004-07-28 | ダイキン工業株式会社 | Brushless DC motor |
CN1681194A (en) * | 2004-04-09 | 2005-10-12 | 圆创科技股份有限公司 | Motor controlling circuit with controllable driven voltage supply |
CN101223687A (en) * | 2005-08-26 | 2008-07-16 | 罗姆股份有限公司 | Motor drive device and cooling device using the same |
CN101267180A (en) * | 2007-03-15 | 2008-09-17 | 普诚科技股份有限公司 | Control circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6756754B2 (en) * | 2002-10-01 | 2004-06-29 | Siemens Vdo Automotive Inc. | Integrated one touch up and down windowlift motor with direct sense for anti-pinch |
-
2010
- 2010-05-05 CN CN2010101657046A patent/CN102237850B/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3546482B2 (en) * | 1994-09-20 | 2004-07-28 | ダイキン工業株式会社 | Brushless DC motor |
CN1681194A (en) * | 2004-04-09 | 2005-10-12 | 圆创科技股份有限公司 | Motor controlling circuit with controllable driven voltage supply |
CN101223687A (en) * | 2005-08-26 | 2008-07-16 | 罗姆股份有限公司 | Motor drive device and cooling device using the same |
CN101267180A (en) * | 2007-03-15 | 2008-09-17 | 普诚科技股份有限公司 | Control circuit |
Non-Patent Citations (1)
Title |
---|
JP特许第3546482B2 2004.07.28 |
Also Published As
Publication number | Publication date |
---|---|
CN102237850A (en) | 2011-11-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106230416B (en) | It is a kind of with active clamp without bootstrapping gate driving circuit | |
CN100533961C (en) | Voltage comparator circuit | |
CN105549673B (en) | Dual-mode switching type LDO circuit | |
CN107102671A (en) | Low-power consumption fast transient response low-voltage difference adjustor | |
US7605656B2 (en) | Operational amplifier with rail-to-rail common-mode input and output range | |
CN202503479U (en) | A class AB operational amplifier with high gain and a high power supply rejection ration | |
CN110729995B (en) | Level conversion circuit and level conversion method | |
CN104426494B (en) | High speed amplifier | |
CN107092296A (en) | A kind of fast transient response low-voltage difference adjustor | |
CN102237850B (en) | Motor control circuit applied to multiple control modes | |
CN109283475A (en) | Magnetic sensor circuit | |
CN110275567B (en) | Current subtraction circuit and application thereof | |
CN107800422A (en) | Level shifter and semiconductor device | |
CN105529994A (en) | Transimpedance amplifier with gain bootstrap function | |
US9654092B1 (en) | High speed gain stage with analog input and determinable digital output using regenerative feedback | |
CN106059516B (en) | Track to track operational amplification circuit and ADC converter, dcdc converter and power amplifier | |
TWI398090B (en) | Motor controlling circuit for multiple control modes | |
US9473122B1 (en) | Rail-to-rail input stage circuit with constant transconductance | |
CN201323554Y (en) | Gain auxiliary amplifying circuit | |
CN104253609B (en) | A kind of low-voltage differential signal drive circuit | |
JP5723303B2 (en) | Light receiving circuit | |
CN205945659U (en) | Transimpedance amplifier with gain bootstrapping function | |
CN111541432B (en) | Error amplifier circuit for dynamic negative bias application | |
CN203872141U (en) | Large-dynamic range variable gain amplifier | |
CN104038171B (en) | Large dynamic range variable gain amplifier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130731 Termination date: 20180505 |
|
CF01 | Termination of patent right due to non-payment of annual fee |