CN102177584A - 具有可调电阻的硅基纳米级电阻器件 - Google Patents
具有可调电阻的硅基纳米级电阻器件 Download PDFInfo
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Abstract
一种非易失性固态电阻器件,所述非易失性固态电阻器件包括第一电极、p型硅第二电极、和电连接在所述电极之间的非结晶硅纳米结构。所述纳米结构具有响应于通过所述电极施加到所述纳米结构的电压可调的电阻。所述纳米结构可以被形成为被嵌入位于所述电极之间的绝缘层中的纳米柱。第一电极可以是银或其它导电金属电极。第三(金属)电极可以在邻近纳米结构的位置处连接到p型多晶硅第二电极以允许所述两个金属电极连接到其它电路。电阻器件可以被用作数字非易失性存储器件的单位存储单元以通过在两个或更多个值之间改变它的电阻来存储一位或更多位数字数据。
Description
技术领域
本发明涉及能够用于存储器存储和可控电路互连的具有可调电阻的两端非易失性固态电阻器件。
背景技术
电阻性随机存取存储器(RRAM)作为超高密度非易失性信息存储装置的潜在候选物最近已经产生重要的影响。典型的RRAM器件包括夹在一对电极之间的绝缘体层并且展现电脉冲感应滞后电阻变换效应。通过由于焦耳热和二元氧化物(例如NiO和TiO2)中的电化学过程或离子导体(包括氧化物、硫族化物和聚合物)的氧化还原过程而在绝缘体内形成导电细丝来解释所述电阻变换。也已经通过TiO2和非晶硅(a-Si)膜中离子的场辅助扩散解释了所述电阻变换。
在a-Si结构的情形下,金属离子到硅中的电压感应扩散导致减小a-Si结构的电阻的导电细丝的形成。这些细丝在偏置电压被除去之后继续存在,从而给予器件非易失性特性,并且它们可以在反极性施加的电压的原动力下通过离子的反向扩散回到金属电极而被除去。
由夹在两个金属电极之间的a-Si结构形成的电阻器件已经被示出展现了该可控电阻特性。然而,这样的器件通常具有微米尺寸的细丝,其可以阻止它们按比例缩小到亚100纳米范围。这样的器件也可能需要高形成电压,其可能导致器件损坏并且可能限制成品率。
发明内容
根据本发明的一个方面,提供一种非易失性固态电阻器件,包括第一电极、p型硅第二电极、和电连接在所述电极之间的非结晶硅纳米结构。所述纳米结构具有响应于通过电极施加到纳米结构的电压可调的电阻。非结晶硅纳米结构可以是例如非晶硅纳米结构或非晶多晶硅纳米结构。
根据本发明的另一个方面,电阻器件被用作数字非易失性存储器件中的存储单元。存储器件可以包括这种电阻器件的阵列,其在一个实施例中为每个电阻器件提供一位存储,在另一个实施例中为每个电阻器件提供多级数字存储(multi-level number storage)使得每个存储单元可以存储一位以上的数据。
根据本发明的另一个方面,电阻器件被用作电子电路中的电互连。所述互连可以至少在基本导电和基本不导电状态之间变换。
根据本发明的又一个方面,提供一种非易失性固态电阻器件,包括第一金属电极、p型多晶硅电极、至少部分地位于所述电极之间的绝缘层、嵌入在绝缘层中的非晶硅结构、和第二金属电极。非晶硅结构具有均被连接到所述电极的不同电极的相对端面。第一电极包括金属,所述金属在有跨越电极施加的电压的情况下提供在硅结构内形成细丝的金属离子。结果,硅结构展现可以根据施加的电压被调整的电阻。第二金属电极在离硅结构不超过100 nm的位置处与多晶硅电极接触。
根据本发明的另一个方面,提供一种将非易失性固态开关器件从断开状态调整到接通状态的方法,所述方法包括在非结晶硅纳米结构两端施加电压的步骤,其中施加的电压具有这样的幅度和持续时间:选择所述幅度和持续时间以便获得硅纳米结构从断开状态变换到接通状态的预定概率。
附图说明
以下将结合附图描述本发明的优选示范性实施例,其中类似的标记表示类似的元件,并且其中:
图1(a)是根据本发明构造的单一单元a-Si电阻器件的一个实施例的图示;
图1(b)是部分构造的a-Si结构(例如图1(a)中所示)的顶视图的SEM图像;
图1(c)是示出典型a-Si结构(例如图1(a)中所示)的电阻变换特性的图;
图1(d)是示出a-Si器件(例如图1(a)中所示)的编程响应(programming response)的波形;
图1(e)是示出a-Si器件(例如图1(a)中所示)的耐久性测试的结果的波形;
图2(a)-2(c)描绘了典型a-Si器件对于不同偏置电压的变换响应的直方图;
图2(d)是示出在a-Si器件(如图1(a)中所示)的不同导电状态的金属离子扩散的三部分图(three-part diagram);
图2(e)是示出a-Si器件(例如图1(a)中所示)的变换时间和偏置电压之间的关系的图;
图3(a)示出利用不同的串联连接的控制电阻器对典型a-Si器件编程或对通过其它方式控制的电流电平编程的结果;
图3(b)描绘了编程的a-Si器件的最终电阻与用来编程器件所选择的控制电阻之间的相互关系;
图3(c)是在没有任何串联连接的控制电阻器的情况下在施加给定的偏置电压时对于典型a-Si器件随着时间的过去单一、分立的电阻变换事件的概率图;
图3(d)是在没有任何串联连接的控制电阻器的情况下在施加给定的偏置电压时对于典型a-Si器件随着时间的过去具有至少一个电阻变换事件的概率图;
图3(e)是在使用串联连接的控制电阻器时对于典型a-Si器件随着时间的过去单一、分立的电阻变换事件的概率图;
图4(a)是在没有偏置电压施加到a-Si器件(例如图1(a)中所示)时接通到断开的电阻转换的等待时间的图;
图4(b)是等待时间与温度的关系图;
图5是示出将控制电阻器用于单个a-Si器件中的多级数字存储的控制电路的示意图;
图6是使用a-Si结构(例如图1(a)中所示)的存储器件的平面图(部分断开);
图7-9是具有内置二极管的单一单元a-Si电阻器件的不同实施例的简图;
图10和11是具有内置二极管和用作用于a-Si器件的多级编程的栅控可变电阻器的场效应晶体管(FET)的a-Si电阻器件的不同实施例的简图;以及
图12和13描绘了在此公开的基本a-Si电阻器件的示范性本征二极管特性。
具体实施方式
图1(a)示出包括纳米级a-Si结构14的非易失性固态电阻器件10,所述纳米级a-Si结构14展现可以被选择性地设置为多个值、并且可以被复位的电阻,全部都使用合适的控制电路来进行。一旦被设置,电阻值可以利用小电压读取,所述小电压幅度足以确定该电阻而不使它改变。尽管示出的实施例使用a-Si作为电阻元件,但将要理解的是,可以使用其它非结晶硅(nc-Si)结构,例如非晶多晶硅。因此,正如在此和在权利要求中所使用的,非结晶硅(nc-Si)表示展现可控电阻的非晶硅(a-Si)或非晶多晶硅(多晶-Si)或所述两者的组合。此外,尽管这里的许多讨论也被应用于更大规模的a-Si结构,例如那些具有一个或多个在微米范围内的尺寸的a-Si结构,但是示出的实施例是a-Si纳米结构,所述a-Si纳米结构展现只有它的小尺寸才有的特定特性。正如在此所用的,术语纳米结构指的是具有至少两个纳米级范围内的尺寸的结构;例如,具有在0.1到100纳米的一般范围内的直径或多个截面尺寸的结构。这包括具有全部三个纳米级空间尺寸的结构;例如,具有与它的纳米级直径在相同量级的长度的圆柱形纳米杆或纳米柱。纳米结构可以包括本领域技术人员已知的多个纳米结构;例如,纳米管、纳米线、纳米棒、纳米杆、纳米柱、纳米粒子、和纳米纤维。一个这样的结构14是图1(a)和1(b)中所示的实施例,所述实施例是截面(具有小于100 nm(例如在所示的特定实例中为60 nm)的直径)可以为圆形的塞子或柱结构。柱高度或长度(取决于方向)可以是纳米级(例如所示实例中为30 nm)或更大。
图1(a)和1(b)的a-Si结构14被嵌入绝缘电介质16中,所述绝缘电介质16可以由多种材料制成并且以不同方式构造,但是图中所示的是旋涂玻璃(SOG)层16,所述旋涂玻璃(SOG)层16最初围绕a-Si结构14流动,然后被固化,所有这些都可以利用已知的工艺进行。利用被热二氧化物层24覆盖的硅衬底层22构建整个电阻器件10。在a-Si柱14下面的是与a-Si柱14的下端面接触并且从所述柱横向延伸离开以容纳叠置的金属电极20的硼掺杂或其它p型多晶硅电极18,所述金属电极20可以由任何合适的金属(包括例如铂系金属,诸如钯或铂)制成。在a-Si柱14的上部表面(端面)上与多晶硅(p-Si)电极18相对的是充当细丝形成离子的源的银(Ag)金属电极12。尽管在所示的实施例中使用银,但是要理解的是,该电极12(以及另一个金属电极20)可以由多种其它合适金属形成,例如金(Au)、镍(Ni)、铝(Al)、铬(Cr)、铁(Fe)、锰(Mn)、钨(W)、钒(V)、钴(Co)。也可以使用能够提供细丝形成离子的其它合适金属。
为制作图1(a)的a-Si器件10,硼掺杂p-Si底部电极层18可以通过LPCVD(低压化学气相沉积)沉积在具有200 nm热二氧化物的正品(prime grade)硅衬底上。非晶硅层可以是沉积在硼掺杂的p-Si的顶部的30 nm厚的层,后面是两个RIE(反应离子刻蚀)步骤以限定a-Si柱14和p-Si底部电极18结构。然后可以在样品上以3000 RPM的速度旋涂旋涂玻璃(SOG),然后将其在320℃固化1小时。该绝缘SOG层16提供两个对置电极12、18的电隔离以及为a-Si柱14提供机械支撑。在被形成后,SOG层16可以被部分刻蚀掉以制造平坦表面并且暴露a-Si柱14的端面。然后可以利用剥离工艺通过图案化在a-Si柱14的暴露的端面上形成Ag电极12。然后可以施加第二金属(铂)电极20以提供到底部p-Si层18的欧姆接触。铂电极20位于a-Si柱14附近以帮助使通过p-Si电极18的电阻最小,并且该距离优选不大于100 nm。可以选择图案设计以便最小化顶部和底部电极12、18之间的交迭以便保持通过SOG 16的低的直流泄漏电流。本领域技术人员将会理解的是,可以对该制造程序进行多种修改,并且也可以使用其它制造方法以实现允许器件的电阻可调性的图1(a)的结构或另外合适的nc-Si结构。美国专利申请公开物No. 2009/0014707 A1提供涉及非易失性固态电阻开关器件(例如图1(a)和1(b)中所示的a-Si器件)的特性、使用、和操作的附加信息。它也提供涉及a-Si器件的替换实施例的结构的信息,其至少一些可适用于图1(a)和1(b)中所示的a-Si器件的结构。在此通过引用并入包含在美国专利申请公开物No. 2009/0014707 A1中的涉及其中公开的非易失性固态电阻开关器件的制造、结构、和使用的信息。
图1(a)中所示的单一a-Si器件可以被用作独立可重构互连或存储位(利用它的独立受控的顶部和底部电极对)。使用化学气相沉积(CVD)沉积的多晶硅作为底部接触使器件能够制造在多种衬底上(包括用于多层3D结构集成的可能)。与连续a-Si膜相比,示出的a-Si塞子结构14有助于确保对有源a-Si区和细丝面积在物理上进行很好地限定。此外,器件的该结构与CMOS技术完全兼容并且可以容易地并入现有***作为逻辑电路(例如神经形态网络)中的高密度非易失性存储器或可重构互连。
图1(c)示出典型a-Si柱(例如图1(a)中所示)的电阻变换特性(例如针对具有大约60 nm的直径和30 nm厚度的器件)。它包括示出接通过程期间的步进式转换的以对数标度为单位的该变换特性的插图。这些纳米级a-Si开关不需要高压形成,并且在形成后所述器件可以通过施加正写入和负擦除电压脉冲在低电阻接通和高电阻断开状态之间变换。在小偏置下测量的接通/断开电阻比可以高达107,如图1(c)中所示。以上述方式制造的a-Si器件的测试表明,作为存储器件,就成品率(例如对于具有60 nm直径的a-Si柱的器件来说成品率>95%)、速度、耐久性和保持力而言,a-Si开关展现优越的性能度量。图1(d)示出具有50 ns写入/擦除脉冲宽度的代表性写入-读取-擦除-读取脉冲序列和来自典型器件的输出响应。所述器件的耐久性测试的结果在图1(e)中示出。具有< 20μA的接通电流的典型器件被预期经受得住大于105个编程周期而不退化。超过该限制,断开状态电导开始增加,从而导致接通/断开电阻比减小。
a-Si结构的变换可以通过在施加编程电压时纳米级Ag细丝的形成和恢复来解释,在图2(d)中示意性地示出。在前面关于微米级金属/a-Si/金属结构的实验和理论研究中,提出细丝呈被俘获在a-Si层中的缺陷位置中的一连串带正电的Ag+粒子形态。在接通状态中的导电机制是通过Ag+链的电子隧道效应,然后器件电阻受最后的Ag+粒子与底部电极之间的隧穿电阻支配。如图1(c)中所示,该行为与当附加Ag+粒子跳迁到新的俘获位置中Ag细丝以步进式方式增加时在断开-接通转换期间以对数标度为单位的电流的步进式增加一致。
在a-Si柱结构中明确限定的有源变换区域连同由CMOS兼容制造工艺提供的良好控制一起使得能够进行详细研究以探索由电阻开关器件提供的独特特性。细丝形成模型的一个直接结果是变换比率可能是与偏置相关的,因为与电子隧穿效应不同,Ag+粒子的跳迁是热激发过程并且该比率由与偏置相关的激发能E a ’(V)确定:
其中k B 是玻尔兹曼常数,T是绝对温度,τ是特征停留时间并且ν是尝试频率。如图2(d)中所示,可以通过施加偏置电压降低激发能,导致产生与偏置相关的等待时间和变换比率。
已经通过对作为偏置电压的函数的第一转换(即图1(c)中的第一电流步骤)的等待时间的研究验证了该效应。通过施加具有给定电压幅度的矩形脉冲到处于断开状态中的器件并且测量时间t的下降直到电流的第一急速增加为止来测量等待时间。然后通过负电压脉冲擦除所述器件并且重复所述测量。图2(a)-(c)示出在相同器件上在2.6 V、 3.2 V和3.6 V的偏置电压下对于第一转换的等待时间的直方图。因为变换过程的随机性质,等待时间应当遵循泊松分布并且在时间t处在Δt内出现变换的概率由以下给出:
图2(a)-(c)中的直方图可以与使用τ作为唯一拟合参数的等式2拟合,从而分别产生15.3 ms、1.2 ms 和0.029 ms的τ值。这些图表明,τ是V的强函数并且在V增加仅1V时减小大约103。图2(e)示出在5个不同偏置电压下测量的τ的分布以及采用指数式衰减的拟合,将τ 0 和V 0 看作拟合参数:
有兴趣的是注意等式3中的V 0 的物理意义。由图2(d)并且到第一阶,,其中E a 是零偏置时的激活能,E是电场并且d是Ag+俘获位置之间的距离。如果假定电压的大部分降在Ag+链两端并且Ag+粒子均匀分布在链内,则到第一阶,其中n是Ag+位置的数目。然后可以由等式1直接导出等式3,其中
重要地,由图2(e)中的拟合推断的0.155V的V 0 值非常接近于由该简单模型断定的V 0 值,0.156V,假定在细丝中有3个Ag+位置(n=3),正如由图1(c)中的半对数I-V曲线中的主要电流步骤数所表明的。等式3清楚地表明,等待时间强烈地与偏置相关,并且它可以通过增加施加的偏置而指数式减小。
与偏置相关的变换特性对器件操作具有重要的含意。首先,即使变换可能非常急剧-见图1(c),变换也基本上不具有“硬”阈值电压,因为即使在相对低的偏置电压下也总会有出现变换的有限概率。另一方面,阈值电压可以被限定用于给定的编程脉冲宽度。例如,如果阈值被限定为在其上95%的成功率被实现的电压,则对于1 ms脉冲阈值电压是3.3 V,并且对于10 ns的脉冲宽度阈值电压是5.1 V。第二,通过调整外部电路电阻可以在这些器件中实现多级位存储。当串联电阻器被附着到器件时,它两端的电压在初始变换后将被减小,导致随后的变换事件的等待时间更长得多。因此,如果在随后的变换事件可能出现之前除去编程脉冲则可以产生部分形成的细丝,导致在接通和断开状态之间的中间电阻值。图3(a)示出在使用相同编程脉冲但是具有不同串联电阻器值的相同器件上获得的最后器件电阻。在器件上获得的8 = 23个不同电阻值表明作为存储部件的每个器件可以存储多达3位信息。器件电阻R也与串联电阻器的电阻Rs很好地关联,如图3(b)中所示,因为当器件电阻变得与Rs可比较时引起等待时间延长的分压器效应最显著。
多种方法可以被用来实现将多级数字选择性地编程到a-Si器件中。正如在此所用的,多级数字是具有大于两个(二进制)级或值的数字,例如三进制数或数字、四进制数字等。多级数字存储可以被用来存储多位二进制信息;例如,四级a-Si存储单元可以在单个a-Si单元中存储两位二进制数据,并且八级单元可以存储三位二进制数据。当在数字电路器件中使用时,存储单元可以包括合适的控制电路以把二进制或其它数字编程到a-Si器件中。这种电路在本领域技术人员的水平内并且一个这样的控制电路的示例性简图在图5中示出。通过将附加电阻***到与a-Si结构串联的电路中或者通过在与a-Si结构串联的电路中除去附加电阻,所示的控制电路可以被用来将a-Si结构设置在八个电阻级的任何一个。为此,可以使用解码电路将三位二进制输入数据变换成用来将控制电阻器接入电路或与电路断开的相应控制信号。这样,解码电路可以通过将与a-Si结构串联的总控制电阻设置成相关电阻值而将a-Si结构的电阻调整成多个期望电阻值中的任何一个。正如将要认识到的,图5的控制电路仅是简图并且用来写入、擦除、和读取a-Si结构的电阻值的具体电路布置对本领域技术人员而言是已知的。
例如图5中的控制电路可以被用来执行上述多个步骤以便调整a-Si结构的电阻。这些步骤一起包括可以用来在开始的电阻值和最后的电阻值之间调整a-Si结构的电阻。通常,所述方法包括将a-Si结构(其是第一电阻器件)与第二电阻器件串联电连接并且在串联连接的电阻器件两端施加电压的步骤。如上所述,第二电阻器件是包括一个或者两个或更多个控制电阻器的组合的控制电阻。根据a-Si结构的期望的最后电阻值来选择(例如通过解码电路)控制电阻。而且,正如在此讨论的,至少可以部分地根据施加电压的幅度、施加电压的持续时间、或同时根据两者来设置a-Si结构的最后电阻值。因此,施加步骤可以包括通过在串联连接的电阻器件两端施加所选幅度和持续时间的电压来设置最后的电阻值。此外,如上所述,可以利用a-Si结构实现多级数字存储,使得最后的电阻值是多个可选电阻值中的一个。为此,将a-Si结构与控制电阻串联电连接的步骤进一步包括基于所述可选电阻值中的被选择的电阻值通过选择性地***或分接一个或多个与a-Si结构串联的控制电阻器来电学上形成控制电阻。这再次可以利用图5的解码电路或利用对本领域技术人员而言显而易见的其它合适电路进行。为将a-Si器件复位回到开始的电阻值,施加相反极性的复位电压到a-Si结构。
a-Si结构可以被用作具有许多以阵列或其它合适结构布置的a-Si存储单元的数字非易失性存储器件的存储单元。图6描绘了例如能被用来形成超高密度存储器件的示范性实施例。示出的存储器件126包括具有SiO2顶层124的衬底122和由一组平行金属电极112垂直重叠一组平行p-Si电极118形成的交叉条结构。a-Si电阻器件(总体上以110表示)位于两种电极的每个交叉处。相对于图1的编号元件相差100的图6的编号元件可以具有类似于(然而不一定相同)图1的编号元件的结构和功能。电阻器件110包括存储器件126的单独可寻址存储单元。位于上部电极组112和下部电极组118之间的是在每个存储单元110处包含a-Si结构的SOG或其它绝缘层116。绝缘层116可以向下延伸到衬底的上层124并且因此隔离彼此相邻的电极118,或为此可使用在层116下面的分隔绝缘层121。而且,并不是在一列中的相邻单元之间延伸p-Si电极118,而是它们可以被限制到每个单元位置并且可以使用Pt或其它合适的金属电极来互连每列内的p-Si电极。其它变型对本领域技术人员而言将会显而易见。器件110的单元尺寸127大约是0.003μm2。在其它实例中,单元尺寸127可以小于0.003μm2或者小于或等于0.01μm2。
每个存储单元110可以包括单一a-Si结构,并且如上所述,a-Si结构可以具有被用来实现一位数字存储的可调电阻,或可以具有被设置为三个或更多个电阻(其每一个对应于不同的存储数字)中的任何一个的可调电阻。这样,每个存储单元能够进行多级数字存储。为此,存储单元126可以包括例如图5中的控制电路以允许在任何所选的存储单元110处写入多级数据。
a-Si结构可以通过上述在接通和断开状态之间变换它的方法来操作,而不是被用于位或多级数字存储。这可以通过在a-Si结构两端施加电压来进行,其中施加的电压具有被选择以便实现a-Si器件从断开状态变换到接通状态的预定概率的幅度和持续时间。成功变换的预定概率可以是例如95%或者可以是a-Si器件的特殊应用所期望或要求的任何其它百分比。
如上所指出的,a-Si器件的成功操作不仅取决于偏置的幅度,而且取决于偏置的持续时间。变换控制要求也取决于期望的是数字变换(例如作为一位存储器)还是模拟操作(例如作为互连)。对于以上讨论的泊松过程,图3(c)绘出在时间t期间一个变换事件正好发生的概率,而图3(d)绘出在时间t期间至少一个变换事件发生的概率。它们对应于没有外部串联电阻的情况并且单一变换率1/τ适用于步进式细丝形成过程。然后很明显的是,对于足够长的编程脉冲所述器件充当极好的数字开关(例如对于t 脉冲 > 3τ,获得95%的成功率)。另一方面,对于开关的多级数字存储或模拟操作,脉冲宽度必须被优化。例如对于仅第一变换发生的最高概率,t 脉冲 必须在τ的中心。即使如此,最大成功率仅为38%,如图3(c)中所示。然而,可以通过附加外部串联电阻来明显改善多位操作的成功率,其显著地减小了随后的变换率。图3(e)绘出仅第一变换事件在简化的两步细丝形成过程(其中使用两个不同比率)中发生的概率:
其中τ 1 = 3.36μs和τ 2 = 1.30 s分别对应于当器件两端的电压从4V(在第一变换事件之前并且R >> RS)变到2 V(在第一变换事件之后并且R = RS)时的变换率,作为第一变换事件后分压器效应的结果。现在对于5τ 1 < t 脉冲 <0.01τ 2 (在4 V偏置下大约13 ms的时间余量)可以实现大于99%的更高得多的成功率以将变换限制到仅第一事件。另外,类似的展现的特性从其它电阻开关器件来预期,因为它们中的许多包括某种激活能过程(例如离子的扩散和氧化还原反应)。
可以由与等式1的等待时间相关的温度获取势垒的激活能。图4(a)示出最初在接通状态被编程的器件在零偏置下在从100℃到150℃的温度下与时间相关的电阻变化。返回参考图1(c),到断开状态的突然转换对应于Ag细丝的恢复(通过Ag+粒子从最接近底部电极的俘获位置向顶部电极热激活跳迁),正如通过图4(b)中示出的等待时间t与1/k B T的Arrhenius型关系曲线中的良好拟合所检验的。根据Arrhenius曲线的斜率,所述器件的接通/断开转换的激活能可以被求出是0.87 eV,并且根据外推法在室温下的保留时间可以被估算是6年。
当被并入例如图6中所示的存储器阵列时或另外当特殊应用需要或期望时,可以利用以p-n结形式的本征二极管构造所述a-Si器件。通过在p型多晶硅电极和第二金属(例如铂)电极之间进一步包括n型层,所述a-Si器件可以在制造期间被并入。上述的实例在图7中示出,除了Pt电极下增加的n型层外,其可以与图1的a-Si电阻器件10相同。当在交叉条型的存储器阵列中使用时,该结构可以被用来防止相邻器件之间的串扰,因为通过它的二极管流出一个单元的向前传导电流将被相邻单元的二极管(现在被反向偏置)阻挡。
图8描绘了包括内置二极管的单一单元a-Si电阻器件210的另一个实施例,其可以利用常规CMOS制造技术形成。相对于图1的编号元件相差200的图8的编号元件可以具有与图1的编号元件类似的结构和功能(然而不一定相同)。器件210可以利用N型结晶硅衬底222构造。P型硅区域218可以是通过常规CMOS工艺(例如离子注入或扩散方法)形成的多晶硅层。P型区域218和Ag端子212与a-Si柱214接触,其可以根据施加的偏置改变它的电阻,如上所述。可以通过SOG(旋涂玻璃)或CVD(化学气相沉积)方法形成绝缘层216。第二金属电极220被形成得与衬底层222接触,并且可以是例如具有优良电接触的TiN/Al金属叠层。高掺杂的N型区域226(其可以通过离子注入形成)进一步确保N衬底222和电极220之间的良好电接触。因为P型层218被构建在N型硅衬底222上,所以它们一起形成二极管。因此,当电极212和220用于外部接触时,整个结构包括具有串联连接的PN二极管的a-Si电阻器件。图9描绘了类似于图8的结构310,主要差别是开始衬底的类型(其可以是p型衬底318)。在这种情形下,N型区域222然后形成在衬底218上(通过离子注入或扩散方法),其再次给a-Si电阻器件提供串联连接的PN二极管。
图10描绘了a-Si电阻器件400的一个示范性实施方式,所述a-Si电阻器件400包括一些被用来将a-Si结构编程到许多不同电阻中的任何一个从而允许器件中的多位或其它多级数字存储的控制电路。该结构400可以通过常规CMOS制造工艺构造。所述结构组合了a-Si电阻器件402(具有PN二极管)和可以充当栅偏置控制电阻器的FET 404。a-Si器件402包括嵌入顶部电极之下的绝缘层416中的a-Si纳米柱414,所述顶部电极可以是银或其它合适的金属。FET 404包括形成在栅氧化层432上的栅430。取决于在栅430施加的偏置,两个N型区域423、425之间的电阻可以被控制从而产生可变电阻器。N型区域425通过高掺杂N型区域427连接到第二金属电极420。结构400可以被制造在P型硅衬底418上。另一个P型区域421具有与P衬底418不同的电阻值以控制器件性能。多晶硅互连450通过连接两个N型区域422、423来桥接a-Si电阻器件402和N型FET 404。STI(浅沟槽隔离)440是标准CMOS制造技术,其可以抑制通过P衬底418的直流泄漏电流。如果有源衬底(本体)的厚度薄(<1μm),则器件400的结构可以如图11中所示被简化。这基本上包括从图10的器件400除去元件440、450、和423。衬底518可以是P型硅。N型区域522可以用作PN二极管的N部分以及FET的一部分,导致形成紧凑的器件尺寸。
除了使用增加的n型层以创建上述内置二极管之外,在此公开的基本a-Si电阻器件本身就能展现本征二极管特性。图12和13示出该二极管特性的实例。如这些图中所示,当存储器件处于它的接通状态时,电流可以仅在正偏置下而不在负偏置下流过器件。该本征二极管特性也可以被用来调节电流流动并且防止交叉条阵列中的串扰。可以通过控制a-Si沉积条件和/或通过控制编程电流来获得本征二极管特性。在不希望被限制到任何特殊操作理论的情况下,应当认为该本征特性的可能原因是在界面处的内建电场、和/或PECVD a-Si/多晶硅之间的浅陷阱电势。利用比通常的编程偏置小得多的偏置,自然拉回的Ag流动离子可以再次被注入到接近的界面,因此当利用小的正读取电压读取器件状态时仍旧可以获得接通状态。该过程不同于擦除过程,其中Ag流动离子被拉回到具有足够势垒能的另一个稳定位置。
将被理解的是,前述是本发明的一个或多个优选示范性实施例的描述。本发明并不限于在此公开的特定实施例,而是只由下面的权利要求限定。此外,包含在前面描述中的陈述涉及特定实施例并且不被看作是对本发明的范围或权利要求中使用的术语的定义的限制,除非其中术语或短语在上面被明确限定。各种其它实施例和对公开的实施例的各种改变或变型对本领域技术人员将变得显而易见。所有这样的其它实施例、改变、和变型旨在归入所附权利要求的范围内。
正如在本说明书和权利要求中所使用的,当结合一个或多个部件或其它项的列表使用时,术语“例如”、“举例来说”、“诸如”、和“类似”、以及动词“包括”、“具有”、“包含”、和它们的其它动词形式均被理解为开放式的,意思是所述列表将不被理解为排除其它、另外的部件或项。其它项将利用它们最广泛的合理意义来解释,除非它们在需要不同解释的上下文中使用。
Claims (30)
1.一种非易失性固态电阻器件,包括:
第一电极;
p型硅第二电极;以及
非结晶硅纳米结构,所述非结晶硅纳米结构电连接在所述电极之间使得所述纳米结构具有响应于通过所述电极施加到所述纳米结构的电压可调的电阻。
2.如权利要求1中所述的电阻器件,其中所述非结晶硅纳米结构包括非晶硅纳米结构。
3.如权利要求1中所述的电阻器件,其中所述硅第二电极包括p型掺杂的多晶硅电极。
4.如权利要求1中所述的电阻器件,其中所述硅纳米结构包括具有相对端面的柱,并且每个电极与所述端面中的不同端面接触。
5.如权利要求1中所述的电阻器件,其中所述硅纳米结构在所有三个空间尺寸上都是纳米级。
6.如权利要求1中所述的电阻器件,其中所述尺寸中的每一个小于100 nm。
7.如权利要求1中所述的电阻器件,进一步包括一个或多个与所述硅纳米结构电串联连接的电阻部件。
8.如权利要求7中所述的电阻器件,其中所述电阻部件包括控制电阻器。
9.如权利要求1中所述的电阻器件,进一步包括控制电路,所述控制电路包括所述一个或多个电阻部件,以及用于选择性地改变连接到所述硅纳米结构的串联电阻的数量的电路。
10.如权利要求1中所述的电阻器件,进一步包括用于在两个以上的电阻值之间调整所述硅纳米结构的电阻的控制电路。
11.如权利要求10中所述的电阻器件,其中所述控制电路提供与所述硅纳米结构串联连接的控制电阻,所述控制电路用于通过将控制电阻设置到相关电阻值来将硅纳米结构的电阻调整到所述电阻值中的任何一个。
12.如权利要求1中所述的电阻器件,进一步包括与所述p型第二电极接触的n型掺杂硅层,使得所述电阻器件包括与所述硅纳米结构串联的二极管。
13.如权利要求1中所述的电阻器件,其中所述第一电极是金属电极,在所述电极两端存在施加的电压的情况下,所述金属电极提供在所述硅纳米结构内形成细丝的金属离子。
14.如权利要求13中所述的电阻器件,其中所述第一电极包括银。
15.如权利要求13中所述的电阻器件,进一步包括在所述硅纳米结构附近位置与所述p型硅电极接触的第二金属电极。
16.如权利要求15中所述的电阻器件,其中所述第二金属电极与所述硅纳米结构间隔不超过100 nm。
17.一种具有至少一个包括权利要求1中所述的电阻器件的存储单元的数字非易失性存储器件。
18.如权利要求17中所述的存储器件,其中所述电阻器件的硅纳米结构是具有可调电阻的所述存储单元中的唯一硅纳米结构,并且其中可调电阻能够被设置为三个或更多个电阻中的任何一个,所述三个或更多个电阻中的每一个对应于不同的存储数字,由此所述存储单元能够进行多级数字存储。
19.如权利要求18中所述的存储器件,进一步包括用来根据将在存储单元中存储的数字设置可调电阻值的控制电路。
20.如权利要求19中所述的存储器件,其中控制电路包括与所述硅纳米结构串联的控制电阻。
21.一种具有包括权利要求1中所述的电阻器件的电互连的电子电路。
22.一种非易失性固态电阻器件,包括:
第一金属电极;
p型多晶硅电极;
至少部分地位于所述电极之间的绝缘层;
嵌入所述绝缘层中并且具有均连接到所述电极中的不同电极的相对端面的非晶硅结构,其中所述第一电极包括金属,所述金属在所述电极两端存在施加的电压的情况下提供在所述硅结构内形成细丝的金属离子,由此,所述硅结构展现出能够根据施加的电压被调整的电阻;以及
在离所述硅结构不超过100 nm的位置处与所述多晶硅电极接触的第二金属电极。
23.如权利要求22中所述的电阻器件,其中所述绝缘层包括旋涂玻璃层。
24.一种将非易失性固态电阻器件的电阻从开始的电阻值调整到最后的电阻值的方法,包括以下步骤:
将非易失性固态电阻器件与第二电阻器件串联电连接,第二电阻器件具有基于最后的电阻值选择的电阻;以及
在串联连接的电阻器件两端施加电压。
25.根据权利要求24的方法,其中所述施加步骤进一步包括至少部分地基于施加的电压的幅度、施加的电压的持续时间、或同时基于两者来设置最后的电阻值。
26.根据权利要求24的方法,其中所述施加步骤进一步包括通过在串联连接的电阻器件两端施加所选幅度和持续时间的电压来设置最后的电阻值。
27.根据权利要求24的方法,其中最后的电阻值是多个可选电阻值中的一个,并且其中电连接电阻器件的步骤进一步包括基于所述可选电阻值中的被选择的电阻值通过选择性地***或分接一个或多个与非易失性固态电阻器件串联的控制电阻器来电学上形成第二电阻器件。
28.根据权利要求24的方法,进一步包括通过施加相反极性的复位电压到非易失性固态电阻器件来将非易失性固态电阻器件复位到开始的电阻值的步骤。
29.一种将非易失性固态开关器件从断开状态调整到接通状态的方法,所述方法包括在非结晶硅纳米结构两端施加电压的步骤,其中施加的电压具有这样的幅度和持续时间:选择所述幅度和持续时间以便实现硅纳米结构从断开状态变换到接通状态的预定概率。
30.根据权利要求29的方法,其中所述施加步骤进一步包括响应于施加的电压在非结晶硅纳米结构内形成导电细丝的步骤。
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EP2342750A4 (en) | 2012-05-09 |
KR20110080153A (ko) | 2011-07-12 |
US20140153317A1 (en) | 2014-06-05 |
JP5702725B2 (ja) | 2015-04-15 |
JP2012505551A (ja) | 2012-03-01 |
WO2010042732A2 (en) | 2010-04-15 |
US20100085798A1 (en) | 2010-04-08 |
CN102177584B (zh) | 2014-05-07 |
WO2010042732A3 (en) | 2010-07-08 |
US8687402B2 (en) | 2014-04-01 |
EP2342750B1 (en) | 2015-01-28 |
EP2342750A2 (en) | 2011-07-13 |
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