CN102148994A

CN102148994A - Parallel inter-frame prediction coding method

Info

Publication number: CN102148994A
Application number: CN 201010106225
Authority: CN
Inventors: 杨华岚
Original assignee: CHENGDU SHIJIA ELECTRONICS INDUSTRIAL Co Ltd
Current assignee: Chengdu Bosheng Information Technology Co., Ltd.
Priority date: 2010-02-04
Filing date: 2010-02-04
Publication date: 2011-08-10

Abstract

The invention discloses a parallel inter-frame prediction coding algorithm, which is provided with real time coding capacity, and can be applied to various portable applications. The algorithm comprises mode selection of various inter-frame prediction modes and I-frame coding, and covers all the inter-frame prediction characteristics of H.264. Tested after realization of Verilog HDL hardware, a system can realize real-time CIF (common intermediate format) coding of a main frequency of 71MHz; and an average frame rate can reach 35FPS (frame/second).

Description

A kind of parallel infra-frame prediction frame coding method

Technical field

The present invention relates to field of video encoding, the hardware designs algorithm that particularly a kind of parallel infra-frame prediction frame is encoded.

Background technology

H.264 be present up-to-date international video compression standards.In all video encoding standards, H.264 have the highest code efficiency, mainly be because more accurate infra-frame prediction (intra prediction) and the inter prediction (inter prediction) that adopts.But the raising of these code efficiencies all can be accompanied by the raising of encoder complexity, for realizing that real time algorithm has proposed new challenge.

In intraframe predictive coding system H.264, the pixel of rebuilding behind the face code before prediction data is used is as predicted value.Initial data obtains residual error with subtracting each other by the prediction data of using intraframe prediction algorithm to produce, and system is to residual coding, thereby has improved code efficiency.For brightness, infra-frame prediction has H.264 adopted 4X4 and two kinds of Forecasting Methodologies of 16X16 to produce prediction data, and wherein the 4X4 prediction has nine kinds of Forecasting Methodologies (predictive mode is seen Fig. 1), and 16X16 has 4 kinds of Forecasting Methodologies; For colourity, H.264 one have 4 kinds of predictive modes, the same with the luma prediction modes of 16X16.

Summary of the invention

In the present invention, we have proposed a kind of based on the real-time I frame coded system of low cost H.264, comprise and overlap the hardware realization of intraframe prediction algorithm cheaply, and I frame encryption algorithm hardware is realized cheaply.

The hardware implementations of intraframe prediction algorithm of the present invention is as follows:

1.1. master-plan as shown in Figure 2.Brightness and colorimetric prediction macro block by this hardware produce, parallel processing, thereby can obtain better throughput.Wherein upper part calculates the 16x16 prediction data of brightness and the prediction data of colourity, and lower part calculates the prediction data of brightness 4x4.

Wherein the pixel value of the current macro register holds current macro of upper part needs 384Byte so comprise colourity and brightness.The current macro register of lower part only needs 256Byte, because only need preserve luminance pixel values.The prediction buffer memory of upper part has comprised 384Byte, and the prediction buffer memory of lower part only needs 16Byte, data reconstruction around the contiguous buffer memory current macro of the overall situation.The contiguous buffer memory in this locality of lower part is deposited 4x4 and is predicted needed neighboring pixel, and the pixel A that comprises among the figure one arrives M, altogether 16 Byte.

1.2.4x4 the hardware configuration of luma prediction:

We find that (A+B), (B+C), (C+D), (D+E), (E+F), (F+G), (G+H), (J+K), (I+J), (M+I), (M+A) etc. are some common factors of these pattern the insides from Fig. 1, calculate these common factors, leave in the register standby.

In our hardware was realized, the critical path of the luma prediction pixel of generation 4x4 as shown in Figure 3.Registers group REG_L0_0 wherein deposits 12 common factors to REG_L0_11, registers group REG_L1_0 to REG_L1_11 deposit that other will use to intermediate object program.If top adjacent block and left side adjacent block all exist, so, entire I ntra4x4 predicted 165 cycles consuming time.Since the computation sequence of various patterns can not exert an influence to the result, can allow the input of adder keep so just can reducing the switching of adder input, thereby having reduced power consumption continuously.

1.3.16x16 the hardware configuration of luma prediction and colorimetric prediction:

Level, vertical and these three kinds of patterns of DC can use adder and shifter directly to realize.And the Plane pattern see Fig. 4 for details.The critical path of the critical path of 16x16 prediction and 4x4 prediction is similar.At first calculate C0, (C0+b), (C0+2b) and (C0+3b), and the result is kept in the buffer memory.Utilize these intermediate object programs to produce prediction data then.If adjacent top data and left data all exist, finishing the 16X16 prediction so needs 1127 cycles, and wherein the plane pattern needs 340 cycles.For colorimetric prediction, consistent with brightness 16x16 pattern, so by having used identical hardware configuration, under this structure, the prediction of finishing colourity needs 302 cycles.

The hardware implementations of I frame encryption algorithm of the present invention is as follows:

2.1 mode selection module hardware configuration

Mode selection module hardware comprises infra-frame prediction, model selection, Hadamard conversion.Whole hardware module is by two part parallel computings: a part is calculated brightness 16x16 pattern and colourity pattern, and a part is calculated the 4x4 luminance patterns and selected in addition.See Fig. 5.

2.2 residual error coefficient encoder hardware structure:

The residual error coefficient encoder comprises dct transform, quantification, inverse dct transform, inverse quantization and entropy coding part, sees Fig. 6.

Encoder shown in the present is after using Verilog RTL to realize, integrated operation on Xilinx Vertex II, under the dominant frequency of 71MHz, average 5150 cycles just can be finished the processing of a macro block, reach the speed of CIF sequence average 35 frame per seconds on the whole.

Description of drawings

Do some explanations below in conjunction with accompanying drawing.

H.264, nine kinds of patterns of the Intra 4x4 that Fig. 1 defines.

The overall design drawing of Fig. 2 intraframe prediction algorithm.

The critical path figure of the luma prediction pixel of Fig. 3 4x4.

The detailed design figure of Fig. 4 Plane pattern.

Wherein, p represents neighbor, and the Clip1 function is transformed into input between 0 to 255.Clip1 (x): clip1 (x)=255 when x＞255; When x＜0, clip1 (x)=0; Clip1 (x)=x when x is worth for other.

Fig. 5 mode selection module hardware designs figure.

Fig. 6 residual error coefficient encoder hardware design drawing.

Specific implementation process

To the hardware designs algorithm of this infra-frame prediction frame coding, concrete implementation step is described below:

1.1 carry out master-plan according to Fig. 2.Brightness and colorimetric prediction macro block by this hardware produce, parallel processing, thereby can obtain better throughput.Wherein upper part calculates the 16x16 prediction data of brightness and the prediction data of colourity, and lower part calculates the prediction data of brightness 4x4.

1.2, finish the hardware designs of 4x4 luma prediction according to the critical path (as shown in Figure 3) of the luma prediction pixel that produces 4x4.Registers group REG_L0_0 wherein deposits 12 common factors to REG_L0_11, registers group REG_L1_0 to REG_L1_11 deposit that other will use to intermediate object program.

1.3 because the critical path of the critical path of 16x16 prediction and 4x4 prediction is similar, finish the hardware designs of 16x16 luma prediction and colorimetric prediction according to Fig. 3, build level, vertical, these three kinds of patterns of DC with adder and shifter, build the Plane pattern according to Fig. 4.

2.1, finish the mode selection module hardware designs according to Fig. 5.This part comprises infra-frame prediction, model selection, Hadamard conversion, and by two part parallel computings: a part is calculated brightness 16x16 pattern and colourity pattern, and a part is calculated the 4x4 luminance patterns and selected in addition.

2.2, finish the design of residual error coefficient encoder hardware according to Fig. 6.This part comprises dct transform, quantification, inverse dct transform, inverse quantization and entropy coding part.

Claims

1. the hardware designs algorithm of a parallel infra-frame prediction frame coding is characterized in that, comprises as the lower part:

1.1) master-plan of intraframe prediction algorithm hardware.

1.2) hardware designs of intraframe prediction algorithm 4x4 luma prediction.

1.3) hardware designs of intraframe prediction algorithm 16x16 luma prediction and colorimetric prediction.

2.1) the mode selection module hardware designs of I frame encryption algorithm.

2.2) design of the residual error coefficient encoder hardware of I frame encryption algorithm.

2. the hardware designs algorithm that parallel infra-frame prediction frame as claimed in claim 1 is encoded is characterized in that described step 1.1) middle intraframe prediction algorithm hardware master-plan:

Master-plan as shown in Figure 2.Brightness and colorimetric prediction macro block are by this hardware generation, parallel processing, and wherein upper part calculates the 16x16 prediction data of brightness and the prediction data of colourity, and lower part calculates the prediction data of brightness 4x4.

3. the hardware designs algorithm of parallel infra-frame prediction frame coding as claimed in claim 1 is characterized in that described step 1.2) in the hardware designs of intraframe prediction algorithm 4x4 luma prediction:

In our hardware was realized, the critical path of the luma prediction pixel of generation 4x4 as shown in Figure 3.Registers group REG_L0_0 wherein deposits 12 common factors to REG_L0_11, registers group REG_L1_0 to REG_L1_11 deposit that other will use to intermediate object program.

4. the hardware designs algorithm of parallel infra-frame prediction frame coding as claimed in claim 1 is characterized in that described step 1.3) in the hardware designs of intraframe prediction algorithm 16x16 luma prediction and colorimetric prediction:

Because the critical path of the critical path of 16x16 prediction and 4x4 prediction is similar, finish the hardware designs of 16x16 luma prediction and colorimetric prediction according to Fig. 3, build level, vertical, these three kinds of patterns of DC with adder and shifter, build the Plane pattern according to Fig. 4.

5. the hardware designs algorithm of parallel infra-frame prediction frame coding as claimed in claim 1 is characterized in that described step 2.1) in the mode selection module hardware designs of I frame encryption algorithm:

According to Fig. 5, finish the mode selection module hardware designs.This part comprises infra-frame prediction, model selection, Hadamard conversion, and by two part parallel computings: a part is calculated brightness 16x16 pattern and colourity pattern, and a part is calculated the 4x4 luminance patterns and selected in addition.

6. the hardware designs algorithm of parallel infra-frame prediction frame coding as claimed in claim 1 is characterized in that described step 2.2) in the residual error coefficient encoder hardware design of I frame encryption algorithm:

According to Fig. 6, finish the design of residual error coefficient encoder hardware.This part comprises dct transform, quantification, inverse dct transform, inverse quantization and entropy coding part.