CN102079502A - MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof - Google Patents
MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof Download PDFInfo
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Abstract
The invention discloses an MEMS (micro electro mechanical system) device and a wafer-level vacuum packaging method thereof, wherein the MEMS device is composed of a glass substrate (1), a silicon wafer sensitive structure layer with a sealing ring (2), and a silicon cap (9), and the MEMS device is characterized in that at least two silicon islands (11) are arranged in the silicon wafer sensitive structure layer, the bottom of each silicon island (11) is connected with the glass substrate (1) and an electrode lead (8), a press welding spot (6) is respectively arranged on the top of each silicon island (11); parts, corresponding to the silicon islands, on the silicon cap are respectively provided with a press welding spot cavity (7), so that the press welding spots (6) are arranged in the press welding spot cavities (7); and the periphery of each press welding spot cavity is provided with a press welding spot sealing ring (12) which is connected and matched with the top of each silicon island, and the periphery of each press welding spot sealing ring is provided with a press welding spot isolation channel (5). The MEMS device and the wafer-level vacuum packaging method thereof disclosed by the invention have the advantages that the technical problem of electrical isolation between the leakproof structure of the press welding spot and the press welding spots caused by that an electrode is led in the surface of the structural layer of the device from the substrate is avoided, so that the vacuum packaging structure of the MEMS device disclosed by the invention is reasonable in design, simple in process, long in vacuum retention time, reliable in performance and versatile, thereby reducing the cost for vacuum packaging.
Description
Technical field
The invention belongs to the micro-electronic mechanical skill field, relate to a kind of MEMS device and MEMS device disc grade vacuum packaging method.
Background technology
MEMS (the abbreviation of Micro Electro Mechanical systems, being microelectromechanical systems) device comprises some moving parts usually, these movable members are very fragile, be subjected to the influence of the factor such as dust, steam in scribing and the assembling process easily, cause the decline of device destruction or overall performance, also have a lot of MEMS devices need be operated in the vacuum environment simultaneously, reduce air damping, improve the quality factor q value of device.As mems accelerometer, gyroscope, micro-resonator, diaphragm pressure sensor, RF MEMS element, vacuum field transmitter and some optical MEMS devices etc.The quality of Vacuum Package has directly determined the performance of this class device, thereby it becomes particularly important.
The Vacuum Package of MEMS device disc grade is meant with the silicon wafer to be that unit carries out encapsulation operation, and being connected and waiting all packaging process between chip and the encapsulation is that unit is operated at silicon wafer all, compares with single-chip, saved the cost of encapsulation greatly.In MEMS wafer level Vacuum Package, mainly be adopt that anode linkage, silicon-silicon bond close, gold-silicon bonding, middle binder bonding wafer bonding technology such as (SU-8 glue, BCB glue, glass pastes etc.).With being sealed in the corresponding vacuum cavity of the chip that processed on the silicon chip, make chip operation in vacuum state, be not subjected to external influence.The adverse effect that can also protect simultaneously chip not caused by later process (as scribing etc.).
The particularity of MEMS encapsulation has increased the difficulty and the cost of MEMS encapsulation greatly, and the MEMS packaging cost accounts for 50%～90% of whole M EMS cost, and encapsulation technology becomes the bottleneck of MEMS development.Solve MEMS encapsulation problem is the research emphasis of MEMS technical field always.
MEMS device disc grade vacuum sealing technique mainly contains the MEMS device of making at surface treatment, often adopts the more of wafer level Vacuum Package research that silicon-glass or silicon-silicon realizes.Adopt in addition glass-silicon bonding body silicon technology is carried out the wafer level Vacuum Package of MEMS device, it mainly contains employing and beats the encapsulating structure method of lead hole in the substrate glass back, but this complex process, cost height, vacuum retention time are short.The metal crimp solder joint of device will be distributed on the device surface under normal conditions.The method for packing that provides as following patent application:
1, the patent No.: 200510102941.7, patent name: wafer-level vacuum encapsulating method.Electrode is on substrate, on the cover board dig through hole, under vacuum environment, in capping, evenly be coated with one deck encapsulating material, make encapsulating material fill up each through hole, for each through hole of sealing, make the micro-structured component in each space be positioned at a vacuum state,, finish one one single encapsulation crystal grain through cutting more again with the encapsulating material slaking.
2, the patent No.: 200710121384.2, patent name: a kind of microelectromechanical systems wafer level Vacuum Package and flip chip method.Be mainly used in the MEMS device of surface treatment processing, adopt the sheet glass block to encapsulate, need not consider electrode draw and electrode between electricity isolate and sealing problem.
3, the patent No.: 200910306690.2, patent name: wafer-level vacuum encapsulation wire interconnecting structure of micro electro mechanical system and manufacture method thereof.Open the hole on the silicon substrate, through hole and silicon substrate surface have insulating barrier, and metal electrode passes through hole and with its sealing, has the intermediate layer between metal electrode and the insulating barrier, and cover plate and silicon substrate bonding are finished Vacuum Package.
Summary of the invention
Purpose of the present invention is exactly to overcome existingly to open the shortcoming that the encapsulating structure method of fairlead exists, a kind of MEMS device architecture that provides and MEMS device disc grade vacuum packaging method from the substrate glass back.
To achieve these goals, the present invention has adopted following technical scheme:
A kind of MEMS device, form by glass substrate, the silicon chip sensitive structure layer that has seal ring structure and silicon cap, it is characterized in that: be provided with at least two silicon island according to designed pressure welding point quantity and position in the silicon chip sensitive structure layer, the isolated mutually and insulation of each silicon island and other parts of sensitive structure layer, the following of each silicon island is connected with glass substrate and the electrical leads that is arranged on the glass substrate respectively, and each is respectively equipped with pressure welding point above the silicon island; Be respectively equipped with three pressure welding point cavitys with each silicon island correspondence position on the silicon cap, pressure welding point cavity periphery is provided with the pressure welding point sealing ring and is connected cooperation above the silicon island, and pressure welding point sealing ring periphery is provided with the pressure welding point isolation channel, and pressure welding point is in the pressure welding point cavity.
A kind of MEMS device disc grade vacuum packaging method is characterized in that comprising the steps:
(1) silicon chip sensitive structure layer anchor point made: utilize photoetching process, ICP to carve silicon technology, produce silicon island, sealing ring and anchor point on silicon chip sensitive structure layer, and form corresponding shallow channel;
(2) make contact conductor on the glass substrate: splash-proofing sputtering metal aluminium on glass substrate, utilize photoetching process photoetching metal lead wire, form contact conductor after corroding unnecessary metal;
(3) silicon-Bo electrostatic bonding: silicon chip sensitive structure layer and glass substrate are aimed at through plasma treatment, dual surface lithography, adopt silicon-Bo static bonding process, finish being connected of silicon chip sensitive structure layer and glass substrate;
(4) make the metal electrode pressure welding point on silicon chip sensitive structure layer: splash-proofing sputtering metal aluminium on silicon chip sensitive structure layer forms the metal electrode pressure welding point through photoetching, quarter behind the aluminium;
(5) structure discharges: adopt photoetching process, ICP deep etching technology, the shallow slot of the silicon island part of silicon chip sensitive structure layer is carved logical, and the silicon chip sensitive structure discharged, form the movable sensitive structure parts;
(6) making of silicon cap: silicon chip is carried out high-temperature thermal oxidation, LTO oxidation formation oxide layer, deposition one deck gold on this oxide layer, adopt photoetching process, etching gold, carve oxide layer, ICP etch silicon, form the corresponding pressure welding point isolation channel of shallow slot, pressure welding point sealing ring and pressure welding point cavity with silicon chip sensitive structure layer; And the Sensitive Apparatus cavity corresponding with Sensitive Apparatus;
(7) silicon cap and silicon chip sensitive structure layer gold-silicon eutectic bonding: the silicon cap is aimed at silicon chip sensitive structure layer dual surface lithography, adopted vacuum gold-silicon eutectic bonding technology, finish the encapsulation of upper silicon cap and silicon chip sensitive structure layer;
(8) etching is exposed pressure welding point: adopt photoetching process, double-sided alignment photoetching, ICP deep etching silicon etch metal crimp solder joint cavity in the silicon cap.
The present invention is structural design and the manufacturing by silicon island, sealing ring and lid silicon cap, when solving the MEMS device disc grade Vacuum Package of body silicon MEMS technology manufacturing, electrode is drawn out to a difficult problem on device architecture top layer or the silicon cap plate from glass substrate, has realized that interelectrode electricity is isolated and MEMS device disc grade high vacuum encapsulates.This technical matters is simple, realizes easily, need not add any processing step on the basis of bulk silicon technological, has reduced packaging cost, and dependable performance satisfies the requirement of MEMS component vacuum package application.
Key problem in technology of the present invention is the structural design of wafer level Vacuum Package, mainly comprises the structural design of silicon island, the structural design of sealing ring and the structural design of silicon cap.By these effective structural designs, realized distribution again, electrical isolation and the wafer level Vacuum Package of electrode.
The invention has the advantages that: avoided that electrode is incorporated into the device architecture laminar surface from underlay substrate in the prior art, and when blocking a shot Vacuum Package to the end, to the design of Sealing Structure of pressure welding point and the technical problems such as electricity isolation between pressure welding point.Make that vacuum encapsulation structure of the present invention is reasonable in design, technology is simple, vacuum retention time length, dependable performance, have versatility, has reduced the Vacuum Package cost.
Four description of drawings
The present invention has 5 accompanying drawing.
Fig. 1 is a MEMS device disc grade encapsulating structure generalized section;
Fig. 2 is silicon island and a seal ring structure schematic diagram in the silicon chip sensitive structure layer;
Fig. 3 is the planar structure schematic diagram behind silicon chip sensitive structure layer and the glass substrate silicon-Bo bonding;
Fig. 4 is a silicon cap schematic diagram;
Fig. 5-1---Fig. 5-9 is that MEMS device disc grade encapsulating structure is made and encapsulation process technological process generalized section.
The specific embodiment
One, the structure of MEMS device:
Referring to accompanying drawing 1, a kind of MEMS device provided by the invention on a slice silicon wafer, is produced one group of MEMS device, and each MEMS device is made up of glass substrate 1, the silicon chip sensitive structure layer that has sealing ring 2 and silicon cap 9.
(silicon island is according to the corresponding setting of pressure welding point quantity and position to be provided with three silicon island 11 in the silicon chip sensitive structure layer, present embodiment is designed to three silicon island), each silicon island 11 is isolated mutually and insulation with other parts of sensitive structure layer, the following of each silicon island 11 is connected with glass substrate 1 and the electrical leads 8 that is arranged on the glass substrate respectively, and each is respectively equipped with pressure welding point 6 above the silicon island 11; Be respectively equipped with a pressure welding point cavity 7 with each silicon island correspondence position on the silicon cap, pressure welding point cavity periphery is provided with pressure welding point sealing ring 12 and is connected cooperation above the silicon island, pressure welding point sealing ring periphery is provided with pressure welding point isolation channel 5, and pressure welding point 6 is in the pressure welding point cavity 7.
In conjunction with Fig. 1, shown in Figure 2, silicon chip sensitive structure layer periphery is that distribution triangular in shape is provided with three silicon island 11 in sealing ring 2, the sealing ring 2, and silicon island 11 is isolated mutually and insulation with other parts of sensitive structure layer.Sealing ring will surround all device architecture parts, guarantees that the MEMS device is in internal cavities.
In conjunction with Fig. 1, shown in Figure 3, the following of each silicon island 11 is connected with glass substrate 1 and the electrical leads 8 that is arranged on the glass substrate respectively.The effect of silicon island is by silicon-Bo bonding techniques, and the contact conductor of making on the glass substrate 8 is drawn out on the device architecture surface, realizes being electrically connected and the electricity isolation.The structure of silicon island and anchor point are on same lithography mask version.On the device architecture layer, silicon island and inner sensitive structure partly disconnect.
In conjunction with Fig. 1, shown in Figure 4, the structural design of silicon cap 9: designed two kinds of cavitys on the silicon cap, the one, the cavity 9a of containment device sensitive structure 10 parts, the 2nd, the cavity 7 of the metal crimp solder joint on the containment device structure sheaf, promptly the metal crimp solder joint is distributed on the silicon island.In design, the cavity structure size of the metal crimp solder joint on the containment device structure sheaf is bigger than metal crimp solder joint, but littler than silicon island size.Surrounded simultaneously a circle electrically isolating ring 12 outside each pressure welding point cavity, shading ring 12 peripheries are provided with a circle isolation channel 5, realize that the electricity between the pressure welding point is isolated.
Two, MEMS device and wafer-level encapsulation method thereof:
A kind of MEMS device disc grade method for packing is characterized in that comprising the steps:
(1), silicon chip sensitive structure layer anchor point made: shown in Fig. 5-1, adopt N (100) silicon chip and Pyrex7740 glass and cleaning treatment, utilize photoetching process, ICP to carve silicon technology, on silicon chip sensitive structure layer, produce silicon island 11, sealing ring 2, anchor point 13 and sealing ring 2, and form corresponding isolation channel 5, cavity 9a;
(2), make contact conductor on the glass substrate: shown in Fig. 5-2, splash-proofing sputtering metal aluminium on glass substrate 1 utilizes photoetching process photoetching metal lead wire, forms contact conductor 8 after corroding unnecessary metal;
(3), silicon-Bo electrostatic bonding: shown in Fig. 5-3, silicon chip sensitive structure layer and glass substrate 1 aimed at through plasma treatment, dual surface lithography, adopts silicon-Bo static bonding process, finishes being connected of silicon chip sensitive structure layer and glass substrate;
(4), make the metal electrode pressure welding point on silicon chip sensitive structure layer: shown in Fig. 5-4, splash-proofing sputtering metal aluminium on silicon chip sensitive structure layer forms metal electrode pressure welding point 6 through photoetching, quarter behind the aluminium;
(5), structure discharges: shown in Fig. 5-5, adopt photoetching process, ICP deep etching technology, the isolation channel of the silicon island part of silicon chip sensitive structure layer carved logically form complete pressure welding point isolation channel 5, and the silicon chip sensitive structure is discharged, form movable sensitive structure parts 10;
(6), the making of silicon cap:
Shown in Fig. 5-6, the silicon chip of making silicon cap 9 is carried out high-temperature thermal oxidation, LTO oxidation formation oxide layer 4, deposition one deck gold 3 on this oxide layer;
Shown in Fig. 5-7, adopt photoetching process, etching gold, carve oxide layer, ICP etch silicon, form and the corresponding pressure welding point isolation channel 5 of silicon chip sensitive structure layer, pressure welding point sealing ring 12 and pressure welding point cavity 7; And the Sensitive Apparatus cavity 9a corresponding with Sensitive Apparatus;
(7), silicon cap and silicon chip sensitive structure layer gold-silicon eutectic bonding: shown in Fig. 5-8, silicon cap 9 is aimed at silicon chip sensitive structure layer dual surface lithography, adopted vacuum gold-silicon eutectic bonding technology, finish the encapsulation of upper silicon cap and silicon chip sensitive structure layer;
(8) etching is exposed pressure welding point: shown in Fig. 5-9, adopt photoetching process, double-sided alignment photoetching, ICP deep etching silicon etch metal crimp solder joint cavity 7 in silicon cap 9.
Through above-mentioned production process, realize the wafer level Vacuum Package of MEMS device.The upper strata is that silicon cap, intermediate layer are that device architecture part, lower floor are glass, and its structural profile schematic diagram as shown in Figure 1.
Claims (2)
1. MEMS device, form by glass substrate (1), the silicon chip sensitive structure layer that has sealing ring (2) and silicon cap (9), it is characterized in that: be provided with at least two silicon island (11) in the silicon chip sensitive structure layer, (the 11 isolated mutually and insulation of each silicon island with other parts of sensitive structure layer, the following of each silicon island (11) is connected with glass substrate (1) and the electrical leads (8) that is arranged on the glass substrate respectively, is respectively equipped with pressure welding point (6) above each silicon island (11); Be respectively equipped with a pressure welding point cavity (7) with each silicon island correspondence position on the silicon cap, pressure welding point (6) is in the pressure welding point cavity (7), pressure welding point cavity periphery is provided with pressure welding point sealing ring (12) and is connected cooperation above the silicon island, and pressure welding point sealing ring periphery is provided with pressure welding point isolation channel (5).
2. a MEMS device disc grade vacuum packaging method is characterized in that comprising the steps:
(1) silicon chip sensitive structure layer anchor point made: utilize photoetching process, ICP to carve silicon technology, on silicon chip sensitive structure layer, produce silicon island (11), sealing ring (2) and anchor point (13), and form corresponding Sensitive Apparatus cavity (
9A);
(2) make contact conductor (8) on the glass substrate: splash-proofing sputtering metal aluminium on glass substrate, utilize photoetching process photoetching metal lead wire, form contact conductor (8) after corroding unnecessary metal;
(3) silicon-Bo electrostatic bonding: silicon chip sensitive structure layer and glass substrate 1 aimed at through plasma treatment, dual surface lithography, adopts silicon-Bo static bonding process, finishes being connected of silicon chip sensitive structure layer and glass substrate;
(4) make the metal electrode pressure welding point on silicon chip sensitive structure layer: splash-proofing sputtering metal aluminium on silicon chip sensitive structure layer forms metal electrode pressure welding point (6) through photoetching, quarter behind the aluminium;
(5) structure discharges: adopt photoetching process, ICP deep etching technology, the shallow slot of the silicon island part of silicon chip sensitive structure layer is carved logical, and the silicon chip sensitive structure discharged, form movable sensitive structure parts (10);
(6) making of silicon cap: silicon chip is carried out high-temperature thermal oxidation, LTO oxidation formation oxide layer (4), go up deposition one deck gold (3) in this oxide layer (4), adopt photoetching process, etching gold, carve oxide layer, ICP etch silicon, the corresponding pressure welding point isolation channel of shallow slot (5), pressure welding point sealing ring (12) and the pressure welding point cavity (7) of formation and silicon chip sensitive structure layer, and the Sensitive Apparatus cavity (9a) corresponding with Sensitive Apparatus;
(7) silicon cap and silicon chip sensitive structure layer gold-silicon eutectic bonding: the silicon cap is aimed at silicon chip sensitive structure layer dual surface lithography, adopted vacuum gold-silicon eutectic bonding technology, finish the encapsulation of upper silicon cap and silicon chip sensitive structure layer;
(8) etching is exposed pressure welding point: adopt photoetching process, double-sided alignment photoetching, ICP deep etching silicon etch metal crimp solder joint cavity (7) in the silicon cap.
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