CN101131592A - Band-gap reference source with high power supply restraint - Google Patents
Band-gap reference source with high power supply restraint Download PDFInfo
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- CN101131592A CN101131592A CNA2007100532944A CN200710053294A CN101131592A CN 101131592 A CN101131592 A CN 101131592A CN A2007100532944 A CNA2007100532944 A CN A2007100532944A CN 200710053294 A CN200710053294 A CN 200710053294A CN 101131592 A CN101131592 A CN 101131592A
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Abstract
There is a sort of reference source which has the crack by checking the high electrical source, and it consists of the self-polarization circuit, the regulating circuit, the kernel circuit which has the crack, and the startup circuit. The IPTAT generating circuit of the kernel circuit which has the crack makes the collector current of the Q1 and Q2 of the NPN pipe to equal by that the degenerative feedback which is magnified adjusts its quiescent point, the IPTAT current and the VBE of the Q8 of the NPN transistor which has the negative temperature coefficient in the constant-current circuit are progressed the first compensation of the temperature, at the same time they debase the temperature coefficient. The constant-current circuit produces the polarization by itself, and provides the polarization current to the IPTAT generating current. The operational amplifier circuit advances the plus for the two-stage operational amplifier, the compensation current progresses the frequency compensation for the two-stage operational amplifier. The generating circuit removes the dependency of the reference export VREF to supply voltage by negative feedback effect in order advance the PSRR. The startup circuit removes the degeneration polarization point and it drives the self-polarization circuit to work. The self-polarization circuit provides the polarization voltage for the regulating circuit. The circuit configuration of this invention is simple and new, it does not need the external polarization, the area of this circuit is small, and it has the good temperature coefficient.
Description
Technical Field
The invention belongs to the field of digital-analog hybrid integrated circuits, in particular to a Bi-CMOS band-gap reference source with low power consumption and high power supply rejection ratio, which is a band-gap reference voltage source with simple structure, low power consumption and high power supply rejection ratio, and is particularly suitable for being applied to analog-to-digital converters (ADC) and digital-to-analog converters (DAC) of hybrid integrated circuits.
Background
In the design of ADC and DAC mixed integrated circuits, a high-performance Reference source (Reference) integrated on a chip is indispensable. With the complexity of circuit systems and the refinement of digital-analog mixed signals, the requirements on hybrid integrated circuits such as ADCs and DACs are increasing, and the requirements on reference sources, particularly power supply rejection thereof, are also increasing.
The reference voltage source is manufactured by utilizing the reverse breakdown characteristic of the diode conventionally. The diode is matched with the current-limiting resistor, and the current flowing through the diode is adjusted to counteract the influence of the change of the power supply voltage on the current-limiting resistor. However, this requires a high supply voltage to reverse-breakdown the diode, and more importantly, it has a large dependence on the supply voltage, and the supply rejection ratio (PSRR) is not ideal. Also using positive V BE To generate the reference voltage, but this would make the temperature coefficient large. The bandgap reference source is favored because of its advantages such as low temperature coefficient, high power supply rejection ratio, and stable output.
In order to reduce the temperature coefficient of the bandgap, one usually achieves the objective by a first-order compensation of temperature. The circuit structure of the conventional bandgap reference source is shown in fig. 1, and its power supply rejection performance is not very good, the precision is not very high, and it is very sensitive to the offset of the operational amplifier.
Disclosure of Invention
The invention aims to provide a bandgap reference source with high power supply rejection, which has the advantages of low power consumption and high power supply rejection.
The band-gap reference source with high power supply rejection comprises a self-biasing circuit, an adjusting circuit, a band-gap core circuit and a starting circuit; the band gap core circuit comprises NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP transistors Q3, Q4 and Q5, resistors R1, R2, R3 and R4 and a capacitor C1; bases of NPN transistors Q1 and Q2 are respectively connected with two ends of a resistor R3, emitters are connected together and are connected to a resistor R4 together, and the other end of the resistor R4 is grounded; the collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the collectors of the NPN transistor Q2 and the PNP transistor Q4 are connected together; base potentials of the NPN transistor Q2 and the PNP transistor Q4 are the same, and emitter potentials are connected to the reference output voltage V REF The above step (1); the emitter of PNP transistor Q5 is connected to reference output voltage V REF The upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode is connected with the base electrode of the NPN transistor Q8, the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and are commonly connected with the base electrode of the NPN transistor Q7; the emitter and base of NPN transistor Q7 are respectively grounded and reference output voltage V REF (ii) a The collector and the base of the NPN transistor Q8 are connected together and connected to the resistor R3; one end of the resistor R2 is connected with the resistor R3, and the other end is connected with the reference output voltage V REF C, removing; one end of the resistor R1 is connected with the base electrode of the NPN transistor Q7, and the other end is connected with the capacitor C1; the other end of the capacitor C1 is connected with the base electrode of the PNP transistor Q5; reference output voltage V REF The output end is connected with a peripheral circuit;
starting circuit at supply voltage V IN When the power is on, the power works, current is generated and is transmitted to the self-bias circuit to drive the self-bias circuit to be conducted; the self-bias circuit starts to conduct after receiving the current provided by the starting circuitSelf-bias to generate the voltage V IN Irrelevant bias voltage is transmitted to the adjusting circuit, and the starting circuit is closed at the same time; after receiving the bias voltage output by the self-bias circuit, the adjusting circuit generates constant current through self adjustment and outputs the constant current to the band gap core circuit; the band-gap core circuit generates a band-gap reference voltage V through the operation of the band-gap core circuit after receiving the constant current provided by the adjusting circuit REF And takes it as the output of the whole band-gap reference source.
Compared with the prior art, the core circuit of the band-gap reference source has extremely high Power Supply Rejection Ratio (PSRR) through the adjusting circuit outside the core circuit and the local power supply V in the core circuit REF To be realized. In addition, the core circuit in the invention has simple structure, consumes very small current under the same input voltage, and belongs to a low-power-consumption band-gap reference source. Under the Bi-CMOS process, the CMOS process is carried out,the circuit structure of the traditional band-gap reference source has a large temperature coefficient through first-order compensation of temperature, and in the circuit structure of the band-gap reference source, a novel I is utilized PTAT The circuit generates a structure, so that the temperature coefficient is greatly reduced. In addition, the invention adds a self-bias circuit, an adjusting circuit and a starting circuit, wherein the accurate duplication of the current of two branches in the self-bias circuit ensures the independence of the power supply voltage, thereby allowing the large-amplitude change of the input voltage; the adjusting circuit is biased by a self-biasing circuit and provides an external power supply for the band-gap core circuit, so that the band-gap core circuit is less influenced by an input voltage (power supply voltage). In order to avoid the existence of a degenerated point in the self-bias circuit, the starting circuit is introduced, and the starting circuit is closed after the self-bias circuit is started, so that the normal operation of the circuit is ensured, and the power consumption of the circuit is greatly reduced.
Exemplary bandgap structure in fig. 1, PSRR is reduced due to mismatch of operational amplifiers, and accuracy is reduced due to limited gain. In the bandgap structure diagram 3 of the present invention, the two stages of operational amplifiers are used to provideThe gain is high, and the precision is further improved; the offset of the operational amplifier can be reduced by using single-ended input; the frequency compensation of the compensation circuit 8 is used to improve the phase margin of the operational amplifier itself, thereby ensuring its stability. The specific analysis is as follows: the PNP transistor Q5 and the NPN transistor Q6 form a first stage amplifier-a common emitter amplifier, wherein the PNP transistor Q5 is of a PNP type because the Y point potential is biased to ensure V X ＝V Y . The NPN transistor Q6 is an active load of the PNP transistor Q5, which utilizes the characteristic of high dynamic impedance of the active load to increase the gain, and in addition, the static power consumption of the active load is also small. The NPN transistor Q7 is a common emitter amplifier, and the cascade connection of the two common emitter amplifiers greatly improves the gain and the precision. One of the great roles of the operational amplifier is that its deep negative feedback makes the output independent of the input, and here, the feedback polarity of the operational amplifier is briefly explained: when there is an instantaneous positive signal at point Y, the first stage operational amplifier and the second stage operational amplifier are both common emitters, so that after passing through the two stages of operational amplifiers, the signal is still positive, the positive signal is applied to the resistor R3, and the base voltage of the NPN transistor Q1 is changed into delta V BE Base voltage of NPN transistor Q2 is changed into delta V BE +ΔIR 3 Therefore, the change of the base of the NPN transistor Q2 has far larger influence on the Y point than the change of the base of the NPN transistor Q1; moreover, the base and the Y point of the NPN transistor Q1 are the same-direction ends, and the base and the Y point of the NPN transistor Q2 are the reverse ends, so the negative feedback coefficient of the circuit is far larger than the positive feedback coefficient, and deep negative feedback is formed. That is, when collector currents of the NPN transistors Q1 and Q2 are slightly different, bases of the NPN transistors Q1 and Q2 can be sensed, and thus they adjust their respective quiescent operating points by the action of such deep negative feedback to adjust their respective quiescent operating pointsThe difference in collector currents is reduced, thereby ensuring accurate equality of collector currents, which is also highly advantageous for reducing the temperature coefficient.
In a word, the circuit structure of the reference source is simple and novel, the self bias is used for providing power supply without external bias, the occupied area of the circuit is small, and the circuit has a good temperature coefficient.
Drawings
FIG. 1 is a core circuit schematic of a typical bandgap reference source;
FIG. 2 is a schematic block diagram of a bandgap reference source of the present invention;
FIG. 3 is a schematic diagram of a core circuit of the bandgap reference source of the present invention;
FIG. 4 is a circuit diagram corresponding to one embodiment of FIG. 2;
FIG. 5 shows the PSRR simulation results of the present invention;
FIG. 6 shows the simulation result of the variation of output with input voltage (voltage regulation rate) in the circuit of the present invention.
Detailed Description
The invention relates to a band-gap reference source with a starting circuit and a self-bias circuit, which has the advantages of high power supply rejection (PSRR), large input range, small voltage regulation rate, small consumed current under the same power supply voltage and the like. As shown in fig. 2, the bandgap reference source includes a bandgap core circuit 3 for generating a reference, and a self-bias circuit 1, an adjusting circuit 2 and a start-up circuit 4 for providing an external power supply to the bandgap core circuit 3. When the power supply voltage V IN When the power is on, the starting circuit 4 works to drive the self-bias circuit 1 to be conducted; the self-bias circuit 1 is turned on to turn off the starting circuit 4 and provide the relative power voltage V for the adjusting circuit 2 through self bias IN An unrelated bias voltage; the adjusting circuit 2 provides an external power supply irrelevant to the power supply voltage for the band gap core circuit 3; the band gap core circuit 3 outputs a reference voltage V REF And use of V REF As its own "local supply" to make it compatible with the supply voltage V IN Is irrelevant.
As shown in fig. 3, the band gap core circuit 3 includes NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP transistors Q3, Q4 and Q5, and further includes a resistor R1,R2, R3, R4 and a capacitor C1. The bases of NPN transistors Q1 and Q2 are respectively connected with two ends of a resistor R3, the emitters of the NPN transistors are connected together and are commonly connected with a resistor R4, and the other end of the resistor R4 is grounded. The collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the NPN transistor Q2 and the PNP transistor are connected togetherThe collectors of Q4 are tied together. The base potentials of the PNP transistor Q3 and the PNP transistor Q4 are the same, and the emitter potentials are connected to V REF The above. The emitter of the PNP transistor Q5 is connected with V REF The upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode is connected with the base electrode of the NPN transistor Q8, and the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and commonly connected with the base electrode of the NPN transistor Q7. The emitter and base of NPN transistor Q7 are respectively connected with ground and V REF The above. The collector and base of NPN transistor Q8 are connected together and to resistor R3. One end of the resistor R2 is connected with the resistor R3, and the other end is connected with the resistor V REF The above. V REF As output terminal connected to peripheral circuit.
NPN transistors Q1, Q2 and resistor R3 form I PTAT A generation circuit 6 for generating I PTAT The current then has a negative temperature coefficient V with an NPN transistor Q8 BE Compensation is performed to reduce the temperature coefficient. The PNP transistors Q3, Q4 ensure that the currents flowing through the two circuits are exactly equal through current mirroring. NPN transistors Q8, Q1 and resistor R4 constitute a constant current source circuit 7, form a micro current source, and supply bias currents to PNP transistors Q3, Q4. The PNP transistor Q5, the NPN transistor Q6, and the NPN transistor Q7 form an operational amplifier circuit 5 to form a two-stage operational amplifier, where the PNP transistor Q5 and the NPN transistor Q6 are first stages, and the NPN transistor Q7 is a second stage. The resistor R1 and the capacitor C1 form a compensation circuit 8, and frequency compensation is carried out on the two-stage operational amplifier to ensure the stability of the two-stage operational amplifier. The whole circuit of fig. 3 is composed of a "local supply" V REF The power is supplied, and the core band gap circuit and the power voltage V are ensured IN Is not relevant.
Specific operating principle of the band gap core circuit 3As follows. In FIG. 3, a positive temperature coefficient I is generated PTAT The circuit of the current is realized through NPN transistors Q1, Q2 and R3, and specifically comprises the following steps:
let I S，Q1 ＝NI S，Q2 Then, I PTAT ＝ ΔV BE / R3 ＝ V T lnN / R3 The current is positive temperature coefficient and passes through the negative temperature coefficient V of the NPN transistor Q8 BE The first order compensation is performed with:
at room temperature (T = 300K), V BE / T = 1.5mV/° K, and V T / T = 0.087mV/° K, the zero temperature coefficient at this temperature can theoretically be achieved by adjusting the ratio of R2 to R3. In practice, the amount of the liquid to be used,it is difficult to achieve very low temperature coefficients, and in the present invention, H-spice simulation under a 0.6 μm Bi-CMOS process library has resulted in temperature coefficients reaching below 40 ppm/deg.C in the range of-20 to-125 deg.C, which is a very low value in Bi-CMOS processes. In a typical bandgap structure such as that shown in fig. 1, the collector currents of NPN transistors Q1 and Q2 are equal to each other, so that the temperature coefficient is theoretically small, but the collector currents of the NPN transistors Q1 and Q2 are difficult to match perfectly due to the fact that the input impedance of the operational amplifier is not infinite, and the like, so that the temperature coefficient is not ideal. However, in the structure of the present invention, it is well ensured that the collector currents of both NPN transistors Q1, Q2 are exactly equal. First, from a large signal perspective, V X ＝V REF -V BE，Q3 And V is Y ＝V REF -V BE，Q5 This ensures V X ＝V Y Thereby ensuring that the collector currents flowing through the NPN transistors Q1 and Q2 are exactly equal; second, from the small signalAngle analysis shows that when collector currents of the NPN transistors Q1 and Q2 slightly change, static working points of the NPN transistors Q1 and Q2 are adjusted through a deep negative feedback effect of two-stage operational amplifier, and therefore the collector currents of the NPN transistors Q1 and Q2 are guaranteed to be accurate and equal.
In addition, bias currents I of NPN transistors Q1 and Q2 and PNP transistors Q3 and Q4 0 The constant current source circuit 7 is used for providing the following specific implementation: in the constant current source circuit 7, from V BE，Q8 ＝V BE，Q1 +I 0 R 4 Andobtaining:
wherein, M is the ratio of the emitter areas of NPN transistors Q1 and Q8. The bias is provided in such a way, so that the advantage of no need of external separate bias is achieved, the performance is stable, and the layout area is saved.
The following examples are given by way of illustration only and are not intended to limit the invention in any way.
As shown in fig. 4, the self-bias circuit 1 includes resistors R5, R6, R7, and R8, NPN transistors Q9 and Q10, and PMOS transistors M1 and M2. One end of the resistor R5 is connected with the input end, and the other end is connected with the source electrode of the PMOS tube M1; one end of the resistor R6 is connected with the input end, and the other end is connected with the source electrode of the PMOS tube M2; resistor R8 has one end connected to the emitter of NPN transistor Q10 and the other end grounded. The grid electrodes of the PMOS tubes M1 and M2 have the same potential and are connected to the drain electrode of the PMOS tube M2; the drain of the PMOS transistor M1 is connected to the resistor R7. The base and collector of the NPN transistor Q9 are connected together and commonly connected to the base of the NPN transistor Q10 and the other end of the resistor R7, and the emitter of the NPN transistor Q9 is grounded. The collector of NPN transistor Q10 is connected to the drain of PMOS transistor M2, and the emitter is connected to resistor R8.
The configuration of the bandgap core circuit 3 is the same as that shown in fig. 3.
The regulator circuit 2 is composed of a PMOS transistor M3. The source electrode of the PMOS tube M3 is connected with power voltage, the grid electrode of the PMOS tube M2 in the self-bias circuit 1 is connected with the grid electrode of the PMOS tube, and the drain electrode of the PMOS tube M3 is connected with the emitting electrode of the PNP transistor Q3 in the band gap core circuit 3.
The starting circuit 4 comprises resistors R9 and R10 and NMOS tubes M4 and M5. One end of the resistor R9 is connected with the power supply voltage V IN The other end is connected with the drain electrode of the NMOS tube M4; one end of the resistor R10 is connected with the drain electrode of the NMOS tube M4, and the other end is connected with the grid electrode of the NMOS tube M5. The grid electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M1 in the self-bias circuit 1, and the source electrode is grounded; the drain of the NMOS transistor M5 is connected to the collector of the NPN transistor Q10 in the self-bias circuit 1, and the source is grounded.
The magnitude of the current flowing through the PMOS transistor M2 in the self-bias circuit 1 is determined by a micro-current source composed of NPN transistors Q9, Q10 and a resistor R8, specifically:
I PTAT ＝ ΔV BE / R8 ＝ V T lnN / R8
this current is coupled to the supply voltage V by self-biasing of the self-biasing circuit 1 IN Is irrelevant. The resistors R5 and R6 form source followers of the PMOS tubes M1 and M2, and independence of the self-bias circuit and power supply voltage is further guaranteed. However, a very important problem in a bias circuit 1 that is independent of the power supply is the existence of a "degenerate" bias point. For example, in the embodiment of fig. 4, if all transistors pass zero current when the power supply is powered up, they can be kept off indefinitely because the self-biasing circuit 1 allows zero current to pass on both sides. Based on the above, the circuit of the invention therefore introduces a startup circuit 4 to solve the existence of a "degenerate" bias point. The introduction of the start-up circuit 4 inevitably increases the power consumption, which is expected in the circuit of the present invention, and therefore, the power consumption can be reduced by the resistor R7. The principle is as follows: when the start-up circuit starts to operate, the current flowing through the resistor R7 in the self-bias circuit 1 is zero, so the voltage V of the start-up circuit is zero BE Will be added on the NPN transistor Q9 to turn on the NPN transistor Q9, and the NPN transistor Q9 will be self-biased after being turned onGenerating and powering on the circuit 1The source independent current, then, will generate a voltage drop on the resistor R7, so that the potential at point P is larger than V BE And thus the start-up circuit is turned off, which greatly reduces power consumption, and in addition, the bandgap core circuit 3, due to its simple structure, causes the current consumed by the circuit to be small at the same input voltage, thereby also reducing power consumption.
The current generated in the self-biasing circuit 1 is almost independent of the supply voltage, which results in a large input range of the input voltage. When the current flows through the PMOS transistor M2, the gate voltage of the PMOS transistor M2 is determined according to the saturation leakage current equation of the PMOS transistor M2, and the gate voltage is the bias voltage of the PMOS transistor M3 in the adjusting circuit 3. PMOS transistor M3 can also be referred to as a voltage regulator transistor because when the supply voltage V is applied IN When it becomes larger, due to I PTAT The current is basically unchanged, so that the gate voltage of the PMOS transistor M2 correspondingly increases according to the saturation current equation, that is, the gate potential of the PMOS transistor M3 increases with the increase of the source potential, and the voltage between the gate and the source of the PMOS transistor M3 does not change much, so that the current flowing through the PMOS transistor M3 also basically does not change much but only slightly decreases, and thus the slight decrease of the leakage current of the PMOS transistor M3 causes the output of the bandgap to slightly decrease, which is about- Δ V REF . When Vin is increased, the bandgap output voltage is also slightly increased to about + Δ V REF And + Δ V REF ≈-ΔV REF . It can be seen that the adjusting circuit 2 is actually a negative feedback circuit of the bandgap core circuit 3 to ensure that the bandgap output voltage V in the bandgap core circuit 3 is REF Independent of the power supply voltage, thereby also improving the power supply rejection ratio of the whole circuit.
In addition, the circuit structure of the invention introduces the idea of local power supply to further improve the power supply rejection ratio. That is, in the bandgap core circuit 3, if we can introduce a voltage V equal to the power supply voltage IN The PSRR of the bandgap core circuit 3 is increased by the power supply with small correlation. In fact, the circuit configuration of the present invention makes use of the idea that the "local supply" referred to above is the bandgapOutput V REF . By regulation of PMOS transistor M3 in regulation circuit 2, V REF And V IN The dependence of (c) has decreased much, and in the bandgap core circuit 3, all the devices are powered by the "local supply" V REF The PSRR is also greatly improved because of the direct power supply. The H-spice simulation result under the Bi-CMOS process library based on 0.6 mu m is shown in figure 5. As can be seen from fig. 5, the power supply rejection ratio PSRR of the bandgap output is very high in the three models TT, SS, and FF.
The circuit of the invention has small voltage regulation rate of band gap output under the condition of direct current. The specific analysis is as follows: when the input voltage has a large fluctuation range, the PMOS tube in the adjusting circuit 2 is usedM3 Effect of the tuning tube, V REF The amplitude of variation is small, and V REF And further influenced by the deep negative feedback of the operational amplifier in the band-gap core circuit 3, resulting in V REF Substantially independent of input voltage V IN The effect of the change. The above analysis was well verified by performing an H-spice simulation on a Bi-CMOS process of 0.6 μm (simulation results are shown in FIG. 5).
Claims (4)
1. A high power supply rejection bandgap reference source, characterized by: the band-gap power supply comprises a self-biasing circuit (1), an adjusting circuit (2), a band-gap core circuit (3) and a starting circuit (4); wherein the content of the first and second substances,
the band gap core circuit (3) comprises NPN transistors Q1, Q2, Q6, Q7 and Q8, PNP transistors Q3, Q4 and Q5, resistors R1, R2, R3 and R4 and a capacitor C1; bases of NPN transistors Q1 and Q2 are respectively connected with two ends of a resistor R3, emitters are connected together and are connected to a resistor R4 together, and the other end of the resistor R4 is grounded; the collectors of the NPN transistor Q1 and the PNP transistor Q3 are connected together, and the collectors of the NPN transistor Q2 and the PNP transistor Q4 are connected together; the base potentials of the NPN transistor Q2 and the PNP transistor Q4 are the same, and the emitter potentials are connected with the reference output voltage V REF The above step (1); the emitter of the PNP transistor Q5 is connected to the baseQuasi-output voltage V REF The upper and base electrodes are connected with the collectors of the NPN transistor Q2 and the PNP transistor Q4, the emitter electrode of the NPN transistor Q6 is grounded, the base electrode of the NPN transistor Q6 is connected with the base electrode of the NPN transistor Q8, the collectors of the PNP transistor Q5 and the NPN transistor Q6 are connected together and are commonly connected with the base electrode of the NPN transistor Q7; the emitter and base of NPN transistor Q7 are respectively grounded and reference output voltage V REF (ii) a The collector and the base of the NPN transistor Q8 are connected together and connected to the resistor R3; one end of the resistor R2 is connected with the resistor R3, and the other end is connected with the reference output voltage V REF The above step (1); one end of the resistor R1 is connected with the base electrode of the NPN transistor Q7, and the other end of the resistor R1 is connected with the capacitor C1; the other end of the capacitor C1 is connected with the base electrode of the PNP transistor Q5; reference output voltage V REF The output end is connected with a peripheral circuit;
the starting circuit (4) is operated at a supply voltage V IN When the power is on, the power works, current is generated and is transmitted to the self-bias circuit (1) to drive the self-bias circuit (1) to be conducted; the self-bias circuit (1) starts to be conducted after receiving the current provided by the starting circuit (4), and generates a voltage V corresponding to a power supply voltage through the self-bias action IN An irrelevant bias voltage is transmitted to the adjusting circuit (2), and the starting circuit (4) is closed; after receiving the bias voltage output by the self-bias circuit (1), the adjusting circuit (2) generates constant current through self adjustment and outputs the constant current to the band gap core circuit (3); the band-gap core circuit (3) generates a band-gap reference voltage V through the operation of the band-gap core circuit after receiving the constant current provided by the adjusting circuit (2) REF And takes it as the output of the whole band-gap reference source.
2. The bandgap reference source as recited in claim 1, wherein: the self-bias circuit (1) comprises resistors R5, R6, R7 and R8, NPN transistors Q9 and Q10 and PMOS transistors M1 and M2; one end of the resistors R5 and R6 is connected with the power supply voltage V IN The other end of the resistor R5 is connected with the source electrode of the PMOS tube M1, and the other end of the resistor R6 is connected with the source electrode of the PMOS tube M2; resistor R8 is terminated atThe emitter of the NPN transistor Q10, the other end is grounded; the grid electrodes of the PMOS tubes M1 and M2 are connected with the drain electrode of the PMOS tube M2, and the drain electrode of the PMOS tube M1 is connected with the resistor R7; the base electrode and the collector electrode of the NPN transistor Q9 are connected together and are connected to the base electrode of the NPN transistor Q10 and the other end of the resistor R7 together, and the emitter electrode of the NPN transistor Q9 is grounded; the collector of NPN transistor Q10 is connected to the drain of PMOS transistor M2, and the emitter is connected to resistor R8.
3. The bandgap reference source as claimed in claim 1 or 2, wherein: the adjusting circuit (2) is composed of a PMOS tube M3, and the source electrode of the PMOS tube M3 is connected with the power supply voltage V IN The grid electrode of the PMOS transistor M2 in the self-bias circuit (1) is connected, and the drain electrode of the PMOS transistor Q3 in the band gap core circuit (3) is connected.
4. The bandgap reference source as recited in claim 3, wherein: the starting circuit (4) comprises resistors R9 and R10 and NMOS tubes M4 and M5; one end of the resistor R9 is connected with the power supply voltage V IN The other end is connected with the drain electrode of the NMOS tube M4; one end of the resistor R10 is connected with the drain electrode of the NMOS tube M4, and the other end is connected with the grid electrode of the NMOS tube M5; the grid electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M1, and the source electrode is grounded; the drain of the NMOS transistor M5 is connected to the collector of the NPN transistor Q10, and the source is grounded.
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| CN102053645A (en) * | 2011-01-31 | 2011-05-11 | 成都瑞芯电子有限公司 | Wide-input voltage high-power supply rejection ratio reference voltage source |
| CN102262414A (en) * | 2010-05-29 | 2011-11-30 | 比亚迪股份有限公司 | Band-gap reference source generating circuit |
| CN102375469A (en) * | 2010-08-10 | 2012-03-14 | 中国人民解放军国防科学技术大学 | PSR (power supply rejection) reinforcement circuit for low power supply voltage bandgap reference |
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| CN116954296A (en) * | 2023-08-14 | 2023-10-27 | 无锡盛景微电子股份有限公司 | Low-power-consumption self-bias second-order compensation band-gap reference circuit |
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| CN102279616B (en) * | 2011-03-29 | 2012-07-18 | 山东华芯半导体有限公司 | High-precision current reference source with pure MOS structure and method of manufacturing high-precision current reference source |
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2007
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| CN101581948B (en) * | 2008-05-15 | 2012-06-06 | 欧姆龙株式会社 | Reference voltage generating circuit |
| CN102033566B (en) * | 2009-09-24 | 2013-10-23 | 上海华虹Nec电子有限公司 | Bipolar NPN type band-gap reference voltage circuit |
| CN101794159B (en) * | 2010-03-08 | 2012-05-23 | 东南大学 | Band-gap reference voltage source of high power supply voltage rejection ratio |
| CN101794159A (en) * | 2010-03-08 | 2010-08-04 | 东南大学 | Band-gap reference voltage source of high power supply voltage rejection ratio |
| CN102262414A (en) * | 2010-05-29 | 2011-11-30 | 比亚迪股份有限公司 | Band-gap reference source generating circuit |
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| CN104467850A (en) * | 2013-09-17 | 2015-03-25 | 上海信朴臻微电子有限公司 | Bias circuit for high performance low-power analog-to-digital converter |
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| CN106339025A (en) * | 2016-05-23 | 2017-01-18 | 西安电子科技大学 | Low-voltage and high-precision band-gap reference circuit applied to node of Internet of Things |
| CN105912066A (en) * | 2016-06-02 | 2016-08-31 | 西安电子科技大学昆山创新研究院 | Low-power-consumption high-PSRR band-gap reference circuit |
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| CN108563280A (en) * | 2018-05-25 | 2018-09-21 | 成都信息工程大学 | A kind of band gap reference promoting power supply rejection ratio |
| CN111142607A (en) * | 2020-03-16 | 2020-05-12 | 成都纳能微电子有限公司 | Voltage conversion current circuit with high power supply rejection ratio |
| CN111796624A (en) * | 2020-07-27 | 2020-10-20 | 东南大学 | CMOS voltage reference circuit with ultrahigh power supply ripple rejection ratio |
| CN112686559A (en) * | 2021-01-06 | 2021-04-20 | 郑州铁路职业技术学院 | Achievement transformation online supply and demand matching method based on big data and artificial intelligence |
| CN112667023A (en) * | 2021-03-15 | 2021-04-16 | 四川蕊源集成电路科技有限公司 | Voltage generator with wide input range and voltage control method |
| CN113220060A (en) * | 2021-04-30 | 2021-08-06 | 深圳市国微电子有限公司 | Band-gap reference circuit with high power supply rejection ratio and electronic equipment |
| CN113721697A (en) * | 2021-09-03 | 2021-11-30 | 龙骧鑫睿(厦门)科技有限公司 | Low-temperature floating band gap reference voltage source |
| CN113721697B (en) * | 2021-09-03 | 2022-09-16 | 龙骧鑫睿(厦门)科技有限公司 | Low-temperature floating band gap reference voltage source suitable for integrated circuit |
| CN113885634A (en) * | 2021-11-02 | 2022-01-04 | 苏州华矽共创信息技术合伙企业(有限合伙) | Band-gap reference voltage source suitable for low-current gain type NPN triode |
| CN114035641A (en) * | 2021-11-03 | 2022-02-11 | 西安电子科技大学重庆集成电路创新研究院 | Band gap reference circuit with high performance |
| CN115390613A (en) * | 2022-10-28 | 2022-11-25 | 成都市安比科技有限公司 | Band gap reference voltage source |
| CN115390613B (en) * | 2022-10-28 | 2023-01-03 | 成都市安比科技有限公司 | Band-gap reference voltage source |
| CN116954296A (en) * | 2023-08-14 | 2023-10-27 | 无锡盛景微电子股份有限公司 | Low-power-consumption self-bias second-order compensation band-gap reference circuit |
| CN116954296B (en) * | 2023-08-14 | 2024-07-12 | 盛泽芯集成电路(无锡)有限公司 | Low-power-consumption self-bias second-order compensation band-gap reference circuit |
| CN117254775A (en) * | 2023-09-27 | 2023-12-19 | 江苏帝奥微电子股份有限公司 | Self-bias oscillating circuit |
| CN117254775B (en) * | 2023-09-27 | 2024-03-08 | 江苏帝奥微电子股份有限公司 | Self-bias oscillating circuit |
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