CA1133143A - Self-correcting, solid-state mass memory organized by bits and with reconfiguration capability for a stored program control system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
1. A self-correcting, solid-state mass-memory, organized by bits and with reconfiguration capability for a stored program control system, comprising a processing system interfaced with the mass memory through a controller, said memory consisting of one or a plurality of memory modules and a control module at least, comprising a time base which generates timing and con-trol signals for memory operation, with shape and period var-iable according to the operation, an addressing control circuit which generates the addresses for memory reading and writing, in-put-output means which send the data towards the memory or the controller and a self-correcting logic which controls the right operation of the memory, corrects and signals to the controller the possible memory errors, said memory being characterized in that each memory module is intended to store a bit of a plu-rality of words consisting of information and redundancy bits to be used for self-correction operations and comprises:

- a plurality of memory integrated circuits obtained by charge-coupled technology and consisiting of blocks of shift re-gisters organized in serial-parallel-serial configuration, each block being able to he addressed randomly and at the same time as the blocks of equal position in all the corres-ponding circuits of all the memory modules and containing a plurality of cells to be addressed in sequence;

- data input-output means;
- means for receiving from the control module or each control module and sending to the integrated circuits of the memory module the timing, addressing and control signals.

Description

~ 33~

The present invention relates to stored-program control systems for telecommunications equipments and more particularly it concerns a self-correcting mass-memory with reconfiguration capa-bility, making use of the charga-coupled device (CCD) technology.

5 It is known that present stored-program control systems have memories organized in a hierarchic structure, providing fast-access memor:i~s for on-line programs and data (main memories), followed by other memories, generally with slower access, for program~ and data of less immediate and frequent use (mass mem-~
ories). These memories often act also as auxiliary memories ~orthe main memories, that is they contain also semi-permanent data and on-line programs necessary to allow the control system to be put again into normal service when a failure occurs in the mai~ memories.
,~
Until recently mass-memories consisted usually of magnetic disk tape or drum uni~s, because, in ~he then sta-te of the ar~, these solutions alone could ensure large storage capacity at low cost.

Magn~tic memories present some inconveniencies, in that they can not attain sufficiently high operating speed, and in particular fast access time; and in that they can not en~ure a sufficiently high system availability, owing to the frequen~
interventions necessary to maintain the efficiency of the units; this problem is aggravated by the fact that the magnetic units have moving mechanical parts that require initial running-in and present wear characteristics that can also require pre-ventive maintenance.

For these reasons studies aimed at providing alternative types of memories, mainly of small and medium capacity (for instance up to 10 million words) have proved to be of great importance;
because of developments in the techniques used to manufacture solid-s~ate components, most of these studies have been direc-ted towards components of very large scale integration~ and more particula~ly towards charge coupled devices.

A memory of this type with an operating capacity very similar to those-o-E a disk-unit is already commercially available.

Such a solid-state memory intrinslcally presents high op-erating speed as well as good reliability and easy-maintenance characteristics; moreover it presents good modularity, that is ; 15 to say, quite small units may be used initially and then increased according to the requirements.

This memory also presents some problems which make it not well suited for use in telecommunications system control: more particularly it provides no error self-correcting capability ~0 and is organized in "bytes", that is by 8-bit words.
. .
In telecommunications applications the control system must be in service continuously: thus it is important for the mass~
memory ~o be provided with a self-correcting capability avoiding syst~m down~ime during detection of the cause of an error and the correction thereof; self-correction provides efficient protection of the stored data, so that said data is not lost and can be used by any auxiliary unit put into service by means of a reconfiguration system.

In fact, processing systems with severe reliability require-ments need usually a plurality of mass-memory units. On the .. . ......

contrary, if redundant parts for automatically replacing failed components, when a failure occurs, are provided within one such memory unit, the reliability requirements of the processing system could be metby a single mass-memory unit, allowing a remarkable saving.

Moreover, for both speed and flexibility purposes,in ~he tele-communications field~ or more generally in process control, the control system must be able to operate on words of 16 bits or more.

To achieve flexibility as to the real length of the words, the number of redundancy bits necessary for self-correction and the provision of redundant parts, it is important that a memory organized by bits is provided: the memory consists of many modules, each one storing one bit of a plurality of words.

Th~ aim of the present invention is to provide a solid-state mass-memory organized by bits, which can use solid-state compo-nents of the CCD type, which can ble utilized in a control sys-tem applied to telecommunications with high relia~ility require-ments and which comprises both error self~correction means and internal redundancies allowiny its reconfiguration.

Accordingly the invention provides a self-correcting and recon-figurable solid-state mass-memory organized in bits, having at least one memory unit comprlsing a first group of memory mo-dules each adapted to store one bit of each of a plurality of words consisting of information bits and redundancy bits enab~
ling self-correction, one or more spare memory modules which in case of failure replace one or more modules in th~ first group, and control means controlling the exchange of data between the memory unit and a control, said control means generating timing and addressing signals for the memory unit, supervising the operation of the memory unit by detecting and correcting errors and comprising switching means for switching out a memory module in the first group upon failure and swit ching in a spare memory module in its place; wherein said control means comprise triplicate control modules and each memory module comprises three data transceivers, each con-nected, on one hand, to one of the three control modules through an associated data transmission line and, on the other hand, to all memory circuits in the memory modules and to one input of a first majority logic circuit, which receives from each transceiver the bit to be written in the memsry7 as supplied by the associated control module and supplies to the memory circuit concerned a bit present on at least two out of three inputs of said first majority logic circuit; and a second majority logic circuit which has inputs in groups of three respectively connected to con-nections that, in three unidirectional buses transferring timing and addressing signals from associated control module to the memory module, convey homologous signals, the second ma~ority logic circuit providing an output for each group of three inputs which receives the signal present on at least two inputs in the group, the outputs of the second ma-jority logic circuit being connected to means that allow the reception by the module of the timing and addressing signals.

These and other characteristics of the invention will be bet-ter disclosed by the following description, given by way of example and in not limiting sense, of a preferred embodiment thereof, taken in conjunction With the annexed drawings in which:

- Fig. l represents a block diagram of a solid-state mass-memoxy unit and its interconnections with a "multiprocessor"
processing system;

Fig. 2 is a block diagram of a memory module of the memory unit of Fig. l;

- Fig. 3 is a block diagram of the control module of the memory unit of Fig. l;

- Fig. 4 is a detailed schematic diagram of the time base of ~ 33~
~4a-the control module of Fig. 3;

- Fig. 5, on the same sheet as Fig. 1, is a detailed schema-tic diagram of the device checking the addresses in the control module of Fig. 3;

- Fig. 6 is a detailed schematic diagram of the input/output unit of said control module, according to a first embodiment;

- Fig. 7 is a detailed scheme of the correction logic;

- Figs. 8a, 8b~ 8G and 8d show the relationship of certain of the signals controlling the operations in the memory, un-der different operating conditions;

- Fig. 9 is a schematic diagram of a memory unit also inclu-ding a spare memory module;

- Fig. 10 is the scheme of the input/output unit of the con-trol module of the unit shown in Fig. 9;

- Fig. 11 is the block diagram of the switching point of the input/out- ..................................................

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~1 3.?.~3 put unit of Fig. 10;
- Fig. 12 shows schernatically a full redundant embodiment of a me-mory unit.
Fig. 1 shows a telecommunications equipment TC, for in-5 stance a telephone f~xchange with stored-program control system CPR, that by way of example and for sake of generality is supposed to be of the "multiprocessor" type.
System CPR comprises: a plurality of processing units El .
. . . Em, one or a plurality of main memory units MPl . . . MPn for 10 on-line data and programs, and one or a plurality of mass-memory units MMl ... MMi The presence of several units MM can depend on both me-mory capacity and reliability purposes, if each unit has not internal-ly a ~edundant structure.
lS Processing units E are connected to memory units MM, MP
through a connection network RC and the so-called "controllers" Cl.
.. . Cn, C'l . . . C'i, that is the devices controlling data transfer be-tween processing and memory units. Devices C, G', known in the technique, are not an integrating part of the present invention, then 20 they will not be described in detail.
Every unit MMl . . . MMi of the mass-memory is composed of a plurality of ~nemory modules MEl . .. MEp as well as o~ a con-trol module MC. ~ -Memory Inodules ME are obtained by integrated circuits us-25 ing a charge-coupled technology; according to the present invention each module stores a bit of all the words storable in the module.
These words are composed of information bits (stored in tnodules MEl . . . MEh) and r dundancy bits (stored in nlodules MEi.
.. . MEp), that can be used for error-detection and correction.
The number o modules ME of a unit MM is then equal to the number of bits of a word.
As the invention is to be applied to telecommunications sys-- tems, for reasons of operating speed, the words ought to contain at .
,, ,, 1~-3~:?~L~3 least 16 inforrnation bits; in addition, it has corne out that, using the Hamming s~ode for the error correction, the minimum nulnber of redundancy bits ensuring the single error correction on 16 bits is 5 bits.
Owing to the bit organi~ation according to which each mod-ule stores a bit of a plurality of words, the Hamming code allows the detection and correction of all the possible errors occurring in a me-mory module, as described hereinater.
The er~bodirnent of figures l to 8 refers to words contain-10 ing, besides the information bits, only the minimum number of re-dundancy bits, assuring the correction of single errors, in particular it relates to 16 bit information and 5-bit redundancy words.
Then, the memory unit is composecl of 21 modules. Never-theless, a characteristic of the invention is its hori~ontal flexilibity;
15 hereinafter, we examine also embodiments with a higher number o redunslancy bits allowing the detection of multiple errors or, above all, the internal reconfiguration of the memory unit, by using one or more modules devotecl to redundancy bits: "reconfiguration" means the possibility of substit~lting a failed me}nory module with a spare 20 2nodule.
The memory modules are interconnected to each other and to the control module through a bus 1 convey;ng to all the modules both addresses and control signals; furthermore, each module is connected bidire~tionally to the control module through a wire 10(1).
2S .,. 10(p), carrying each information bits.
The structure of modules ME will be described in greater details in Fig. 2.
Control module MC, which is connected to controller C' through a bus 2, has the task of controlling the exchange of data be-30 tween the controller and the melnory, of generating the timing sig-nals necessary to the operation of the n~emory unit, of providing tlle correct addressing during the operations, and of supervising the op-eration of the memoly itself by d.te tiny dnd colrecting e~-or~.

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:~ ~ 3 ~ 3 The data transfer between control module MC and control-ler C' is parallel/asynchronous, i. e. all the bits of a word are transferred parallelly to the control module, at the requested in-stant The independent control of addressing and timing allows the simplification of the structure and prograInming of the controller;
besides, by a suitable choice of the controller, the mass-memory may be seen by the computing system as any main-me~nory bank.
The structure of MC will become clearer from Fig. 3.
With reference to Fig. 2, a generic memory module ME;
comprises a plurality of i~tegrated charge-coupled circuits AC,iden-tical to one another and designed to store a bit of the words to be stored into unit MM. The choice of the integrated circuit and the number of circuits AC of a module will depend onthe required ca-lS pacity of each module; obviously such a number will depend on con-struction standards.
By way of example, a Inodule with 32 integrated circuits l~Cl ... AC32 is shown.
Advantageously each integrated circuit AC; consists of a 20 plurality of individually addressed blocks of shift registers organiz-ed in the serial-parallel-serial coniguratisn, that is each blockcon-tains as input register loaded in s ries and unloaded in parallel, a plurality of intermediate registers loaded and unloaded in parallel, and an output register loaded in parallel, and unloaded in seriesO By 25 this arrangement the registers of a block actually behave as a sin-gle register, and all the blocks form together a random access me-mory.
In these circuits, beginning fro}n a position indicated by the controller, read, write or "read-modify-write" operations may 30 be effectuated. The last operation occurs when correcting devices have detected an error to be corrected. In the absence of requests - for operation, the information will be "refreshed" by recirculating the bits of the information itself.

Inside each block, fast timing signals will control the shift~
ing in series within a register (~nore particularly the loacling of the input register and unloading of the output register); slow timing sig-nals will control the transfer in parallel between adjacent registers 5 (more particularly, the unloading of the input register and loading of the output rcgister).
According to the present invention these signals, herein-after referred to as "shift signals" and "transer signals", respec-tively, have different period and/or shape depending on the type of 10 operation effectuated and on the working phase within each operation, as it will be better described hereinater. In all the operation phases the ratio between the periods of the two types of signals will obvious-ly remain constant.
A circuit of this type is sold under the name of CCI) 464 by 15 the Fairchild Camera and Instrument Corporation of Mountain View (California, USA); this circuit comprises 16 blocks of 128 registers with 32 positions, in which the shifting is controlled by a pair of sig-nals (~ 2) the first of which determines the time allotted to each bit and the second one controls the actual loading or unloading in ;~o series. A second pair of signals, having a period 32 times longer, controls the transfer in parallel.
For clarity reasons, the following description will be made in the asslL~nption that circuits AC are really circuits CCD 464. Yet, by r~eans of obvious modifications, the invention can be applied t~
2S any type of charge-coupled memory circuit organi~ed by blocks of registers available in serial-parallel-serial configuration.
Al, A2 denote conventional buffers receiving from the con-trol module, through wires 12, the address bits relative to one o the 16 register blocks in all circuits AC and, through wîres 13,the 30 shift and transfer signals; Al, A2 amplify these signals so that they can drive all circuits AC.
13uffers Al, A2 are connected to circuits AC through con-nections lZ' and 13',corresponding to inputs 12, l3. ~ buffer, for ~ 3 ~ f~.3 example ~2, receives from the control module, through a wire 15, also a "write enable" signal WE, conveyed to circuits AG through wire 15 ' DEl denotes a conventional decoder, receiving from the 5 control rxlodule, through a connection 11, the most signiicant ad-dress bits (i, e. the bits detecting one of the 32 circuits A(;); the output oi DEl is a signal CS enabling the real addressing of one of circuits ACl .. . AC32.
Signal CS is sent to the relevant circuit through one of 10 wires 1101 .. 1132.
The decoded receives also frorn the control module, through a wire 14, an enable signal for the whole module.
RTl denotes a receiving/transmitting unit acting as data input/output unit, connected to the control module through wire 10 lS and to memor~ circuits AC through wires lOa, lOb, conveying the bit to be written and the read bit, respectively.
The operation of the transmitter of RTl is enabled by a sig-nal coming from the control module tsignal C;K2), as described her einafter .
With reference to Fig. 3, control module MG comprises a time ba~e BT, an address control device IN, a data input and out-put unit IU and a self-correcting logic LC.
The n~icroprogrammed time base BT, is designed to gen-erate timing signals for memory unit MM (Fig. 1), enclosing the ZS shift and transfer signals, and to generate ~ogether with IN read and write addresses in circuits AC (Fig. 2) of each module ME
(Fig. 1). The microprogrammed structure operates so that cer-tain operations occur at a variable speed depending on the operat-ing phases, and this is a undamental characteristic of the inven-30 tion.
Input/output unit IU has the task of controlling the opera-tions connected with theasynl-hronous data exchange between the controller and the memory and viceversa.

Self-correcting logic LC is designed to generate redundancy bits, on the basis of the information bits received through IU; in case of memory reading, LC is also entitled to corrlpare the generated bits Witl'l the read bits; in case of discrepancy, to correct the infor-5 mation bits and to signal the discrepancy to the controller.
The structure of blocks IN, BI, IU, LC and the interconnec-tiOIlS between said block:s will result in greater details in the follow-ing Figures. To simplify the drawing, Figure 3 schernatizes with sep-arated connections the links of each block with the controller, the me-10 mory modules or the remaining blocks.
With reference to Fig. 4, OS denotes a conventional oscillat-or, which generates a fundamental clock signal CKO utilized by the time base to obtain other timing signals.
References ROMl, REl, CNl d~note a read only-memory, 15 a parallel-parallel register and a counter that together form a coun-ter CNO module 40~6 acting as an address counter. More particular-ly, the result of the counting of CNO detec$s the position o a word inside a block of registers in circuits ~C (~ig. Z~ of the different modules as an effect of the shift and transfer signals: at the output 31 20 of CNO the least significant bits of the complete address will be pre-s erlt .
Counter CNO is subdivided into two courlters module 64,one -~ of which, with output decoding, consists of ROMl and REl and the other one of CNl.
Memory ROMl, which is addressed by the counting of its internal state, contains 64 words, each comprising six bits of intern-al state (that is six bits indicating the result of the counting module 64), three bits forming a conditioning signal for a second read-only memory ROMZ, and 1 bit forming the carry of the counter.
The words of ROMl are stored and recallecl in parallel by REl upon command of the shift signal (~2) which causes the store and recall of the bits of the ~rlemory: thus REl stores a new word each time that a bit must be shifted by a position inside the illpUt or output ~ ~ 3 1 3L~3 register of a block of ciri uits AC (Fig. 2).
The output of REl relative to the state bits (wires 30 of con-nection 3~ is carried to ROMl as address signal; wires 30, together with wires 31 outgoing frorn CNl transfer to device IN (Fig. 3) the 5 sequential part of the address, to be cornpared with the same address part generated in IN.
The output 32 (Fig. 4) relative to the carry, forms an input of counter CN1 and advances it by a step at each complete reading of ROM 1 .
The result of the counting effectuated by CNl, which origi-nates the most significant bits of the sequential part of the address, is presented to output 31 upon a command s~f the sarne signal ~P% con-trolling the storage of bits into REl. In this way all the bits of the se-quential part of the address are present at ths same time.
A further outp~t 33 of ROMl transfers to ROM2 three decod-ing bits of the internal state of ROMl, used for generating transfer signals .
Memory ROM2 forms, with a second parallel-parallel re-gister RE2, a sequential logic with 8 internal states identifying the 20 elementary time inside a cycle, and is designed to generate shift and transfer signals. Memory RC)M2 contains 512 words, each compris-ing three status bits and four bits relative to each one of said signals, and is jointly addressed by its internal state, the decoding bits o~ the internal state of ROMl, two bits denoting what type of operation is in 25 progress, and the result of the comparison between the sequential part of address generated by CNO and the one generated by IN (Fig.
3).
The signals denoting the type of operation arrive from the controller through wires Z0, register RE5 and wires Z00; the com-- 30 parison signal arrives from IN through wire 4, register RE6 and wire 4 0.
Registers RE5, RE6 can transfer to the output the signals present ~t their inputs in cor~respondence with the trailing edge of ~1 1 (denoted by ~1).
The words of ROM2 are stored (and recalled) by RE2 at a rythIn similar to the one of fundamental clock CKO. The outputs of RE2 relative to the internal state of ROM2 (wires 34) are used as aa-5 dre6sing signals for the ~nemoiy itself and for a further read-only mernory ROM3; the outputs relative to shift signals ~ 2 (wires 139, 131) are sent to memory circuits AC; the transfer signals pre-sent on OUtptlt wires 35, 36 are stored into a register RE4 de3ignecl to determine the exact phase location of the transfer signals with re^
10 spect to the shift signals. The storage onto RE4 is controlled by the trailing edge of the pulses of CKV (signal CKt:)) whilst ~E2 is control-led by the leading edge of the sanle pulses.
Effective transfer signals ~3, ~4 are present on output wires 132, 133 of RE4 (which with wires 13~, 131 form connection 13).
The use of read-only memories allows the required variabili-;~ ty of both period and shape of said signals to be easily obtained as a functior~ of the type of oyeration and operating phase in each operation.
More particularly, at each read and/or write operation, a fast shift of bits in register blocks can be controlled till the required ~- 20 initial word is reached; afte~ this phase a slower shift will occur (for instance with a double period) for the real transfer of words to the memory or computer. In this way a reduced access time is obtained, whilst the read and/or write rnode occur at a slower atthm in orcler to tak~ into account the processor requirernents.
2S As to the shape of the shift and transfer signals, the address of memory ROM2 conditioned by the kind of operation will of course allow at the output a sequence of words such that the bits relative to each one of said signals may remain in either of logic states as long as required. This will be clearly seen by exarnining Fig. 8.
Read-only rnernory ROM3 is a combinatory logic, that in function of the kind of operation (present on wires 200) of the inter-nal state of memory ROMZ (arriving to ROM3 through wires 34), of the cornparison signal coming fror~ J (:~ig. 3) through wires 4, 40 3~J~

and of two signals denoting the data transfer status (signals coming from input/output unit IU, Fig. 3, through ~,vires 59 register R~5 and wires S0), generates the timing signals dilferent from shift and trans-fer signals.
S ROM3 contains 256 words, each one of thern comprising the bit originating enabling to write signal WE, and two bits (CKl, CK2) the first of which enables the data transfer towards the controller and the generation of the sequential part of address by means of IN, and the second one enables the data transmission to memory modules. In 10 the absence of CE~2, data transmission will be enabled by memory modules towards controller. It is worth noting that bit CKl can be emitted only if the signals present on wires S0 denote the end of an operation and whether address identity between IN and CNO occurs for this cycle, It has to be reme~nbered that registers RE5, RE6 load the bits present at their inputs in correspondence with the trailing edge of ~1. In this way, practically at the beginning of a memory cycle, the memory knows whether it has to effectuate an operation or it does not, whether it must set itself in search phase or whether it 20 must really read or write data.
A parallel-parallel register RE3 tin~ed by CKO provides the correct positioning in time of the signals generated by ROM3 b~3fore transferring them to utilization deYices through wires 15, 16, 17.
Also the shape of WE, CKl, CK2 will be seen with reference to Fig.
ZS 8.
In E~ig. 5, CP denotes a presettable counter, with a pair s~f inputs, connected to the controller through connection 22 and wire 21, presenting the address o~ the first word involved in an operation and the loading command for such address, respectively. Beginning 30 from such an address, CP generates sequentially the addresses of all the words involved in the operation, and increases its contents at the end of each read and/or write operation. The advance command is provided by signal CKl whose generation, as stated, depends on ~ 3~

the ending of a preceding operation.
CP can be considered as subdivided into two parts, CPl, CP2 which receive respectively the most significant bits of an ad-dress (that is the bits identifying the integrated circuit interested in an operation, in each module and the block of shift registers in said circuit)and the least significant bits of the same address (that is the bits identifying the word inside a block).
Counter CPl is connectecl to decoder DE~l(Fig. 2) and ar~-plifier ~1 of the mernory modules through wires 11, 12 respectively, on which the part of the address relative to integrated circuit and block of registers is present.
Counter CP2 is connected to an inpu-t of a comparator CM2 ~Fig. 6) through wires 18 on which the sequential part of the address is present.
CM2 has a second input connected to connection 3 through ` which it receives the sequential part of the address generate~l by the tinle ba s e.
Wires 18 and the wires of connection 3 will be connected to the inputs of CM2 so as to optimi~e i;he access time to memory tak-ing into account the speed of the controller, as e~plainecl later.
~-~ In case of equality of the addresses, CM2 generates the comparison signal that through connection 4 is sent to both the time base and the input of a two-input AND gate Pl.
The other input of gate Pl is connected to the output of a - 25 two-input logic OR gate P29 which re ::eives rom the controller, through wires 201, 202 of connection 20, the signals R, W indicating the request for a reading or writing respectively, in the memory.
The output of gate Pl is connected through wire 14 to decoder DEl (Fig. 2~, enabling it to operate.
Ln Fig. 6, reference RT2 denotes a conventional data trans-ceiver, for instance of the type "open collector". To simplify the drawing an only logic gate for cach direction has been shown, but it is evident that RT2 consists of as many pairs of gates as are the ~ a 3.i~l3 wires of connection za,.
In case of data transer from the controller towards the memory, RT2 receives frorn C' (Fig. 1) through wires Z4 (Fig. 6), the 16 information bits and transfers them via bus 8 towards a sec-5 ond transceiver l~T3 and hence on bus 100, consisting of wires 10(1... lO(h).
In case of data transfer towards the controller, RT2 sends on wires 24 the information bits, possibly corrected by logic LC
(Fig. 3) and received through wires 60 and a register RE7 timed by 10 signal CK1; during read-modify-write mode, the same corrected bits may also be transferred to RT3, thus allowing the correction of memory without controller intervention.
The transmission towards the controller is enabled when wire 201 presents the sigxlal indicating that a read phase is in pro-15 gress.
Transceiver ~T3 consists of two units, each as RT2. Incase of writing in memory, RT3 transmits on bus 100 the information bits coming from RT2 and on bus 101 (consisting of wires lO(i) . . .
lO(p)) the redundancy bits coming from correction logic LC (Fig. 3) 20 through wires 61 (Fig. 6~. The transmission is enabled by sigIIal CK2 present on wiré 17.
In case of reading in memory, RT3 transfers towards cor-rection Iogic LC ~Fig. 3~ both the inormation (wires 62~ and redun- -danc~ bits (wires 63) so that LC ~nay ef~ectuate check and correction ZS operations.
F~l denotes a conventional flip-flop controlling the "hand shaking" in reading, between the n~emory and the controller, that is the dialogue necessary to the correct transfer of the data read in the memo ry.
Whenever FE'l receives from the time bas~, through wire 16, a pulse of signal C;Kl, FFl ernits on wire 51 towards the control-ler a signal indicating that a datum read in the me~ory is ready to be transferred to the controller and hence that a reading is in pro-3.~

gress; the signal is also sent to memory ROM3 (Fig. 4) of BT.
FFl is reset to ~ero when a signal, confirming the ocsur-red data acceptation, arrives from the controller through wire 25 (Fig- 6~
References FF2 denotes a second flip-flop, identical to FFl, clesigned to control the "hand-shaking" in writing between the memory and the controller, that is the dialogue necessary to the correct trans-fer to the memory of the data supplied by the processor.
Whenever FF2 receives fro~ controller C' (Fig. 1), through 10 wire 26, a signal indicating that the datum is valid, i. e. that it must be really written, FF2 emits on its output 52 a signal indicating that a datum coming frorn the processor is ready to be transferred to the - m emo ry .
In ~ddition, FF2 is reset to zero by the trailing edge o 15 enabling-to-write signal W:E, coming from the time base through wi r e 15 .
The signal present on wire 5Z (which with wire 51 forms connection 5 of Fig. 4) is sent to both rnemory ROM3 af the time base as "ready datum" and the controller, which thus is informed if the ~ ~ 2i) operation i9 still in progress or is completed.
;~ Fig. I represents by way of example a correction logic ~- based on the Hamrning code and using five redundancy bits, which al-lows the correction of single errors on words presenting at most 31 bits, considering also the redundancy bits. The description refers to ZS the considered example, i. e. words with 16 information bits, In the drawing, reference GH denotes the generator of such redundancy bits, that advantageously consists of a set of 5 parity generators to which the sixteen wires 6Z are duly connected.
Output 61 of GH is connected on one side to RT2 (Fig. 6) 30 and on the other to an input of a comparator CM3 consisting for in-stance of exclusive-OR circuits; a second input of CI\/13 is connected to wires 63 conveying the redundancy bits read in the memory.
Output 9 o CM3 presents five bits that with their logic :~ 3~

~ 17 -value denote whether the bits present on wires 61 and 63 are equal or not. These five bits constitute an error code indicating the incor-rect information bit; taking into account that the memory i6 organiz-ed by bits and that a bit of a word for each rnodule is stored, the er-5 ror code indicates also the failed module.
Output 9 of CM3 is connected on one side to a register RE10,timed by C:Kl, whose output 92 is connected to the controller and con-~eys the informatlon relative to the failed module.
On the other side output 9 of CM3 is connected to an input 10 of a decoder DE which on the basis of the bits of the error code pro vides on output wires 91 sixteen bits whose logic value indicates the possible error o a corresponding infor~nation bit. Wires 91 are CDn-nected to an input o a corr~cting device CR, advantageously consist-ing of exclusive-OR circuits, whose second input is co~ected to 15 wires 62. The output of CR is composed of wires 60 on which the cor-rected bits are present.
As the memory is organized by bit6, any failure of the module ~}nemory integrated circuits or addressing unit) gives rise to an error in the unique ~utput bit of the module; therefore, when CR
20 corrects th?t bit, it corrects also any error of the rnodule (self-cor-rection with high coverage).
A fu~ther output 90 of DE2 carries the information on the presence or absence of error~, and is connected to a register RE8 tirned by CKl. The output of RE8 is connected to the controller through 25 a wire 6.
The structure just described is sufficient to detect and to correct the memory errors. For detecting possible malfunctions of logic LC and unit IU (Fig. 3), logic LC can comprise a further com-parator GM4 (Fig. 7), having an input connected to the output of CR
30 and another one to bus 8. Then C;M4 compares the bits corrected by LC to those present on bus 8 after correction. The output of CM4 is connected to a register RE9 activated by the trailing edge of CKl (denoted by CKl) or of WE (denoted by WE); the output of RE9 (wire 3L~9 3 ~2~!~3 7) is connected to the controller.
A further perforrnance of correction logic LC may be ob-tained by storing in RE10 not only the error code present on wires 9 and indical:ing the incorrect bit of a word, but also the address part 5 present on wires 11: this allows the detection o the memory circuit that originated the error and the sending of the relative information to the controller.
Obviously, by utilizing a greater number of redundancy bits and/or a code different from the Hamming code, multiple er-10 rors can be detected and connected.
The Inode of operation of logic LC is as ollows.
First considering a reading in the memory, the informa-- tion bits coming from a memory module on wires 100 (Fig. 6) are sent through wires 62 to generator GH (Fig. 7), whilst the redundan-- 15 cy bits presen~ on wîres 101 are sent through wires 63 to CM3~, that that compares them to those present on wires 61. (It is to be noted that in read phase the transmitters of RT3, Fig. 6, are disabled, .. . .
thus the bits present on wires 61 caImot come back to wires 101).
Possible errors, recogni~ed as discrepancies between the corre-20 sponding bits on the two inputs, are indicated by the presence of one or more 0 9 on wires 9.
The signals present on wires 9 are sent to DE2 that, on - the basis of the location of 0 s in the output configuration of CM3, identifies the information bits resulting incorrect and emits on wires 25 91 sixteen bitst each one associated to an iniormation bit. In the presence of an incorrect bit, the corresponding bit will have a logic - value such as to cause in CR the inversion of the logic value of said incorrect bit and then its correction.
The corrected bits are then sent to the transmitter of RT2 30 (E'ig. 6) and hence to the controller. In case of read-modify-write mode of operation, as also the transmitters of RT3 are enabled, the corrected bits presented by RT2 on bus 8, can be transferred on v,~ires 100 and then sent to the memory.

':

~'~ 3;~

In case of presence of coInparator CM4 (E`ig. 7), the cor-rected bits present on wire 60 are compared to those arrived at RT2 (Fig. 6) through RE7 and presented on bus 8; in this way the good operation of RTZ and bus 8 is verified. The result of the cor~-5 parison is sent, as stated, to the controller.
During writing, the information bits coming from the con-troller still arrive at GH (Fig. 7) through RT2 (Fig. 6)J bus 8, RT3 and wires 62, and the redundancy bits generated in GH are se~t to the memor~ via wires 61. As the transmitters of RT2 are disabled, 10 the bits present on wires 60 cannot be transerred to the controlle-l.
If ~omparator CM4 is present, the bits on wires 60 can be ~- compared to those really transrnitted by the controller and present on bus 8; a possible discrepancy will point out possible failures in LC; the anomalous situation will be put into evidence to the control-lS ler through register RE9.
Figures 8a, 8b, 8c, 8d show the behaviour of some of timing or conditioning signals in the various modes of operation of the memory, such as: refresh, read, write, read-modify-write.
The signals that in a certain operation are always at 0 20 have not been represented for said operation.
As to the output signals from BT, transfer signals have not been represeTlted as they are not functional for the description of the mode s~f operation.
Shift signal ~P1 presents a pulse that has always the min-25 imunl poss;ble duration permitted by the fundamental clock signal(one period of CK0) and always appears at the beginning of the pe~
riod of signal ~1 that, as already said, defines the time available in the Inemory for each bit (cycle).
Signal ~2 presents a pulse delayed with respect to pulse 30 ~1 to an extend dependent on the kind of operation, and has the min-imal duration with the exception of the read-modify-write operation, where two operations are necessary for the same rnemory cell.
As to the other signals emitted by BT, WE is obviously 3~ 3 - ~o -active only during the operation phases establishing memory writ-ing and it presents a pulse with constant deviation but variable posi-tion; sigl~al CKl is ac~ive during ~rite, read,read-modify-write modes and presents in all these cases a pulse of constant duration and po-S sition; signal CK2 is active in the sa~ne cases as WE and presents aconstant duration pulse such that it overlaps the pulse of WE, what-ever its position may be.
In addition, references DPR, DPW of Fig. 8 denote the signals of "ready datum" in reading and writing!present on wires Sl, ;~ 10 52 (Fig. 6) which denote, by passing to 0, the completion of arl op-eration; reference A - B denotes the signal whose logic level 1 cha-racterizes the equality between sequential addresses generated by CNO (Fig. 4) and CP (Fig. 5); reference FL denotes the signal of the reading end coming from the controller on wire 25 (Fig. 6); re-15 erellce DV denotes the signal coming from the controller on wire 26 and indicating that a datum to be ~vritten is ~alid.
It will be noted that signal CKO is represented only for the refresh mode.
The mode of operation of the device according to the in-20 vention will now be described separately for the four types of pos-~ible operations, that is: information refresh, read, write, read-modify write modes.
For this description reference will be made also to the diagranls of Fig. 8, supposing, by way of example, that undarnent-25 al clock signal C;K0 has a period of 100 ns, and that shift signals

2 have a period of 400 ns in ca~e of fast shift and of 800 nsin case of slow shift.
1) Refresh mocle .
This phase is controlled by the time base when the me-30 mory is not used, that is nor reading or writing is required by con-- troller C ' (Fig. 1 ) .
Under these conditions there is no output signal from gate Pl of IN (Fig. 5), thus all memory circuits AC (Fig. 2) are .
.

: , , ~ __. 3 ~3 ~ ~ 3 disabled by decoder DEl. In addition also signals WE, CKl, CK2 are at 0, so that tranceivers RTl (Fig. 2), RT2, RT3 (Fig. 6) are not enabled and no bit loading or unloading is possible in clrcuits ~C.
Hence these circuits receive from the control moduie on-ly the shift and transfer signals, that on this occasion have maxim-um period.
Under these conditions the bits stored in the registc:rs are recirculated continuously, thus allowing the information keep-1 0 ing.
2) Kead mode ~ .
A read operation can be considerecl as formed of two phases: data search and transfer.
Th~e first phase begins when controller C' (Fig. 1~ acti-lS vates the reading signal (wire 20, Fig. 4) possibly signalling to ad-dress control device IN (Fig. 3) the address of the first word in-volved in the operation, and ends when the time base generates the address where said word is stored; the second phase begins at that instant ancl terminates when the transfer is over.
Of course there will be no search phase i the initial ad-dr~ss signalled by the controller is the one on which the memory is located.
The following description is refelred to the most gener-al case in which the read operation comp~ises both phases.
This being stated, when the controller requests the read ing, it can send to CP (Fig. 5) both the initial adclress and cornmand for storing such an address, and to P2, ROM2 (Fig. 4) and RT2 tFig. 6) the indication that a read operation is requested (signal K
at 1 on wire 201).
Under this assu~nption, the address supplied by CP (Fig.
S) is different fro~ the one of CNO (Fig. 4); the output signal of C:M2 (Fig. 5) signals this situation to KOM2 and ROM3 (signal A =
B at 0, Fig. 8b) which put them selves in search phase and gener-ate signals ~1 to ~4~and CKl with a period and shape typical of this phase. More particularly, ~ 2 have the minimum period and CKl is at 0 (Fig. 8b).
These conditions are valid till the cyclical counting of 5 CNO (Fig. 4) generates, as next state of ROM1, the sa~le ad-dress denoted by CP (Fig. S). This condition is supposed in coinci-dence with the second pulse of ~2 in Fig. 8b. At the end of the sub-;~ sequent pulse of ~1 (pulse 3), memories ROM2, ROM3 find address coincidence (signal A - B at 1), no operation in progress (signal 10 DPR at 0) and a reading request: consequently, they locate them-selves in a state corresponding to the actual read phase, i. e. ~Pl, ~Z recover a maximum period and the pulse Gf CK1 can be emitted.
As the reading signal is always present on wire 201,trans-mitter RT2 (Fig. 6) and gate P1 (Fig. 5) are enabled to let through 15 the signals present at their inputs, whilst the transmitters ~f RT2 (Fig. 2) are enabled, as CK2 is at 0.
Furthermore, the passage to 1 of signal A = B present on wire 14 (Figs. 2, S) enables decoder DEl of all memor~r modules, that decodes the address bits present o~ wire 11 and then enables one 20 Of the 32 circuits A(:, e. g. ACl, in all rnodules ME, At the subsequent passage to 1 of dS2 (pulse 3, Figure 8b) the output registers of a same block of circuits AGl of all the mod-ules present at the output the bit stored in their last cell.
In each module, the bit read in circuit ACl is sent through 25 wire 10b to the transrnitter of RTl that sends it on the respective wire 10; the bits present On all wires 10 of the memory uni~ repre-sent the word read in the merllory and sent to the control module.
In particula.r the bits read in the memory are transferred to correction logic LC (Figures 3, 7) for check and possible correc-30 tion.
Corrected bits and error signalling, present on wires hOand on wire 90 respectively, arrive at the input of registers RE?
(Fig. 6) and RE:8 (Fig. 7) and~ as soon as CKl passes lo value 1, , ' ;, ~ 3Q3~3 they are presented on wires 220 and 6, respectively. Meanwhile, at the end of pulse 3 of ~2, counter CNO (Fig. 'L) is advanced by one step, thus it marks an address different from CP (Fig. 5)~
When CKl passes to 1 (Fig. 8b), also counter CP (Fig. 5~
5 advances by one step, thus the addresses are equal again (supposing the comparison occurs between bits of the same weight); besides, DPR (Fig. 8b) passes to 1 and there remains till signal of end of reading FL arrives to FFl (E~ig. 6).
If such a signal arrives before the end of the subsequent 10 pulse of ~1 (pulse 4~, that is if the controller has stored the data within the 400 ns elapsed between the passage to 1 of CKl and the passage to 0 of ~1, the same situation present at the endof pulse 3 oc- -curs and then the operat;ons are repeated as in the preYious cyclc for the next word to be read.
Then this procedure goes on unchanged till the controller takes away the read cornmand either because the whole block of words has been read or because CP (Fig. 5) has signalled the end of its count-ing capacity.
Then the system cornes back to the conditions already de-~0 scribed for the information "refresh".
In case control1er C' was u~able to store the first wordwithin the predicted time, at the ~nd of pulse 4 of ~1, signal FL has not yet arrived, and so DPR is still at 1, as denoted by the broken line in Fig. 8b. In this situation the emission of CKl is not enabled, 25 thus at the arrival of pulse 4 of ~2, when the time base advances again by one step, address discrepancy between CNO (Fig. 4) and CP (E`ig. 5) will occur. The timebase restores itsel in search phase till the address iderltity is ound again.
The paftsage to a search phase can occur either when the 30 signal of reading end arrives, or as soon as the address discrepan-cy is found. It i9 evident that in case of very slow control syste~ns requesting some periods of ~1 to store a word, the second solution can allow the operations to be sped up.

~1 3~

It has to be remembered that, owing to the structure of the memory, the period of ~1 cannot be lengthened beyond a certain limit, because it rnay happen that the control system is unable to store the data within the a~ailable tirne.
It is clear, however, that the data do not get lost because a new operation cannot begin if the previous one is not completed (CKl is at 0 if DPR is not at 0 before the end of the pulse of cPl).
Under the conditions described above (that is controller unable to accept the data within a period of ~1) the next address equality c:an occur only after a time depending on the way the inputs of CM2 (Fig. 5) have been connected to wires 3 and 18. If the connec-tion is such that the bits with eq~Lal weight are corrlpared in the two addresses, reading will be possible only after that the time base has scanned again the addresses of the 4096 cells of a block. If, on the contrary, the wires are connected so as to compare the bits with different weight in the two addresses, a more frequentreading is possible. For instance, if the controller requires a reading time comprised between 1 and 2 cycles, the least significant bit of the time base can be compared to the most significant one of the word counter; the second bit of the time base can be co1npared to the least significant one of the counter of word~, the third bit of the time base ean be compared to the second bit of the counter and so on; in this way there is address equality every two cycles and so the optimi3a-tion of transfer speed. Analogous procedure can be followed in cases 25 where the controller requires for instanee 4, 8 . cycles for read ing; then it will be enough to shift the ~,vires by two, thre~positions.

3) Writ~e mode The write operations are basically carried out by follow-ing the same procedures adopted for read operations, that is when the write command arrives frolrl C' (Fig. 1), the search of the first address begins, and then the actual data transfer. The search phase is identical to the read phase, with the only e~ception that the enabl-ing s;gnal for gate Pl (Fig. 5) of IN arrives through vire 202 and not ~ 3.~ 3 - ~5 -ire ZOl. When the addresses have been established equal (for in-stance again during the second cycle of ~1), at the end of the subse-quent pulse of ~1, DPW is at 1 (supposing the controller has ~urnish-ed the first character to be written at the ~noment of the writing re-5 quest), signal ~ = B is at 1 and obviously the signal of writing re-quest (not shown) is at 1. Under these conditions, ROM2, ROM3 dis-pose the~nselves in the state corresponding to writing, wherein, as stated, WE and CK2 will be active and the pulse of ~2 is slightly more delayed with respect to the one o ~1 than it happened during 10 reading (for instance 200 ns insteacl of 10a) in order to allow a better rnatching of the operation in the cycle.
At the passage to 1 of CK2, transmitter RT3 (E'ig. 6) is enabled to let through the bits present on bus 8 and to transfer them on wires 100 towards transceiver Rl'3 (Fig. 2) of the memory mod-15 ules MEl . . . MEhtin each module, the arrived bit is presented onwire 100. From b~ls 10a. From bus 100 (Figo 6) the information bits are transferred also through wires 62 to the correction logic that generates redundancy bits and transrnits them to RT3 that in turn, presents thern on bus 101 (Fig. 6) and sends them to memory modules ~0 MEl . . . MEp. The next passage to 1 of WE and of ~e2 enables in sach memory module the input registers of circuit ~G (Fig, Z) ex~ablod by DEl to store actually the bit arriving on wire lCa and in addition ad-vances CN0 (Fig. 4) by one step.
At the passage to 1 of WE, signal DPW is put to 0 so that 25 the controller may be ready for the subsequent operation. In addition, if logic LC (Fig. 3) cornprises comparator CM4 (Fig. 7) and register - RE8, the possible presence of malfunctions in the transceivers and bus of IU or logic itself is signalled to the controller.
At the passage to 0 of WE, signal CKl passes to I, thus 30 advancing by one step counter CP (Fig. 5): address eq~lality is again - reached. If, before the end of the cycle, the new signal of valid dat-um DV (Fig. 8c) that restores to 1 signal DPW, arrives from the controller, the conditions necessary to writing are again reached;

3~

writing will take place during the subsequent cycle following the same procedure.
If thi3 signal of ~alid datum does not arrive before the be-ginning of the cycle during which the write operation is to be carried out (for in~tance with reference to Fig. 8c, before the beginning of the cycle identified by pulse 4 of di 1), at the arrival of such a pulse, DPW would be at 0. Under these conditions (denoted b~r a broken line in Fig. 8c), signal WE remains ~t 0 so that the operation is not car-ried out; as a consequence CKl remains at 0~ CP (Fig. 5) is not ad-10 ~anced, and at the subsequent cycle the addresses generated by CN0 (Fig. 4) and CP (Fig. 5) (supposing the comparison occurs between bits with equal weight) will not be equal, thus preventing again opera-tions from being carried out. Also in this case, the above mentioned considerations related to read operations for connecting the wires of lS connections 3 and 18 (Fig. 5) with the inputs of CM2, remain valid.
Obviously, if DV does not arri~e even if delayed, the me-~nory enters the refresh state. Such situation is no$ represented in Fig. 8c.

4~ Read-modifv-write mode This type o:E operation allows the rewriting in the m~mory of the data corrected in the correction logic; the relative information is supplied to the time base by l:he simultaneous presence of signals ~, W.
In this type of operation ~ 2 are at ma~imum period 25 (Fig. 8d); ~2 passes to 1 as for the reading but it remains at 1 till about the end of the cycle (for instance 100 ns before the end). In this way the memory is preset to carry out two operations for the same cell. Signal CKl has tilI the sarne behaviour as described ~or read and write modes.
Signal WE passes to 1 short after CKl (for instance after 100 ns) and remains at I till the end of the cycle. Signal CK~ will be superimposed on WE as for writing and passes to 1 with CKl, com-ing back to 0 at the end of pulse ~1 of the subsequent cycle.

~-3 .~

In this kind of operation, while ~Z is at 1, both signals CKl and WE (and then CK2) are at 1 for a certain time; consequent-ly the data can be transerred to both the controller and the memory;
more particularly, the corrected data supplied by the correction log-ic through wires 60 are presented by RE7 on both wires 220 and bus 8 (as in read mode) and in addition can pass from such a bus onto wires 100 and 61 (as in write mode) and can be sent to both ME and the correction logic in order to generate redundancy bits.
In this type of operation, as shown in Fig. 8d, the dialogue on the controller side appears to be slaved only to the ready dat~u~
in reading (DPR) and to the end of reading signal FL, whilst signals DPW and DV are disregarded and hence not represented.
Obviously the considerations already applied for reading and writing may be applied, also to said case, if the controller i5 slow with respect to the memory.
The embodiment described with reference to Figures 1 to 8 relates to the case of words contai;ning, besides the information bits, only the minimum number of redundancy bits necessary for self-correction. Nevertheless, the bit organization of the memory allows a certain flexibility in the nurnber of both information and re-dundancy bits.
The ~rariation of number h of inforrnation bits involve~ on-ly the changement in the number o both men~ory modules ME (Fig.
1) intended for saidbitsand connection wires 100 (Fig. 6). This hap-pens where the number of information bits added to the number of redundancy bits is lower than the number of bits checlcable by the established redundancy bits (in our case, five redundancy bits can control 31 bits, then the infor~nation bits can increase up to 26 with-out involving an increase in the redundancy bits). Obviously, the num-ber of information bits can exceed said value involving also the in-crease in the number of redundancy bits and related memory mod-ules.
The variation in the number (p - h) of redundancy bits (it ~ ~3 t~

can be also carried out independently of the increase in information hits) will involve the variation in the number of both related memory modules ME (Fig. 1) and connection wires 101 (Fig. 6~, added to the variations inside blocks GH, CM3, DE2 (Fig. 7) of correction logic LC.

In particular, if Hamming code is always used for the cor-rection, the words to be stored can contain 16 information bits and 6 redundancy bits: this allows the detection also of double errors.

A further possibility offered by the bit organization con-sists in providing, besides modules ME(i) ... ~E(p) intended to store the redundancy bits necessary for the self-correction, one or more spare modules, that is one or more modules inten-ded to replace one or more failed modules through a reconfigu-ration. This reconfiguration involves also a new initializa-tion of the memory i.e. the writing in the spare module of the data contained in the substituted module.

This embodiment, described with reference to Figures 9 to 11, presentsgreat reliability advantages and allows the restora-tion of the memory system without service interruptions.

Fig. 9 shows a memory unit MMi still presenting as in caseof Fig. 1 a control module MC and memory modules ME(l) ...
MEth) for information bits and ME~ .. ME(p) for self-correction bits, and in addition~ a module ME (p~l) capable ~5 of functioning as a spare for one of modules ME(l) ... ME(p) is provided.

The addition of module ME (p~l) implies that module MC, and in particular input-outpllt unit IU, should also contain switching circuits that in case of a failed memory module allow the sending of the bits intended for the damaged mo-dule to the spare module and to the controller of the bits coming from the spare module instead of those of the failed module.

,, , ~, :

', 3~3 These switching circuits are denoted by PS in Fig. lO and are connected on one side to wires lO0, lOl already descri-bed referring to Fig. 6, and on the other to the memory modules through wires lO(I) ... lO(h), lO(i~ ... lO(p)/
10 (p~l).

An embodiment of circuit PS is shown in Fig. ll. In this Figure, MX(l) ... MX(h~, MX(i) .~. MX(p), MX(p+l) denote conventional multiplexers with three state output such as those sold under the trade mark "TRI-STATE"; BU a se~ of three state or open collector buffers, enabled by signal CK2, connected on one side to wires lO0, lOl and on the other to wires lO and carrying out functions similar to those of transmitters RT2, RT3 (Fig. 10).

The term "three state" mean~, as known to technicians, that, besides the two usual logic levels, a third state with high impedance output is possible. This allows the use of bi-directional transmission lines for the connection bet~een control module and memory modules.

Each multiplexer MX(l) ... MX(p) presentstwo inputs and an output: the first input of each multiplexer is connected - to the memory module with the same index, through respective wire 10, the second input of all the multiplexers is connec-ted to spare module ~E(p~l) through wire lO(p+l).
,~
Multiplexers MX(l) ... MX(p), which are enabled during me-mory reading (absence of signal CK2), are normally set on their first input.

The possible switching on the second input, in case of fai-lure or conditions described hereinater, is controlled by a respective select signals s(l) ... s(h), 5 (i) . . . s (p) coming from a decoder DE3 receiving and decoding a bit con-figuration sent by the controller through a connection 27 and indicating which memory module should be replaced by the ,, .
,;

~3~

-29a-spare module. Therefore, this bit configuration acts as a switching command.

Multiplexer MX(p+l) is provided with an output connected to spare module ME(p~l) through wire lO(p~l) and p inputs con-nected to wires 100(1) ... lOO(h), lOl(i) ... lOl(p), res-pectively. MX(p~l) is provided with an additional input, connected to a wire 102; as advantage this input can be steadily connected in parallel to one of the other p inputs, e.g. to input 100(1), and it is connected 0.................

:~ 3 '~3 to output lO(p~l) under usual operation conditions of the memory.
If data of module ME(l) are stored in module ME(p~
since the beginning of memory operation, this embodirnent allows that correction logic LC controls also spare module ME(p+l), as

5 described in the following.
Multiplexer MX(p+1~ is enabled during write modes by signal CK2; the switching among its different inputs is controlled by the bit pa~tern present on connection 27.
The scheme of Fig. 11 refers to case of only one relia-~æc~
~- 10 bility spare module ME(p+1). If several spare modules are rcquest-ed, some variations to PS structure arenecessary and in particular~
- each spare module is connected to both a multiplexer similar to MX(p+l) and an additional input of ~ultiplexers MX(1) .. . MX(p);
- the bit pattern conveyed by the controller on connection 27 must indicate the identity of the da~aged ~odule or modules as well as the expected reconfiguration scheme.
Then, decoder DE3 can be replaced by a read-only me~
mory, addressed by said bit pattern.
In the particular case of only two ~pare ~nodules, two de-20 coders, similar to DE3 and each connected to one of the spare mod-ules, can be sufficient.
The operation of the invention, according to the embodi-rnent shown in Figs. 9 to 11 is substantially similar to the emhodi-ment of Figs. 1 to 7, till a reconfiguration is not requested.
The only variation consists in the fact that, during read x~lodes (absence of signal CK2), the data read in the memory reach j~ transceiver RT3 (Fig. 10) through ~$~F~MX(l~ . . . M~(p) ~Fig. 11) set on their first input, while, during write modes~ the data outgoing from RT2 (Fig. 10) are sent to the n~emory through 30 buffer BU (Fig. 11): urthermore, if multiplexer MX (p-~l) is pro-vided with a "rest" input connected as input 102, the data concern-ing for example module ME(l) are written also in spare module ~3,~3~

M E(p+ 1 ) -l~s to reconIiguration, a distinction is necessary between an effec$ive reconfiguration, entailed by a mernory error, or a fictitious reconfiguration, r equested by the controller, only for 5 supervision purposes of the correct operation of the pare module.
The second case is firstly described; this reconfiguration is allowed by both the presence and the particular connection vf (p+l)-th input of MX (p+l) (wire loz3, assumed to be steadily con-nected to wire I 00(1 ) .
This fictitious reconfiguration irnplies that the controller conveys on connection 27 a bit configuration entailing MX(p+l) switch-ing from input 1()2 to input l00(l); furthermore, this bit configura-tion is decoded by DE3, which emits signal s(l) and entails MX(l) switching on the input connected to ME(p+l).
The reconfiguration is only fictitious, bec~use, as ~l-ready said, ME(1) and ME(p+l) present the same data.
Nevertheless, during the read mode, data are taken from ME(p+l) rather than from ME(l) and are controlled and possibly corrected by LC (Fig. 7), as already described with reference to 20 the embodiment shown in Figs. 1 to 7. Obviously, no variations occur in read modes.
In case of effective failure, the identity of the faulty module is sent to the controller by LC (Fig. 7) through register RE10 and wire ~2. On the basis of said information, the controller 25 sends on connection Z7 (Fig. 11) the switching order.
If the failure occurs in module ME(1), the situation al-ready described for the fictitious reconfiguration occurs, On ~the contrary, if the failure occurs in a module dif-ferent from ME(l), for instance ME(h), DE3 emits signal s(h) and 30 entai1s MX(h) switching from the first to the second input.
As spare module ME(p+l) does not contain the same data of ME(h), the system should be initiali~ed again, i. e. the me-mory should be rewritten,so a3 ME(p+l) contains the requested .
.

~3~3 data .
From now on, the operations are repeated in an unchang-ed way. The new initialization can be avoided in some particular cases, when, for example, the memory is cyclically written: the data read on the spare module are automatically corrected by LC
(Fig. 7) and rewritten into ME(p-~l) Fig. 9) within a memory cycle.
This procedure presents a disadvantage; in fact, if the correction logic allows only the correction of an error at a time, all its correction capacity would be engaged for the reconstruction of the correct data as long as the spare module is not rewritten: if an error occurs in another module, the correction logic could not intervene and the system would be out of order.
Fig. 12 shows a possible embodiment of a fully redun~
dant memory unit MM, presenting not only spare memory modu-lS les, but also se~reral control modules, The full redundancy allows an impro~ement in the re-liability per~ormance of the mass-memory, as also the errors of the control modules can be corrected.
Memory unit MM, shown in Fig. 12, includes three con-trol modules MCA, MCB, MCC and x memory modules. A certain number p of these memorr moclules is intended, as in Fig. 1, to store both information bith and redundancy bits necessary for sel~-correction, the remaining x-p modules are spare modules. Control modules MCA, MCB, MCC still contain time base BT, addressing 2S control device IrJ, correction logic LC and input-output unit IU
(equipped with the switching points), as in the embodiment of the unique control module; furthermore, each module MC comprises a respective synchronization logic LSl, LS2 or LS3 connected to both time base BT of the same control module and synchronization logics of the other modules, able to synchronizc the thr~e time bases.
The triplication of a time base forreliability purposes is known to the technician6 o the art; an exarnyle is described in ~1 33~43 our U. S. Patent No. 4,096,396, issued June 20, 1978.
The three control modules are connected both to the controller through the respective bidirectional connections lor pairs of unidirectional connections) 2A, 2B, 2C and to all the memory modules through wires or connections lO(l)A ...
lO(x~A, llA, 12A, 13AJ 14A, 15A (and lO(l)s to 15B and lO(l)C
to 15C, respectively), corresponding to wires and connections 10 to 15 described with reference to the previous embodiments.
For sake of simplicity, wires and connections 2, 10 to 15 are connected generally to blocks MC and not to MC de-vices, from which they really come.
The Figures shows also, for memory module ME(l), the changes made necessary by the triplication of the control mo-dule. In particular, the ~ive terns of wires`and connections . 15 ll(A, B, C), 12 (A, B, C), 13 (A,~B, C), 14 (A, B, C), 15 (A, -~ B, C) reach as many sections of a majority logic LMl; each -~ section emits as output a signal similar to that present at two inputs, at least Outputs 11, 12, 13, 14, 15 of logic LMl are the inputs of module ME, shown in Fig. 2, denoted by the same references.
; Wires lO(l)A, lO(l)B, lO(l)C are connected to three transceivers RTlA, RTlB, RTlC (equal to transceiver RTl of Fig. 2); they send the signals to be written into the memory to the three inputs of a second majority logic LM2, which emits the signal present at two inputs, at least; output lOa of LM2 corresponds exactly to output lOa of transceiver RTl of Fig. 2.

The data read in the memory and present on wire lOb are sent, at the same time, to three transceivers RTlA, RTlB

~,,,.~

~ .

:~ 33~3 .
-33a and RTlC and on their turn to the respective contxol modules MCA, MCB, MCC.
The statement relative to memory module ME(l) holds, obviously, also for all the other memory modules: each module 5 presents a first majority logic, which receives the five terns .
;of wires or connections ll(A, B, C~ to 15(A, B, C), three transceivers which - - -~ .

`,' , ~ ` ' ~3 ~ 3~

- 3~ -receive the three wires 10 relative to that module ancl a second lag-ic downstream the three transceivers.
Several modifications and changements may be introduced in the reali~ation of the device herein described without going out S of the frame of the invention.
In particular, we referred to bidirectional transmission lines for the signals read in the mernory or to be written in the me-mory. I~ different lines are used for the two transmission directions, transceivers RT2, RT3 of input-output units IIJ (Figures 6 and 10) 10 would be no more necessary; furthermore, in case of the units of 3~ Fig. 10, switching point PS would not entail any more the presence of buffer BU (Fig. 11) and the use of t-}~t-e components.
The simplification s)f input-output unit, allowed by the use c)f unidirectional transrnission lines, would be balanced by the im-15 possible op~ration control of IU through circuits CM4 and RE9 of ; Fig. 9, which can operate because of the coupling between the two transrr~ission directions j-~st allowed by RT2 and RT3 (Figs, 6, 10).
,~, Therefore, the technician should estimate each time the most useful e~nbodirnent, i. e. uni.or bidirectional lines.
Furthermore, Fig. 12 shows an embodiment with tripled control module, being self-corrective also for control equipment.
Different redundancy em~odiments would be also possible, for instance, with only duplicated control module; this embodiment entails a supervision of the reconfigur~tion which often implies other equipments and thus other complex circuits.
If the added equipment does not detect the failures, the two blocks sho~ld detect their failures; this entails a further duplication of each block to obtain a self-~;agnosis with a sufficient coverage and in short times.

Claims (4)

THE EMBODIMENT OF THE INVENTION IN WHICH AN EXCLUSIVE PRO-PERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A self-correcting and reconfigurable solid-state mass-memory organized in bits, having a least one memory unit comprising a first group of memory modules each adapted to store one bit of each of a plurality of words consisting of information bits and redundancy bits enabling self-correction, one or more spare memory modules which in case of failure replace one or more modules in the first group, and control means controlling the exchange of data between the memory unit and a control, said control means generating timing and addressing signals for the memory unit, super-vising the operation of the memory unit by detecting and correcting errors and comprising switching means for swit-ching out a memory module in the first group upon failure and switching in a spare memory module in its place; wherein said control means comprise triplicate control modules and each memory module comprises three data transceivers, each connected, on one hand, to one of the three control modules through an associated data transmission line and, on the other hand, to all memory circuits in the memory modules and to one input of a first majority logic circuit, which recei-ves from each transceiver the bit to be written in the memory, as supplied by the associated control module and supplies to the memory circuit concerned a bit present on at least two out of three inputs of said first majority logic circuit; and a second majority logic circuit which has inputs in groups of three respectively connected to connections that, in three unidirectional buses transferring timing and addressing signals from associated control module to the memory module, convey homologous signals, the second majority logic circuit providing an output for each group of three inputs which receives the signal present on at least two inputs in the group, the outputs of the second majority logic circuit be-ing connected to means that allow the reception by the module of the timing and addressing signals.

2. A mass-memory according to Claim 1, wherein the or each spare memory module stores the same data as a memory module of the first group; and wherein said switching means com-prises decoding means responsive to a code signalling a fic-titious failure of said module to cause switching of the switching means and to allow control and correction of the data loaded in said spare module or modules.

3. A mass-memory according to Claim 1, wherein said swit-ching means further comprise a set of buffers inserted in the lines conveying the data to the memory modules, said buffers being enabled only in the write modes of the memory.

4. A mass-memory according to Claim 1, wherein the means that allow the reception by a memory module of the timing and addressing signals further comprise a decoder generating an enabling signal for one of a plurality of memory circuits in the memory module and buffers for amplifying said timing and addressing signals sufficiently for driving all memory circuits.