ATE131308T1 - Cmos-vorladungs- und ausgleichsschaltung. - Google Patents

Cmos-vorladungs- und ausgleichsschaltung.

Info

Publication number
ATE131308T1
ATE131308T1 AT91300349T AT91300349T ATE131308T1 AT E131308 T1 ATE131308 T1 AT E131308T1 AT 91300349 T AT91300349 T AT 91300349T AT 91300349 T AT91300349 T AT 91300349T AT E131308 T1 ATE131308 T1 AT E131308T1
Authority
AT
Austria
Prior art keywords
precharge
equalization circuit
cmos
pair
equalization
Prior art date
Application number
AT91300349T
Other languages
English (en)
Inventor
Thomas J Runaldue
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE131308T1 publication Critical patent/ATE131308T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
AT91300349T 1990-02-15 1991-01-17 Cmos-vorladungs- und ausgleichsschaltung. ATE131308T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/480,401 US5036492A (en) 1990-02-15 1990-02-15 CMOS precharge and equalization circuit

Publications (1)

Publication Number Publication Date
ATE131308T1 true ATE131308T1 (de) 1995-12-15

Family

ID=23907823

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91300349T ATE131308T1 (de) 1990-02-15 1991-01-17 Cmos-vorladungs- und ausgleichsschaltung.

Country Status (6)

Country Link
US (1) US5036492A (de)
EP (1) EP0442610B1 (de)
JP (1) JP2660454B2 (de)
AT (1) ATE131308T1 (de)
DE (1) DE69115075T2 (de)
ES (1) ES2081425T3 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2825291B2 (ja) * 1989-11-13 1998-11-18 株式会社東芝 半導体記憶装置
KR940007000B1 (ko) * 1991-05-24 1994-08-03 삼성전자 주식회사 개선된 라이트 동작을 가지는 반도체 메모리 장치
KR940001644B1 (ko) * 1991-05-24 1994-02-28 삼성전자 주식회사 메모리 장치의 입출력 라인 프리차아지 방법
US5325338A (en) * 1991-09-04 1994-06-28 Advanced Micro Devices, Inc. Dual port memory, such as used in color lookup tables for video systems
US5355343A (en) * 1992-09-23 1994-10-11 Shu Lee Lean Static random access memory with self timed bit line equalization
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
JP3088232B2 (ja) * 1994-01-11 2000-09-18 沖電気工業株式会社 半導体記憶回路
KR100543200B1 (ko) * 1998-06-15 2006-04-12 주식회사 하이닉스반도체 스태틱램의 비트라인 클램핑회로
KR100279058B1 (ko) * 1998-07-13 2001-01-15 윤종용 낮은 전원 전압 하에서 고속 쓰기/읽기 동작을 수행하는 반도체메모리 장치
JP4912621B2 (ja) * 2005-06-07 2012-04-11 富士通株式会社 半導体装置及び半導体装置の配線方法
US7564728B2 (en) 2005-09-29 2009-07-21 Hynix Semiconductor, Inc. Semiconductor memory device and its driving method
US7986577B2 (en) * 2007-03-19 2011-07-26 Hynix Semiconductor Inc. Precharge voltage supplying circuit
TWI334604B (en) * 2007-06-25 2010-12-11 Ind Tech Res Inst Sensing circuits of phase change memory
JP2014149884A (ja) * 2013-01-31 2014-08-21 Micron Technology Inc 半導体装置
GB2525904B (en) 2014-05-08 2018-05-09 Surecore Ltd Memory unit
CN115565567A (zh) * 2021-07-02 2023-01-03 长鑫存储技术有限公司 读出电路结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4494221A (en) * 1982-03-03 1985-01-15 Inmos Corporation Bit line precharging and equilibrating circuit
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
US4639898A (en) * 1984-12-21 1987-01-27 Rca Corporation Bit-line pull-up circuit
JPH0664907B2 (ja) * 1985-06-26 1994-08-22 株式会社日立製作所 ダイナミツク型ram
JPS62114190A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体記憶装置
US4712193A (en) * 1985-11-21 1987-12-08 Motorola, Inc. Current steering differential write circuit for memory cells
JP2615011B2 (ja) * 1986-06-13 1997-05-28 株式会社日立製作所 半導体記憶回路
JP2644261B2 (ja) * 1988-03-15 1997-08-25 株式会社東芝 ダイナミック型半導体記憶装置
JPH02198097A (ja) * 1989-01-25 1990-08-06 Nec Ic Microcomput Syst Ltd 半導体スタチックメモリ

Also Published As

Publication number Publication date
JP2660454B2 (ja) 1997-10-08
JPH04214294A (ja) 1992-08-05
EP0442610A3 (en) 1993-05-05
US5036492A (en) 1991-07-30
EP0442610B1 (de) 1995-12-06
DE69115075D1 (de) 1996-01-18
DE69115075T2 (de) 1996-06-27
ES2081425T3 (es) 1996-03-16
EP0442610A2 (de) 1991-08-21

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee